Octal 14-Bit, Parallel Input, Voltage-Output DAC AD7841

Transcription

1 a FEATUES Eight -Bit s in One Package Voltage Outputs Offset Adjust for Each Pair eference ange of 5 V Maximum Output Voltage ange of V 5 V % Operation Clear Function to User-Defined Voltage -Lead MQFP Package APPLICATIONS Automatic Test Equipment Process Control General Purpose Instrumentation Octal -Bit, Parallel Input, Voltage-Output AD78 GENEAL DESCIPTION The AD78 contains eight -bit s on one monolithic chip. It has output voltages with a full-scale range of ± V from reference voltages of ± 5 V. The AD78 accepts -bit parallel loaded data from the external bus into one of the input registers under the control of the W, CS, and channel address pins, A A. The outputs are updated on reception of new data into the registers. All the outputs may be updated simultaneously by taking the L input low. Each output is buffered with a gain-of-two amplifier into which an external offset voltage can be inserted via the DUTx pins. The AD78 is available in a -lead MQFP package. FUNCTIONAL BLOCK DIAGAM V CC V SS AB V EF (+) V EF ( ) AB DUT CD DUT AB AD78 DB3 DB INPUT EG EG A A INPUT EG EG B B A B A B W INPUT EG EG C C C C CS A A A L ADDESS DECODE INPUT EG EG D D INPUT EG EG E E INPUT EG EG F F INPUT EG EG G G G F D E D E F INPUT EG H EG H H G H EV. A V EF (+) GH V EF ( ) GH Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. V EF (+) CDEF V EF ( ) CDEF CL DUT EF DUT GH One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 78/39-7 World Wide Web Site: Fax: 78/ Analog Devices, Inc.,

2 AD78 SPECIFICATIONS (V CC = 5 V 5%; = 5 V %; V SS = 5 V %; = DUT = V; L = 5 k and C L = 5 pf to, T A = T MIN to T MAX, unless otherwise noted) Parameter A B Unit Test Conditions/Comments ACCUACY esolution Bits elative Accuracy ± ± LSB max Differential Nonlinearity.9/ ± LSB max Guaranteed Monotonic Over Temperature for All Grades Zero-Scale Error ± 8 ± 8 LSB max V EF (+) = +5 V, V EF ( ) = 5 V. Typically within ± LSB Full-Scale Error ± 8 ± 8 LSB max V EF (+) = +5 V, V EF ( ) = 5 V. Typically within ± LSB Gain Error ± ± LSB typ V EF (+) = +5 V, V EF ( ) = 5 V Gain Temperature Coefficient.5.5 ppm FS/ C typ ppm FS/ C max DC Crosstalk µv max See Terminology. Typically 75 µv EFEENCE INPUTS DC Input Impedance MΩ typ Input Current ± ± µa max Per Input. Typically ±.3 µa V EF (+) ange /5 /5 V min/max V EF ( ) ange 5/ 5/ V min/max [V EF (+) V EF ( )] / / V min/max For Specified Performance. Can Go as Low as V, but Performance Not Guaranteed DUT INPUTS DC Input Impedance 6 6 kω typ Max Input Current ±.3 ±.3 ma typ Per Input Input ange 3 /+ /+ V min/max OUTPUT CHAACTEISTICS Output Voltage Swing V SS +.5 V to V SS +.5 V to V typ = (V EF ( ) + [V EF (+) V EF ( )] D).5 V.5 V V DUT Short Circuit Current 5 5 ma max esistive Load 5 5 kω min To V Capacitive Load 5 5 pf max To V DC Output Impedance.5.5 Ω max DIGITAL INPUTS V INH, Input High Voltage.. V min V INL, Input Low Voltage.8.8 V max I INH, Input Current Total for All 5 C ± ± µa max T MIN to T MAX ± ± µa max C IN, Input Capacitance pf max POWE EQUIEMENTS V CC.75/ /+5.5 V min/max For Specified Performance 5 V ± % 5 V ± % V min/max For Specified Performance V SS 5 V ± % 5 V ± % V min/max For Specified Performance Power Supply Sensitivity Full Scale/ 9 9 db typ Full Scale/ V SS 9 9 db typ I CC.5.5 ma max V INH = V CC, V INL =. Dynamic Current I DD ma max Outputs Unloaded. Typically 8 ma I SS ma max Outputs Unloaded. Typically 8 ma NOTES Temperature range for A and B Versions: C to +85 C. Guaranteed by characterization. Not production tested. 3 See DUT Voltage ange section. The AD78 is functional with power supplies of ± V ±% with reduced output range. Output amplifier requires.5 V of head room at the bottom and top ends of the transfer for function. At V supplies it is recommended to restrict the reference range to ± V. Specifications subject to change without notice. EV. A

3 AC PEFOMANCE CHAACTEISTICS AD78 (These characteristics are included for Design Guidance and are not subject to production testing.) A & B Parameter Versions Unit Test Conditions/Comments DYNAMIC PEFOMANCE Output Voltage Settling Time 3 µs typ Full-Scale Change to ± / LSB. Latch Contents Alternately Loaded with All s and All s Slew ate.7 V/µs typ Digital-to-Analog Glitch Impulse 3 nv-s typ Measured with V EF (+) = +5 V, V EF ( ) = 5 V. Latch Alternately Loaded with FFF Hex and Hex. Not Dependent on Load Conditions Channel-to-Channel Isolation 99 db typ See Terminology -to- Crosstalk nv-s typ See Terminology Digital Crosstalk. nv-s typ Feedthrough to Output Under Test Due to Change in Digital Input Code to Another Converter Digital Feedthrough. nv-s typ Effect of Input Bus Activity on Output Under Test Output Noise Spectral khz nv/ Hz typ All s Loaded to. V EF (+) = V EF ( ) = V Specifications subject to change without notice. TIMING SPECIFICATIONS, (V CC = 5 V 5%; = 5 V %; V SS = 5 V %; = DUT = V) Parameter Limit at T MIN, T MAX Unit Description t 5 ns min Address to W Setup Time t ns min Address to W Hold Time t 3 5 ns min CS Pulsewidth Low t 5 ns min W Pulsewidth Low t 5 ns min CS to W Setup Time t 6 ns min W to CS Hold Time t 7 ns min Data Setup Time t 8 ns min Data Hold Time t 9 3 µs typ Settling Time t 3 ns max CL Pulse Activation Time t 5 ns min L Pulsewidth Low NOTES All input signals are specified with tr = tf = 5 ns (% to 9% of 5 V) and timed from a voltage level of.6 V. ise and fall times should be no longer than 5 ns. Specifications subject to change without notice. A, A, A t t CS W t 5 t 6 t 3 t t 7 t 8 DATA t 9 t CL t L Figure. Timing Diagram EV. A 3

4 AD78 ABSOLUTE MAXIMUM ATINGS, (T A = 5 C unless otherwise noted) V CC to V, +7 V or +.3 V (Whichever Is Lower) to V, +7 V V SS to V, 7 V Digital Inputs to V, V CC +.3 V V EF (+) to V EF ( ) V, +8 V V EF (+) to V SS.3 V, +.3 V V EF ( ) to V SS.3 V, +.3 V DUT to V SS.3 V, +.3 V (A H) to V SS.3 V, +.3 V Operating Temperature ange Industrial (A Version) C to +85 C Storage Temperature ange C to +5 C Junction Temperature C MQFP Package Power Dissipation (T J Max T A )/θ JA θ JA Thermal Impedance C/W Lead Temperature, Soldering Vapor Phase (6 sec) C Infrared (5 sec) C ESD > V NOTES Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents of up to ma will not cause SC latch-up. 3 V CC must not exceed by more than.3 V. If it is possible for this to happen during power supply sequencing, the following diode protection scheme will ensure protection. V CC IN8 HP58-8 AD78 V CC ODEING GUIDE Linearity Temperature Error DNL Package Package Model ange (LSBs) (LSBs) Description Option AD78AS C to +85 C ±.9/+ Plastic Quad Flatpack (MQFP) S- AD78BS C to +85 C ± ± Plastic Quad Flatpack (MQFP) S- PIN CONFIGUATION DUT_AB A PIN IDENTIFIE 33 DUT_GH 3 H V EF ( )AB 3 3 V EF ( )GH V EF (+)AB 3 V EF (+)GH V SS L AD78 TOP VIEW (Not to Scale) 9 CL 8 DB3 7 DB A 8 6 DB A 9 5 DB A DB9 CS 3 DB W V CC DB DB DB DB3 DB DB5 DB6 DB7 B C DUT_CD D V EF ( )CDEF V EF (+)CDEF E DUT_EF F G EV. A

5 AD78 Pin No. Mnemonic Description PIN FUNCTION DESCIPTIONS DUT_AB Device Sense Ground for s A and B. A and B are referenced to the voltage applied to this pin.,, 3, A.. H Outputs., 37, 35, 3, 3 3, V EF ( )AB, V EF (+)AB eference Inputs for s A and B. These reference voltages are referred to. 5, 38 Positive Analog Power Supply; +5 V ± % for specified performance. 6 V SS Negative Analog Power Supply; 5 V ± % for specified performance. 7 L Load Logic Input (active low). When this logic input is taken low the contents of the registers are transferred to their respective registers. L can be tied permanently low enabling the outputs to be updated on the rising edge of W. 8, 9, A, A, A Address inputs. A, A and A are decoded to select one of the eight input registers for a data transfer. CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low. W Level-Triggered Write Input (active low), used in conjunction with CS to write data to the AD78 data registers. Data is latched into the selected input register on the rising edge of W. 3 V CC Logic Power Supply; 5 V ± 5%. Ground. 5 8 DB.. DB Parallel Data Inputs. The AD78 can accept a straight -bit parallel word on DB to DB3 where DB3 is the MSB and DB is the LSB. 9 CL Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the relevant DUT pin. The contents of input registers and registers A to H are not affected when the CL pin is taken low. When CL is brought back high, the outputs revert to their original outputs as determined by the data in their registers. 3, 3 V EF (+)GH, V EF ( )GH eference Inputs for s G and H. These reference voltages are referred to. 33 DUT_GH Device Sense Ground for s G and H. G and H are referenced to the voltage applied to this pin. 36 DUT_EF Device Sense Ground for s E and F. E and F are referenced to the voltage applied to this pin. 39 V EF (+)CDEF eference Inputs for s C, D, E and F. These reference voltages are referred to. V EF ( )CDEF eference Inputs for s C, D, E and F. These reference voltages are referred to. DUT_CD Device Sense Ground for s C and D. C and D are referenced to the voltage applied to this pin. EV. A 5

6 AD78 TEMINOLOGY elative Accuracy elative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in Least Significant Bits. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal LSB change between any two adjacent codes. A specified differential nonlinearity of LSB maximum ensures monotonicity. DC Crosstalk Although the common input reference voltage signals are internally buffered, small I drops in the individual reference inputs across the die can mean that an update to one channel can produce a dc output change in one or another of the channel outputs. The eight outputs are buffered by op amps that share common and V SS power supplies. If the dc load current changes in one channel (due to an update), this can result in a further dc change in one or another of the channel outputs. This effect is most obvious at high load currents and reduces as the load currents are reduced. With high impedance loads the effect is virtually impossible to measure. Output Voltage Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Impulse This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nv-secs. It is measured with V EF (+) = +5 V and V EF ( ) = 5 V and the digital inputs toggled between FFFH and H. Channel-to-Channel Isolation Channel-to-channel isolation refers to the proportion of input signal from one s reference input that appears at the output of another. It is expressed in dbs. -to- Crosstalk -to- crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog O/P change at another converter. It is specified in nv-secs. Digital Crosstalk The glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the digital crosstalk and is specified in nv-secs. Digital Feedthrough When the device is not selected, high frequency logic activity on the device s digital inputs can be capacitively coupled both across and through the device to show up as noise on the pins. This noise is digital feedthrough. DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. Full-Scale Error This is the error in output voltage when all s are loaded into the latch. Ideally the output voltage, with all s loaded into the latch, should be V EF (+) LSB. Zero-Scale Error Zero-scale error is the error in the output voltage when all s are loaded into the latch. Ideally the output voltage, with all s in the latch should be equal to V EF ( ). Zeroscale error is mainly due to offsets in the output amplifier. Gain Error Gain Error is defined as (Full-Scale Error) (Zero-Scale Error). GENEAL DESCIPTION Architecture General Each channel consists of a straight -bit - voltage-mode. The full-scale output voltage range is equal to twice the reference span of V EF (+) V EF ( ). The coding is straight binary; all s produces an output of V EF ( ); all s produces an output of V EF (+) LSB. The analog output voltage of each channel reflects the contents of its own register. Data is transferred from the external bus to the input register of each on a per channel basis. Bringing the CL line low switches all the signal outputs, A to H, to the voltage level on the relevant DUT pin. When the CL signal is brought back high, the output voltages from the s will reflect the data stored in the relevant registers. Data Loading to the AD78 Data is loaded into the AD78 in straight parallel -bit wide words. The output voltages, A H are updated to reflect new data in the registers. The actual input register being written to is determined by the logic levels present on the device s address lines, as shown in Table I. Table I. Address Line Truth Table A A A Selected INPUT EG A ( A) INPUT EG B ( B) INPUT EG C ( C) INPUT EG D ( D) INPUT EG E ( E) INPUT EG F ( F) INPUT EG G ( G) INPUT EG H ( H) 6 EV. A

7 Typical Performance Characteristics AD78 INL EO LSBs = +5V V SS = 5V V EF (+) = +5V V EF ( ) = 5V T A = 5 C CODE DNL EO LSBs = +5V V SS = 5V V EF (+) = +5V V EF ( ) = 5V T A = 5 C CODE INL EO LSBs = +5V V SS = 5V V EF (+) = +5V V EF ( ) = 5V 6 8 TEMPEATUE C TPC. Typical INL Plot TPC. Typical DNL Plot TPC 3. Typical INL Error vs. Temperature DNL EO LSBs.5.5 = +5V V SS = 5V V EF (+) = +5V V EF (+) = 5V EO LSBs = +5V V SS = 5V V EF(+) = +5V V EF( ) = 5V ZEO-SCALE EO FULL-SCALE EO I CC ma DIGITAL THESHOLDS DIGITAL SUPPLIES V CC = +5V = +5V V SS = 5V 6 8 TEMPEATUE C TPC. Typical DNL Error vs. Temperature 6 8 TEMPEATUE C TPC 5. Zero-Scale and Full-Scale Error vs. Temperature 6 8 TEMPEATUE C TPC 6. I CC vs. Temperature = +5V V SS = 5V V CC = +5V Volts.3.. Volts.8.7 I DD /I SS ma 8 6 I DD I SS TPC 7. Typical Digital-to-Analog Glitch Impulse SETTLING TIME s TPC 8. Settling Time (+) 6 8 TEMPEATUE C TPC 9. I DD, I SS vs. Temperature EV. A 7

8 AD78 Unipolar Configuration Figure shows the AD78 in the unipolar binary circuit configuration. The V EF (+) input of the is driven by the AD586, a 5 V reference. V EF ( ) is tied to ground. Table II gives the code table for unipolar operation of the AD78. Other suitable references include the EF, a precision 5 V reference, and the EF95, a low dropout, micropower precision 5 V reference. C F 8 AD586 SIGNAL 6 5 k +5V V EF (+) V CC AD78* V EF ( ) V SS 5V +5V DUT *ADDITIONAL PINS OMITTED FO CLAITY ( TO +V) SIGNAL Figure. Unipolar V Operation Offset and gain may be adjusted in Figure as follows: To adjust offset, disconnect the V EF ( ) input from V, load the with all s and adjust the V EF ( ) voltage until = V. For gain adjustment, the AD78 should be loaded with all s and adjusted until = V EF (+) LSB = V(6383/ 638) = V. Many circuits will not require these offset and gain adjustments. In these circuits can be omitted. Pin 5 of the AD586 may be left open circuit and Pin (V EF ( )) of the AD78 tied to V. Table II. Code Table for Unipolar Operation Binary Number in egister Analog Output MSB LSB ( ) V EF (6383/638) V V EF (89/638) V V EF (89/638) V V EF (/638) V V NOTES V= V EF (+); V EF ( ) = V for unipolar operation. For V EF (+) = 5 V, LSB = V/ = V/638 = 6 µv. Bipolar Configuration Figure 3 shows the AD78 set up for ± V operation. The AD588 provides precision ±5 V tracking outputs that are fed to the V EF (+) and V EF ( ) inputs of the AD78. The code table for bipolar operation of the AD78 is shown in Table III. In Figure 3, full-scale and bipolar zero adjustments are provided by varying the gain and balance on the AD588. varies the gain on the AD588 while 3 adjusts the offset of both the +5 V and 5 V outputs together with respect to ground. For bipolar-zero adjustment, the is loaded with... and 3 is adjusted until = V. Full scale is adjusted by loading the with all s and adjusting until = (89/89) V = V. When bipolar-zero and full-scale adjustment are not needed, and 3 can be omitted. Pin on the AD588 should be connected to Pin and Pin 5 should be left floating. k C F 3 k AD k V V EF (+) V EF ( ) AD78* V SS 5V +5V V CC DUT *ADDITIONAL PINS OMITTED FO CLAITY Figure 3. Bipolar ± V Operation ( V TO +V) SIGNAL Table III. Code Table for Bipolar Operation Binary Number in egister Analog Output MSB LSB ( ) [V EF ( ) + V EF (6383/638)] V [V EF ( ) + V EF (893/638)] V [V EF ( ) + V EF (89/638)] V [V EF ( ) + V EF (89/638)] V [V EF ( ) + V EF (/638)] V [V EF ( )] V NOTES V EF = (V EF(+) V EF( )). For V EF (+) = +5 V, and V EF ( ) = 5 V, V EF = V, LSB = V EF V/ = V/638 =. mv. CONTOLLED POWE-ON OF THE OUTPUT STAGE A block diagram of the output stage of the AD78 is shown in Figure. It is capable of driving a load of 5 kω in parallel with 5 pf. G to G 6 are transmission gates used to control the power on voltage present at. On power up G and G are also used in conjunction with the CL input to set to the user defined voltage present at the DUT pin. When CL is taken back high, the outputs reflect the data in the registers. G G G DUT G 3 = 6k G 5 k G 6 Figure. Block Diagram of AD78 Output Stage 8 EV. A

9 AD78 Power-On with CL Low The output stage of the AD78 has been designed to allow output stability during power-on. If CL is kept low during power-on, then just after power is applied to the AD78, the situation is as depicted in Figure 5. G, G and G 6 are open while G, G 3 and G 5 are closed. G G G G 3 G 6 G G 6 G 5 k G G DUT G 3 G 5 k Figure 5. Output Stage with < 7 V or V SS > 3 V; CL Low is kept within a few hundred millivolts of DUT via G 5 and a kω resistor. This thin-film resistor is connected in parallel with the gain resistors of the output amplifier. The output amplifier is connected as a unity gain buffer via G 3, and the DUT voltage is applied to the buffer input via G. The amplifier s output is thus at the same voltage as the DUT pin. The output stage remains configured as in Figure 5 until the voltage at exceeds 7 V and V SS is more negative than 3 V. By now the output amplifier has enough headroom to handle signals at its input and has also had time to settle. The internal power-on circuitry opens G 3 and G 5 and closes G and G 6. This situation is shown in Figure 6. Now the output amplifier is configured in its noise gain configuration via G and G 6. The DUT voltage is still connected to the noninverting input via G and this voltage appears at. G G 3 G 6 DUT Figure 7. Output Stage After CL Is Taken High Power-On with CL High If CL is high on the application of power to the device, the output stages of the AD78 are configured as in Figure 8 while is less than 7 V and V SS is more positive than 3 V. G is closed and G is open, thereby connecting the output of the to the input of its output amplifier. G 3 and G 5 are closed while G and G 6 are open, thus connecting the output amplifier as a unity gain buffer. is connected to DUT via G 5 through a kω resistor until exceeds 7 V and V SS is more negative than 3 V. G G G DUT G 3 G 5 k G 6 Figure 8. Output Stage Powering Up with CL High While < 7 V or V SS > 3 V When the difference between the supply voltages reaches V, the internal power-on circuitry opens G 3 and G 5 and closes G and G 6 configuring the output stage as shown in Figure 9. G G G 5 k G G 3 G 6 DUT Figure 6. Output Stage with > 7 V and V SS < 3 V; CL Low has been disconnected from the DUT pin by the opening of G 5, but will track the voltage present at DUT via the configuration shown in Figure 6. When CL is taken back high, the output stage is configured as shown in Figure 7. The internal control logic closes G and opens G. The output amr})fier is connected in a noninverting gain-of-two configuration. The voltage that appears on the pins is determined by the data present in the registers. G G DUT G 5 k Figure 9. Output Stage Powering Up with CL High When > 7 V and V SS < 3 V EV. A 9

10 AD78 DUT Voltage ange During power-on, the pins of the AD78 are connected to the relevant DUT pins via G 5 and the kω thin-film resistor. The DUT potential must obey the max ratings at all times. Thus, the voltage at DUT must always be within the range V SS.3 V, +.3 V. However, in order that the voltages at the pins of the AD78 stay within ± V of the relevant DUT potential during power-on, the voltage applied to DUT should also be kept within the range V, + V. Once the AD78 has powered on and the on-chip amplifiers have settled, any voltage that is now applied to the DUT pin is subtracted from the output, which has been gained up by a factor of two. Thus, for specified operation, the maximum voltage that can be applied to the DUT pin increases to the maximum allowable V EF (+) voltage, and the minimum voltage that can be applied to DUT is the minimum V EF ( ) voltage. After the AD78 has fully powered on, the outputs can track any DUT voltage within this minimum/maximum range. Power Supply Sequencing When operating the AD78, it is important that ground be connected at all times to avoid high current states. The recommended power-up sequence is /V SS followed by V CC. If V CC can exceed on power-up, the diode scheme shown in the absolute maximum ratings section will ensure protection. The reference inputs and digital inputs should be powered up last. Should the references exceed /V SS on power-up, current limiting resistors should be inserted in series with the reference inputs to limit the current to ma. Logic inputs should not be applied before V CC. Current limiting resistors (7 Ω) in series with the logic inputs should be inserted if these inputs come up before V CC. MICOPOCESSO INTEFACING Interfacing the AD78 6-Bit Interface The AD78 can be interfaced to a variety of 6-bit microcontrollers or DSP processors. Figure shows the AD78 interfaced to a generic 6-bit microcontroller/dsp processor. The lower address lines from the processor are connected to A, A and A on the AD78 as shown. The upper address lines are decoded to provide a chip select signal or an L signal for the AD78. The fast interface timing of the AD78 allows direct interface to a wide variety of microcontrollers and DSPs as shown in Figure. CONTOLLE/ DSP POCESSO* D3 DATA BUS D UPPE BITS OF ADDESS BUS A A A /W ADDESS DECODE D3 D CS L A A A W *ADDITIONAL PINS OMITTED FO CLAITY Figure. Parallel Interface AD78 APPLICATIONS Power Supply Bypassing and Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD78 is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined at only one place. The pin of the AD78 should be connected to the A of the system. If the AD78 is in a system where multiple devices require an A-to-D connection, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD78. Digital lines running under the device should be avoided as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD78 to avoid noise coupling. The power supply lines of the AD78 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. EV. A

11 AD78 The AD78 should have ample supply bypassing located as close to the package as possible, ideally right up against the device. Figure shows the recommended capacitor values of µf in parallel with. µf on each of the supplies. The µf capacitors are the tantalum bead type. The. µf capacitor should have low Effective Series esistance (ES) and Effective Series Inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. V CC. F F F. F AD78 V SS F. F Figure. ecommended Decoupling Scheme for AD78 Automated Test Equipment The AD78 is particularly suited for use in an automated test environment. Figure shows the AD78 providing the necessary voltages for the pin driver and the window comparator in a typical ATE pin electronics configuration. AD588s are used to provide reference voltages for the AD78. In the configuration shown, the AD588s are configured so that the voltage at Pin is 5 V greater than the voltage at Pin 9 and the voltage at Pin 5 is 5 V less than the voltage at Pin V 5V F AD V 5V F AD V OFFSET. F DEVICE V EF (+)AB V EF ( )AB B DUT_AB AD78* V EF (+)GH V EF ( )GH DUT_GH A G H WINDOW COMPAATO +5V PIN DIVE 5V DEVICE *ADDITIONAL PINS OMITTED FO CLAITY Figure. ATE Application TO TESTE DEVICE One of the AD588s is used as a reference for s A and B. These s are used to provide high and low levels for the pin driver. The pin driver may have an associated offset. This can be nulled by applying an offset voltage to Pin 9 of the AD588. First, the code... is loaded into the A latch and the pin driver output is set to the A output. The V OFFSET voltage is adjusted until V appears between the pin driver output and DUT. This causes both V EF (+) and V EF ( ) to be offset with respect to by an amount equal to V OFFSET. However, the output of the pin driver will vary from V to + V with respect to DUT as the input code varies from... to... The V OFFSET voltage is also applied to the DUT pins. When a clear is performed on the AD78, the output of the pin driver will be V with respect to DUT. The other AD588 is used to provide a reference voltage for s G and H. These provide the reference voltages for the window comparator shown in the diagram. Note that Pin 9 of this AD588 is connected to Device. This causes V EF (+)GH and V EF ( )GH to be referenced to Device. As G and H input codes vary from... to..., G and H vary from V to + V with respect to Device. Device is also connected to DUT. When the AD78 is cleared, G and H are cleared to V with respect to Device. Programmable eference Generation for the AD78 in an ATE Application The AD78 is particularly suited for use in an automated test environment. The reference input for the AD78 octal -bit requires three differential references for the eight s. Programmable references may be a requirement in some ATE applications as the offset and gain errors at the output of a can be adjusted by varying the voltages on the reference pins of the. To trim offset errors, the is loaded with the digital code... and the voltage on the V EF ( ) pin is adjusted until the desired negative output voltage is obtained. To trim out gain errors, first the offset error is trimmed. Then the is loaded with the code... and the voltage on the V EF (+) pin is adjusted until the desired full-scale voltage minus one LSB is obtained. It is not uncommon in ATE design, to have other circuitry at the output of the AD78 that can have offset and gain errors of up to say ± 3 mv. These offset and gain errors can be easily removed by adjusting the reference voltages of the AD78. The AD78 uses nominal reference values of ±5 V to achieve an output span of ± V. Since the AD78 has a gain of two from the reference inputs to the output, adjusting the reference voltages by ±5 mv will adjust the offset and gain by ± 3 mv. There are a number of suitable 8- and -bit s available that would be suitable to drive the reference inputs of the AD78, such as the AD78, a quad -bit digital-to-analog converter with serial load capabilities. The voltage output from this is in the form of V BIAS ± V SWING and rail-to-rail operation is achievable. The voltage reference for this can be internally generated or provided externally. This also contains an 8-bit SUB which can be used to shift the complete transfer function of each around the V BIAS point. This can be used as a fine trim on the output voltage. In this application two AD78s are required to provide programmable reference capability for all eight s. One AD78 is used to drive the V EF (+) pins and the second package used to drive the V EF ( ) pins. Another suitable for providing programmable reference capability is the AD883. This is an octal 8-bit TIM and provides independent control of both the top and bottom ends of the TIM. This is helpful in maximizing the resolution of devices with a limited allowable voltage control range. TIM is a registered trademark of Analog Devices, Inc. EV. A

12 AD78 The AD883 has an output voltage range of to ( V to 5 V). To trim the V EF (+) input, the appropriate trim range on the AD883 can be set using the V EFL and V EFH pins allowing 8 bits of resolution between the two points. This will allow the V EF (+) pin to be adjusted to remove gain errors. To trim the V EF ( ) voltage, some method of providing a trim voltage in the required negative voltage range is required. Neither the AD78 or the AD883 can provide this range in normal operation as their output range is V to 5 V. There are two methods of producing this negative voltage. One method is to ADD BUS +5V provide a positive output voltage and then to level shift that analog voltage to the required negative range. Alternatively these s can be operated with supplies of V and 5 V, with the pin connected to V and the pin connected to 5 V. Now these can be used to provide the negative reference voltages for the V EF ( ) inputs on the AD78. However, the digital signals driving the s need to be level-shifted from the V to +5 V range to the 5 V to V range. Figure 3 shows a typical application circuit to provide programmable reference capabilities for the AD78. C39 / (rev. A) SDATA SCLK ADD DECODE FSIN/CS D IN SCLK 8/-BIT V TO +5V A, A, A V EF (+)AB A A CONTOLLE LOGIC LEVEL SHIFT AD78* FSIN/CS D IN SCLK 8/-BIT V TO 5V V EF ( )AB B B 5V DATA BUS *ADDITIONAL PINS OMITTED FO CLAITY DATA BUS Figure 3. Programmable eference Generation for the AD78 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Lead MQFP (S-).96 (.) MAX.37 (.9).5 (.6) 8.8 SEATING PLANE (3.95).56 (3.875).398 (.).39 (9.9) 3 PINTED IN U.S.A. TOP VIEW (PINS DOWN). (.).3 (.8).83 (.).77 (.96). (.).3 (.8).33 (.8).9 (.7).6 (.). (.3) EV. A