DESCRIPTION FEATURES APPLICATIONS. LTC1590 Dual Serial 12-Bit Multiplying DAC TYPICAL APPLICATION

Size: px

Start display at page:

Download "DESCRIPTION FEATURES APPLICATIONS. LTC1590 Dual Serial 12-Bit Multiplying DAC TYPICAL APPLICATION"

Junior Marshall
5 years ago
Views:

1 FEATRES DNL and INL Over Temperature: ±.LSB Max Gain Error: ±LSB Max Low Supply Current: µa Max -Quadrant Multiplication Power-On Reset Asynchronous Clear Input Daisy-Chain -Wire Serial Interface -Pin Narrow SO and PDIP Packages APPLICATIONS Process Control and Industrial Automation Software Controlled Gain Adjustment Digitally Controlled Filter and Power Supplies DESCRIPTION LTC9 Dual Serial -Bit Multiplying DAC The LTC 9 is a dual, serial input -bit multiplying digital-to-analog converter (DAC). It includes two current output multiplying CMOS DACs and an easy SPI compatible serial interface with daisy-chain output. An asynchronous CLR pin sets both DACs to zero scale. Excellent accuracy, stability and versatility are combined with the smallest package available for a dual -bit multiplying DAC. Parts are available in -pin PDIP and narrow SO packages and are specified over the commercial and industrial temperature ranges. Automatic Test Equipment, LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION Integral Nonlinearity Over Temperature Dual -Bit -Quadrant Multiplying DAC.. THREE SPERIMPOSED CRVES T A = C, C, C D IN V V CC V IN A ±V V IN B ±V 9 Daisy-Chained Control Outputs pf V LT INL (LSB). µp CLK CS/LD D OT -BIT SHIFT REG AND LATCH V V REF B R FB B V REF A R FB A OT B OT B OT A OT A CLR DGND AGND LTC9 pf V V OT B ±V V OT A ±V LTC9 TA INL (LSB)... 9 DIGITAL INPT CODE LTC9 TA Integral Nonlinearity Over Temperature THREE SPERIMPOSED CRVES T A = C, C, C.. 9 DIGITAL INPT CODE LTC9 TA

2 LTC9 ABSOLTE MAXIMM RATINGS W W W V CC to AGND....V to V V CC to DGND....V to V AGND to DGND... V CC.V DGND to AGND...V CC.V V REF to AGND... ±V R FB to AGND... ±V Digital Inputs to DGND....V to V CC.V V OT, V OT to AGND....V to V CC.V Maximum Junction Temperature... C Operating Temperature Range LTC9C... C to C LTC9I... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR V REF B R FB B OT B OT B OT A OT A AGND R FB A N PACKAGE -LEAD PDIP TOP VIEW V CC CLR CLK D IN D OT CS/LD DGND 9 V REF A S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = C/W (N) T JMAX = C, θ JA = C/W (S) Consult factory for Military grade parts. W ATIO ORDER PART NMBER LTC9CN LTC9CS LTC9IN LTC9IS ELECTRICAL CHARACTERISTICS V CC =.V to.v, V REF = V, V OT = V OT = AGND = DGND = V, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Accuracy Resolution Bits INL Integral Nonlinearity (Note ) ±. LSB DNL Differential Nonlinearity Guaranteed Monotonic, T MIN to T MAX ±. LSB GE Gain Error (Note ), T A = C ± LSB T MIN to T MAX ± LSB Gain Temperature Coefficient (Note ) Gain/ Temperature ppm/ C I LEAKAGE OT A, OT B Leakage Current (Note ), T A = C ± na T MIN to T MAX ± na Zero-Scale Error T A = C ±. LSB T MIN to T MAX ±. LSB PSRR Power Supply Rejection V CC = V ±% ±. ±. %/% Reference Input R REF V REF Input Resistance kω AC Performance (Note ) V REFA, V REFB Input Resistance Match % Digital-to-Analog Glitch Impulse (Notes, ) nv-s Multiplying Feedthrough Error (Note ) 9 db Output Current Settling Time (Note ) To.% for Full-Scale Change.. µs Channel-to-Channel Isolation (Note ) 9 db Digital Crosstalk (Notes, ) nv-s Output Noise Voltage Density (Note 9) nv/ Hz THD Total Harmonic Distortion (Note ) 9 db Multiplying Bandwidth (Note ) MHz

3 LTC9 ELECTRICAL CHARACTERISTICS V CC =.V to.v, V REF = V, V OT = V OT = AGND = DGND = V, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Analog Outputs C OT Output Capacitance (Note ) DAC Register Loaded to All s 9 pf DAC Register Loaded to All s pf Digital Input V IH Digital Input High Voltage. V V IL Digital Input Low Voltage. V I IN Digital Input Current. ± µa C IN Digital Input Capacitance (Note ) V IN = V pf Digital Output V OH Digital Output High Voltage I OH = µa V V OL Digital Output Low Voltage I OH =.ma. V Timing Characteristics t D IN to CLK Setup Time ns t D IN to CLK Setup Hold Time ns t CLK High Time ns t CLK Low Time ns t CS/LD High Time ns t LSB CLK to CS/LD ns t CS/LD Low to CLK High ns t CLK Low to CS/LD Low ns t 9 CLK to D OT Delay ns Power Supply V CC Operating Supply Range.. V I CC Supply Current Digital Inputs = V or V CC µa The denotes specifications which apply over the full operating temperature range. Note : ±.LSB = ±.% of full scale. Note : sing internal feedback resistor. Note : Guaranteed by design, not subject to test. Note : I OT with DAC register loaded with all s. Note : OT load = Ω in parallel with pf. Note : V REF = V. DAC register contents changed from all s to all s or all s to all s. Note : output with V REF A = V and V REF B = khz V P-P, or output with V REF B = V, V REF A = khz V P-P. Both DAC registers loaded with all s. Note : Glitch on or output when the other DAC makes a full-scale transition. Note 9: Hz to khz. Calculation from e n = KTRB where: K = Boltzmann constant (J/K ); R = resistance (Ω); T = resistor temperature ( K); B = bandwidth (Hz). Note: V REF = V RMS at khz. DAC register loaded with all s, using LT op amp. Note : V REF = ±V, khz sine wave, DAC register loaded with all s, using LT op amp. Note : db bandwidth using LT op amp.

4 LTC9 TYPICAL PERFORMANCE CHARACTERISTICS W Full-Scale Settling Waveform Integral Nonlinearity (INL) Differential Nonlinearity (DNL) OTPT VOLTAGE (V/DIV) V DD = V V TO V OTPT RANGE LT OP AMP C FB pf INTEGRAL NONLINEARITY (LSB)... DIFFERENTIAL NONLINEARITY (LSB)... TIME (ns/div) 9 G. 9 DIGITAL INPT CODE 9 G. 9 DIGITAL INPT CODE 9 G SIGNAL-TO-(NOISE DISTORTION) (db) ATTENATION (db) 9 9 Multiplying Mode Signal-to- (Noise Distortion) vs Frequency V DD = V SING AN LT WITH khz FILTER Multiplying Mode Frequency Response vs Digital Code D D D9 D D D D D D D D D SING AN LT WITH khz FILTER FREQENCY (khz) ALL BITS OFF k k k M M FREQENCY (Hz) 9 G ALL BITS ON INTEGRAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity vs Reference Voltage V DD = V 9 REFERENCE VOLTAGE (V) Integral Nonlinearity vs Supply Voltage V REF = V V REF = V 9 G 9 SPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity vs Reference Voltage. V DD = V... 9 REFERENCE VOLTAGE (V) Differential Nonlinearity vs Supply Voltage 9 G V REF = V. V REF = V. 9 SPPLY VOLTAGE (V) 9 G 9 G 9 G9

5 LTC9 TYPICAL PERFORMANCE CHARACTERISTICS W OTPT VOLTAGE (mv/div) Midscale Glitch Impulse V DD = V LT OP AMP C FB = pf LOGIC THRESHOLD (V) Logic Threshold vs Supply Voltage SPPLY CRRENT (ma).. Supply Current vs Logic Input Voltage TIME (ns/div) 9 G SPPLY VOLTAGE (V) 9 G INPT VOLTAGE (V) 9 G PIN FNCTIONS V REF B, V REF A (Pins, 9): Reference Inputs for /B. Typically ±V, accepts up to ±V. R FB B, R FB A (Pins, ): Feedback Resistors for /B. Normally tied to the output of current to voltage converter op amp. Typically swings to ±V. Swings from V to V REF. OT B, OT A (Pins, ): True Current Output for DAC A/B. Normally tied to inverting input of current to voltage converter op amp. OT B, OT A (Pins, ): Complement Current Output for /B. Normally tied to ground. AGND (Pin ): Analog Ground Pin. Tie to ground. DGND (Pin ): Digital Ground Pin. Tie to ground. CS/LD (Pin ): The Serial Interface Enable and Load Control Input. When CS/LD is low the CLK signal is enabled so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. D OT (Pin ): The Serial Data Output. Data becomes valid on the rising edge of the CLK. D IN (Pin ): The Serial Data Input. Data on the D IN pin is latched into the shift register on the rising edge of the serial clock. Data is loaded as one -bit word. The first bits are for, MSB-first and the second bits are for, MSB-first. CLK (Pin ): The Serial Interface Clock Input. CLR (Pin ): The Clear Pin for the DAC. Clears both DACs to zero scale when pulled low. This pin should be tied to V CC for normal operation. V CC (Pin ): The Positive Supply Input.. V CC.V. Requires a bypass capacitor to ground.

6 LTC9 BLOCKDAGRA I W V REF B k k k k k k k k k k k R FB B OT B OT B DECODER D (MSB) LOAD D D9 D D DAC REGISTER B (LSB) V REF A 9 CS/LD R FB A OT A OT A CLK D IN IN CLK INPT -BIT SHIFT REGISTER OT D OT 9 BD V CC DGND AGND TIMING DIAGRAMS W W OPERATING SEQENCE D IN MSB INPT LSB INPT D D D9 D D D D D D D D D D D D9 D D D D D D D D D MSB LSB CLK 9 9 CS/LD (ENABLE CLOCK) (PDATE DAC OTPT) LTC9 TD

7 LTC9 TIMING DIAGRAMS W W TIMING DIAGRAM t t t t t CLK t t D IN D A MSB D A D9 A D B D B LSB CS/LD t t 9 D OT D A PREVIOS WORD D A PREVIOS WORD D9 A PREVIOS WORD D B PREVIOS WORD D A CRRENT WORD 9 TD APPLICATIONS INFORMATION Description W The LTC9 is a dual -bit multiplying DAC that has serial inputs and current outputs. It uses precision R/R resistor ladder technology to provide exceptional linearity and stability. The device operates from a single V supply and provides a ±V reference input and voltage output range when used with an external op amp. Serial I/O The LTC9 has a -wire SPI/MICROWIRE TM compatible serial port that accepts -bit serial words. Data is loaded MSB first with the first bits controlling and the second bits controlling. Data is shifted into the D IN input on the rising edge of CLK. The CS/LD input must be taken low before transferring data to enable the CLK input. After transferring data, CS/LD is pulled high to load data from the shift register to the DAC registers which updates both DACs. The buffered output of the -bit shift register is available on the D OT pin. Multiple DACs can be daisy-chained on one -wire interface by connecting the D OT pin to the D IN pin of the next DAC (see the Timing Diagrams section). MICROWIRE is a trademark of National Semiconductor Corporation. Equivalent Circuit Figure shows an equivalent analog circuit for the LTC9 DACs. R is the reference input, R REF, which is nominally k. The DAC output is represented by the Thevinin equivalent current source with a value of: (Code/9)(V REF /R) The current source I LKG models the junction leakage of the DAC output switches. I LKG is typically less than na at C and decreases by roughly two times for every C reduction in temperature. C OT is the output capacitance, and it also comes from the DAC output switches and varies from pf at zero scale to pf at full scale. R O is the equivalent output resistance, which varies with digital input code (see Op Amp Selection section). V REF A V REF B R CODE V REF ( 9 )( R ) R O R I LKG Figure. Equivalent Circuit R FB A R FB B OT A OT B COT OT A OT B AGND 9 F

8 LTC9 APPLICATIONS INFORMATION nipolar -Quadrant Multiplying Mode (V OT = V to V REF ) The LTC9 can be used with a dual op amp to provide a dual -quadrant multiplying DAC as shown in Figure. The unipolar DAC transfer function is shown in Table. The pf feedback capacitor is recommended to compensate for the pole caused by the internal feedback resistor and the OT output capacitance. For high speed op amps this feedback capacitor is required for stability, and a smaller value, pf to pf, may be desired to get the fastest transient response and shortest settling time. A larger feedback capacitor can be used to reduce wideband noise, glitch impulse and distortion for lower frequency signals. A pole is introduced in the DAC transfer function at approximately (C FB )(R FB ). For example, a pf feedback capacitor will typically give a pole at: khz = π pf kω W ( )( ) Table. nipolar Binary Code Table DIGITAL INPT BINARY NMBER ANALOG OTPT IN DAC REGISTER V OT MSB LSB V REF (9/9) V REF (/9) = V REF / V REF (/9) V Bipolar -Quadrant Multiplying Mode (V OT = V REF to V REF ) The circuit of Figure can be used to provide a dual -quadrant multiplying DAC. This circuit starts with the unipolar application circuit and adds three resistors and an op amp. These extra devices provide a gain of from the unipolar output to the bipolar output, plus an offset of ()(V REF ) to produce the transfer function shown in Table. A pack of matched k resistors, with two resistors in parallel forming the k resistor, is recommended..µf V V REF V TO V V CC V REF R FB OT LTC9 OR OT DGND AGND pf V LT V V OT V TO V REF 9 F Table. Bipolar Offset Binary Code Table DIGITAL INPT BINARY NMBER ANALOG OTPT IN DAC REGISTER V OT MSB LSB V REF (/) V REF () V V REF () V REF (/) = V REF Figure. nipolar Operation (-Quadrant Multiplication) V REF V TO V R k R k V.µF V CC V REF R FB OT LTC9 OR OT DGND AGND pf V LT V R k V LT V OT V REF TO V REF V 9 F Figure. Bipolar Operation (-Quadrant Multiplication)

9 LTC9 APPLICATIONS INFORMATION Op Amp Selection W To maintain the excellent accuracy and stability of the LTC9 thought should be given to op amp selection. Fortunately, the sensitivity of INL and DNL to op amp offset has been significantly reduced compared to competing parts of this type. The op amp s V OS causes DAC output offset. In addition, because the DAC s equivalent output resistance R O changes as a function of code, there is a code-dependent DAC output error proportional to V OS. For fixed reference applications this causes gain, INL and DNL error. For multiplying applications, a code-dependent, DC output voltage error is seen. At zero scale the DAC output error is equal to the op amp offset, and at full scale the output error is equal to twice the op amp offset. For example, a mv op amp offset will cause a.lsb zeroscale error and a.lsb full-scale error with a V fullscale range. The offset caused INL error is approximately. times the op amp V OS and DNL error is. times op amp V OS. For the same example of mv op amp V OS and V full-scale range, the INL degradation will be.lsb and DNL degradation will be.lsb. Op amp bias current causes only an offset error equal to (I BIAS )(R FB ) (I BIAS )(kω). For example, a na op amp bias current causes a.mv DAC offset, or.lsb for a V full-scale range. It is important to note that connecting the op amp noninverting input to ground through a resistor will not cancel bias current errors and should never be done! Similarly an offset caused by op amp bias current should not be adjusted by using the op amp null pins since this increases offset between DAC OT and OT pins, causing INL, DNL and gain errors. If op amp offset error adjustment is required, the op amp input offset voltage (the voltage difference between OT and OT) should be nulled. Grounding As with any high precision data converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. OT carries the complementary DAC output current and should be tied to the star ground with as low a resistance as possible. Other ground points that must be tied to the star ground point include the V REF input ground, the op amp noninverting input(s) and the V OT ground reference point. TYPICAL APPLICATIONS Dual Programmable Attenuator DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OT CLEAR.µF D IN CLK CS/LD D OT CLR V AGND DGND -BIT SHIFT REG AND LATCH V IN B ±V V REF B V REF A LTC9 R FB B R FB A 9 OT B OT B OT A OT A pf pf V LT LT V.µF V OT = V IN.µF V OT B D ( 9) V OT A 9 TA V IN A ±V 9

10 LTC9 TYPICAL APPLICATIONS Very Low Power Single Supply Dual V OT DAC k k / LT9 V OT A k k V.V / LT9 V OT B V TO.V 9 V CC V.V k.v OT B OT B R FB B V REF B LTC9 LT-..µF k k / LT9 OT A OT A R FB A V REF A AGND DGND I SPPLY TOTAL = µa (TYP) (WORSE-CASE CODE) 9 TA Dual Programmable Gain Amplifier V V IN B ±V DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OT CLEAR.µF D IN CLK CS/LD D OT CLR AGND DGND -BIT SHIFT REG AND LATCH V REF B R FB B LTC9 V REF A R FB A 9 OT B OT B OT A OT A pf pf V LT LT V.µF.µF V OT B 9 V OT = V IN ( D ) V OT A 9 TA V IN A ±V

11 LTC9 TYPICAL APPLICATIONS Dual Programmable Gain Amplifier with Input Attenuation V IN B ±V V k k k k DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OT CLEAR.µF D IN CLK CS/LD D OT CLR AGND DGND -BIT SHIFT REG AND LATCH k V REF B V REF A LTC9 R FB B R FB A 9 OT B OT B OT A OT A k pf pf V LT LT V.µF.µF V OT B 9 V OT = V IN ( D ) V OT A 9 TA9 k k V IN A ±V PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package -Lead PDIP (Narrow.) (LTC DWG # --).* (9.) MAX 9. ±.* (. ±.).. (..). ±. (. ±.).. (..).9. (.9.) ( ). (.) MIN. (.) MIN. (.) MIN. ±. (. ±.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.. (.) TYP. ±. (. ±.) N 9

12 LTC9 PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S Package -Lead Plastic Small Outline (Narrow.) (LTC DWG # --)..9* (9..).. (..).. (..) TYP..9 (..).. (..) (..) *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE. (.) TYP.. (.9.9)..** (..9) S 9 TYPICAL APPLICATION Dual Programmable Attenuator with Gain V IN B ±V V k k k DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OT CLEAR.µF D IN CLK CS/LD D OT CLR AGND DGND -BIT SHIFT REG AND LATCH V REF B R FB B LTC9 V REF A R FB A 9 OT B OT B OT A OT A k k k pf pf V LT LT V.µF V OT = V IN.µF V OT B D ( 9) V OT A 9 TA k k V IN A ±V RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC9 -Bit Multiplying I OT DAC in SO- True -Bit pgrade for DAC LTC9 -Bit Multiplying I OT DAC True -Bit pgrade for DAC and AD LTCA Parallel I/O Multiplying I OT -Bit DAC -Bit Wide Parallel Input LTC/LTC Serial I/O Multiplying I OT -Bit DACs Clear Pin and Serial Data Output (LTC) LTCA Parallel I/O Multiplying I OT -Bit DAC -Bit Wide Latched Parallel Input LTC Serial I/O Multiplying I OT -Bit DAC -Pin SO and PDIP Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - TELEX: f LT/TP 9 K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 99

FEATURES APPLICATIONS TYPICAL APPLICATION. LTC1451 LTC1452/LTC Bit Rail-to-Rail Micropower DACs in SO-8 DESCRIPTION

FEATURES APPLICATIONS TYPICAL APPLICATION. LTC1451 LTC1452/LTC Bit Rail-to-Rail Micropower DACs in SO-8 DESCRIPTION 12-Bit Rail-to-Rail Micropower DACs in SO-8 FEATRES 12-Bit Resolution Buffered True Rail-to-Rail Voltage Output 3V Operation (LTC1453), I CC : 250µA Typ 5V Operation (), I CC : 400µA Typ 3V to 5V Operation