FEATURES U APPLICATIO S TYPICAL APPLICATIO. LTC1860L/LTC1861L µpower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP DESCRIPTIO

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1 LTCL/LTCL µpower, V, -Bit, ksps - and -Channel ADCs in MSOP FEATRES -Bit ksps ADCs in MSOP Package Single V Supply Low Supply Current: µa (Typ) Auto Shutdown Reduces Supply Current to µa at ksps True Differential Inputs -Channel (LTCL) or -Channel (LTCL) Versions SPI/MICROWIRE TM Compatible Serial I/O High Speed pgrade to LTC/LTC Pin Compatible with -Bit LTCL/LTCL No Minimum Data Transfer Rate APPLICATIO S High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition DESCRIPTIO The LTC L/LTCL are -bit A/D converters that are offered in MSOP and SO- packages and operate on a single V supply. At ksps, the supply current is only µa. The supply current drops at lower speeds because the LTCL/LTCL automatically power down between conversions. These -bit switched capacitor successive approximation ADCs include sample-and-holds. The LTCL has a differential analog input with an external reference pin. The LTCL offers a softwareselectable -channel MX and an external reference pin on the MSOP version. The -wire, serial I/O, MSOP or SO- package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to V full scale allow direct connection to signal sources in many applications, eliminating the need for external gain stages., LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. TYPICAL APPLICATIO Single V Supply, ksps, -Bit Sampling ADC ANALOG INPT V TO V V REF IN + IN GND LTCL µf V CC SCK CONV L TA V SERIAL DATA LINK TO ASIC, PLD, MP, DSP OR SHIFT REGISTERS SPPLY CRRENT (µa) Supply Current vs Sampling Frequency CONV LOW =.µs... SAMPLING FREQENCY (khz) L/L TA Lf

2 LTCL/LTCL ABSOLTE AXI RATI GS W W W Supply Voltage (V CC )... V Ground Voltage Difference AGND, DGND LTCL MSOP Package... ±.V Analog Input... (GND.V) to (V CC +.V) Digital Input... (GND.V) to V Digital Output... (GND.V) to (V CC +.V) (Notes, ) Power Dissipation... mw Operating Temperature Range LTCLC/LTCLC... C to C LTCLI/LTCLI... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C W PACKAGE/ORDER I FOR ATIO V REF IN + IN GND TOP VIEW MS PACKAGE -LEAD PLASTIC MSOP V CC SCK CONV T JMAX = C, θ JA = C/W V REF IN + IN GND TOP VIEW S PACKAGE -LEAD PLASTIC SO V CC SCK CONV T JMAX = C, θ JA = C/W ORDER PART NMBER LTCLCMS LTCLIMS MS PART MARKING LTD LTD ORDER PART NMBER LTCLCS LTCLIS S PART MARKING L LI Consult LTC Marketing for parts specified with wider operating temperature ranges. CONV CH CH AGND DGND CONV CH CH GND TOP VIEW 9 MS PACKAGE -LEAD PLASTIC MSOP T JMAX = C, θ JA = C/W TOP VIEW S PACKAGE -LEAD PLASTIC SO V CC SCK SDI T JMAX = C, θ JA = C/W V REF V CC SCK SDI ORDER PART NMBER LTCLCMS LTCLIMS MS PART MARKING LTD LTD ORDER PART NMBER LTCLCS LTCLIS S PART MARKING L LI CO VERTER A D The denotes specifications which apply over the full operating temperature range, otherwise specifications are., V REF =.V, f SCK = f SCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX NITS Resolution Bits No Missing Codes Resolution Bits INL (Note ) ± LSB Transition Noise. LSB RMS Gain Error ± mv Offset Error ± ± mv Input Differential Voltage Range V IN = IN + IN V REF V Absolute Input Range IN + Input. V CC +. V IN Input. V CC / V V REF Input Range LTCL S- and MSOP, LTCL MSOP V CC V Analog Input Leakage Current (Note ) ± µa C IN Input Capacitance In Sample Mode pf During Conversion pf W LTIPLEXER CHARACTERISTICS Lf

3 DY A IC ACCRACY W. V CC = V, V REF = V, f SAMPLE = khz, unless otherwise specified. LTCL/LTCL SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS SNR Signal-to-Noise Ratio db S/(N + D) Signal-to-Noise Plus Distortion Ratio khz Input Signal db THD Total Hamonic Distortion p to th Harmonic khz Input Signal db Full Power Bandwidth MHz Full Linear Bandwidth S/(N + D) db khz DIGITAL A D DC ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are., V REF =.V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V IH High Level Input Voltage V CC =.V.9 V V IL Low Level Input Voltage. V I IH High Level Input Current V IN = V CC. µa I IL Low Level Input Current V IN = V. µa V OH High Level Output Voltage, I O = µa.. V, I O = µa.. V V OL Low Level Output Voltage, I O = µa. V I OZ Hi-Z Output Leakage CONV = V CC ± µa I SORCE Output Source Current V OT = V. ma I SINK Output Sink Current V OT = V CC. ma I REF Reference Current (LTCL SO-, MSOP CONV = V CC. µa and LTCL MSOP) f SMPL = f SMPL(MAX).. ma I CC Supply Current CONV = V CC After Conversion. µa f SMPL = f SMPL(MAX).. ma P D Power Dissipation f SMPL = f SMPL(MAX). mw RECO E DED OPERATI G CO DITIO S WW full operating temperature range, otherwise specifications are. The denotes specifications which apply over the SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V CC Supply Voltage.. V f SCK Clock Frequency DC MHz t CYC Total Cycle Time SCK + t CONV µs t SMPL Analog Input Sampling Time (Note ) LTCL SCK LTCL SCK t suconv Setup Time CONV Before First SCK, ns (See Figure ) t hdi Holdtime SDI After SCK LTCL ns t sudi Setup Time SDI Stable Before SCK LTCL ns t WHCLK SCK High Time f SCK = f SCK(MAX) % /f SCK t WLCLK SCK Low Time f SCK = f SCK(MAX) % /f SCK t WHCONV CONV High Time Between Data t CONV µs Transfer Cycles t WLCONV CONV Low Time During Data Transfer SCK t hconv Hold Time CONV Low After Last SCK ns Lf

4 LTCL/LTCL TI I G CHARACTERISTICS W The denotes specifications which apply over the full operating temperature range, otherwise specifications are., V REF =.V, f SCK = f SCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS t CONV Conversion Time (See Figure ).. µs f SMPL(MAX) Maximum Sampling Frequency khz t ddo Delay Time, SCK to Data Valid C LOAD = pf ns ns t dis Delay Time, CONV to Hi-Z ns t en Delay Time, CONV to Enabled C LOAD = pf ns t hdo Time Output Data Remains C LOAD = pf ns Valid After SCK t r Rise Time C LOAD = pf ns t f Fall Time C LOAD = pf ns Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : All voltage values are with respect to GND. Note : Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note : Channel leakage current is measured while the part is in sample mode. Note : Assumes fsck = fsck(max). In the case of the LTCL SCK does not have to be clocked during this time if the data word is not desired. In the case of the LTCL a minimum of clocks are required on the SCK input after CONV falls to configure the MX during this time. TYPICAL PERFOR A CE CHARACTERISTICS SPPLY CRRENT (µa) W Supply Current vs Sampling Frequency Supply Current vs Temperature Sleep Current vs Temperature CONV LOW =.µs SPPLY CRRENT (µa) f S = khz V REF =.V SHTDOWN CRRENT (µa) f S = khz V REF =.V... SAMPLING FREQENCY (khz) TEMPERATRE ( C) TEMPERATRE ( C) L/L G L/L G L/L G Lf

5 LTCL/LTCL TYPICAL PERFOR A CE CHARACTERISTICS W REFERENCE CRRENT (µa) 9 Reference Current vs Sampling Rate CONV LOW =.µs V REF =.V REFERENCE CRRENT (µa) Reference Current vs Temperature f S = khz V REF =.V REFERENCE CRRENT (µa) Reference Current vs Reference Voltage f S = khz V CC =.V SAMPLING FREQENCY (khz) TEMPERATRE ( C) REFERENCE VOLTAGE (V).. L/L G L/L G L/L G INL ERROR (LSBs)... Typical INL Curve f S = khz V REF =.V DNL ERROR (LSBs)... Typical DNL Curve f S = khz V REF =.V ANALOG INPT LEAKAGE (na) Analog Input Leakage vs Temperature CONV = V V REF =.V. 9 CODE. 9 CODE TEMPERATRE ( C) L/L G L/L G L/L G9 CHANGE IN OFFSET (LSB) Change in Offset vs Reference Voltage f S = khz V CC =.V CHANGE IN OFFSET (LSB) Change in Offset vs Temperature f S = khz V REF =.V GHANGE IN GAIN ERROR (LSB) Change in Gain Error vs Reference Voltage f S = khz V CC =.V. REFERENCE VOLTAGE (V). TEMPERATRE ( C) REFERENCE VOLTAGE (V) L/L G L/L G L/L G Lf

6 LTCL/LTCL TYPICAL PERFOR A CE CHARACTERISTICS W CHANGE IN GAIN ERROR (LSB) Change in Gain Error vs Temperature. f S = khz.. V REF =.V TEMPERATRE ( C) AMPLITDE (db) 9 9 Point FFT Non Averaged f IN = khz f S = khz V CC = V V REF = V f IN (khz) SNR (db) SNR vs f IN f S = khz V CC = V V IN = db V REF = V f IN (khz) L/L G L/L G L/L G SINAD (db) Signal-to-(Noise + Distortion) vs f IN f S = khz V CC = V V IN = db V REF = V f IN (khz) THD (db) 9 Total Harmonic Distortion vs f IN f S = khz V CC = V V IN = db V REF = V f IN (khz) SFDR (db) 9 Spurious Free Dynamic Range vs f IN f S = khz V CC = V V IN = db V REF = V f IN (khz) L/L G L/L G L/L G PI F CTIO S LTCL V REF (Pin ): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. IN +, IN (Pins, ): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin ): Analog Ground. GND should be tied directly to an analog ground plane. CONV (Pin ): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the pin, allowing the data to be shifted out. (Pin ): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin ): Shift Clock Input. This clock synchronizes the serial data transfer. V CC (Pin ): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. Lf

7 PI F CTIO S LTCL (MSOP Package) CONV (Pin ): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the pin, allowing the data to be shifted out. CH, CH (Pins, ): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin ): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin ): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin ): Digital Data Input. The A/D configuration word is shifted into this input. (Pin ): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin ): Shift Clock Input. This clock synchronizes the serial data transfer. V CC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. V REF (Pin ): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. LTCL (SO- Package) LTCL/LTCL CONV (Pin ): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the pin, allowing the data to be shifted out. CH, CH (Pins, ): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin ): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin ): Digital Data Input. The A/D configuration word is shifted into this input. (Pin ): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin ): Shift Clock Input. This clock synchronizes the serial data transfer. V CC (Pin ): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. V REF is tied internally to this pin. FNCTIONAL BLOCK DIAGRA W VCC CONV (SDI) SCK CONVERT CLK BIAS AND SHTDOWN SERIAL PORT DATA IN -BITS IN + (CH) IN (CH) + -BIT SAMPLING ADC DATA OT PIN NAMES IN PARENTHESES REFER TO LTCL GND VREF L/L BD Lf

8 LTCL/LTCL TEST CIRCITS Load Circuit for t ddo, t r, t f, t dis and t en Voltage Waveforms for Rise and Fall Times, t r, t f TEST POINT V OH k pf V CC t dis WAVEFORM, t en t dis WAVEFORM t r t f TC V OL TC CONV Voltage Waveforms for t en Voltage Waveforms for t dis TC CONV V IH Voltage Waveforms for Delay Times, t ddo and t hdo SCK V IL t ddo t hdo V OH V OL t en WAVEFORM (SEE NOTE ) WAVEFORM (SEE NOTE ) t dis 9% % NOTE : WAVEFORM IS FOR AN OTPT WITH INTERNAL CONDITIONS SCH THAT THE OTPT IS HIGH NLESS DISABLED BY THE OTPT CONTROL NOTE : WAVEFORM IS FOR AN OTPT WITH INTERNAL CONDITIONS SCH THAT THE OTPT IS LOW NLESS DISABLED BY THE OTPT CONTROL TC TC APPLICATIO S I FOR ATIO LTCL OPERATION Operating Sequence The LTCL conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTCL goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTCL goes into sample mode and is enabled. SCK synchronizes the data transfer with each bit being transmitted from on the falling SCK edge. The receiving system should capture the data from on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, will output zeros indefinitely. See Figure. W Analog Inputs The LTCL has a unipolar differential analog input. The converter will measure the voltage between the IN + and IN inputs. A zero code will occur when IN + minus IN equals zero. Full scale occurs when IN + minus IN equals V REF minus LSB. See Figure. Both the IN + and IN inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If IN is grounded and V REF is tied to V CC, a rail-to-rail input span will result on IN + as shown in Figure. Reference Input The voltage on the reference input of the LTCL (and the LTCL MSOP package) defines the full-scale range of the A/D converter. These ADCs can operate with reference voltages from V CC to V. Lf

9 LTCL/LTCL APPLICATIO S I FOR ATIO W CONV t CONV SLEEP MODE t SMPL 9 SCK DON'T CARE Hi-Z B B B9 B B B B B B B B B* Hi-Z Figure. LTCL Operating Sequence *AFTER COMPLETING THE DATA TRANSFER, IF FRTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OTPT ZEROS INDEFINITELY F µf V LSB *V IN = IN + IN VREF LSB V REF LSB VREF V IN * F V IN = V TO V CC LTCL V REF V CC IN + SCK IN GND CONV F V CC SERIAL DATA LINK TO ASIC, PLD, MP, DSP OR SHIFT REGISTERS LTCL OPERATION Figure. LTCL Transfer Curve Operating Sequence The LTCL conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTCL goes into sleep mode. The LTCL s -bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, will output zeros indefinitely. See Figure. Analog Inputs The two bits of the input word (SDI) assign the MX configuration for the next requested conversion. For a Figure. LTCL with Rail-to-Rail Input Span given channel selection, the converter will measure the voltage between the two channels indicated by the + and signs in the selected row of Table. In single-ended mode, all input channels are measured with respect to GND (or AGND). A zero code will occur when the + input minus the input equals zero. Full scale occurs when the + input minus the input equals V REF minus LSB. See Figure. Both the + and inputs are sampled at the same time so common mode noise is rejected. The input span in the SO- package is fixed at V REF = V CC. If the input in differential mode is grounded, a rail-to-rail input span will result on the + input. Reference Input The reference input of the LTCL SO- package is internally tied to V CC. The span of the A/D converter is therefore equal to V CC. The voltage on the reference input of the LTCL MSOP package defines the span of the A/D converter. The LTCL MSOP package can operate with reference voltages from V to V CC. Lf 9

10 LTCL/LTCL APPLICATIO S I FOR ATIO W CONV t CONV SLEEP MODE t SMPL SDI DON T CARE S/D O/S DON T CARE 9 SCK DON'T CARE B B B9 B B B B B B B B B* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FRTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OTPT ZEROS INDEFINITELY F Figure. LTCL Operating Sequence V LSB *V IN = (SELECTED + CHANNEL) (SELECTED CHANNEL) REFER TO TABLE V CC LSB VCC LSB VCC F V IN * SINGLE-ENDED MX MODE DIFFERENTIAL MX MODE Table. Multiplexer Channel Selection MX ADDRESS SGL/DIFF ODD/SIGN CHANNEL # GND TBL Figure. LTCL Transfer Curve GENERAL ANALOG CONSIDERATIONS Grounding The LTCL/LTCL should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTCL MSOP package and GND for the LTCL and LTCL SO- package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the V CC and V REF pins must be free of noise and ripple. Any changes in the V CC /V REF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the V CC and V REF pins directly to the analog ground plane with a minimum of µf tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTCL/ LTCL have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than Ω or high speed op amps are used (e.g., the LT, LT9, LT, LT, LT, LT or LT). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. Lf

11 PACKAGE DESCRIPTIO.9 ±. (. ±.) MS Package -Lead Plastic MSOP (Reference LTC DWG # --) LTCL/LTCL. ±. (. ±.) (NOTE ). (.) REF. (.) MIN. ±. (. ±.) TYP.. (..). (.) BSC RECOMMENDED SOLDER PAD LAYOT GAGE PLANE. (.) NOTE:. DIMENSIONS IN MILLIMETER/(INCH). DRAWING NOT TO SCALE. DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED.mm (.") PER SIDE. DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED.mm (.") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.mm (.") MAX. (.) DETAIL A DETAIL A TYP. ±. (. ±.) SEATING PLANE.9 ±. (.9 ±.). (.) MAX.. (.9.) TYP. (.) BSC. ±. (. ±.) NOTE. (.) REF. ±. (. ±.) MSOP (MS).9 ±. (. ±.) MS Package -Lead Plastic MSOP (Reference LTC DWG # --). ±. (. ±.) (NOTE ) 9.9 ±. (.9 ±.) REF. (.) MIN. ±. (. ±.) TYP.. (..). (.9) BSC RECOMMENDED SOLDER PAD LAYOT GAGE PLANE. (.). (.) NOTE:. DIMENSIONS IN MILLIMETER/(INCH). DRAWING NOT TO SCALE. DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED.mm (.") PER SIDE. DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED.mm (.") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.mm (.") MAX DETAIL A DETAIL A TYP. ±. (. ±.) SEATING PLANE.9 ±. (.9 ±.). (.) MAX.. (..) TYP. (.9) BSC. ±. (. ±.) NOTE. (.) REF. ±. (. ±.) MSOP (MS). MIN. ±. TYP. BSC RECOMMENDED SOLDER PAD LAYOT. ±.. ±... (..) S Package -Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # --).. (..) TYP..9 (..)....9 (..) (..) NOTE: INCHES TYP. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED." (.mm).. (..). (.) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights... (.9.9).9.9 (..) NOTE.. (..9) NOTE SO Lf

12 LTCL/LTCL TYPICAL APPLICATIO Tiny -Chip Data-Acquistion System V.µF µf V V IN AGND µf + LTC9-99Ω pf V REF V CC IN + SCK LTCL IN GND CONV GAIN CONTROL ADC CONTROL LTC9- (IN TSOT- PACKAGE) COMPACTLY ADDS db OF INPT GAIN RANGE TO THE LTCL (IN MSOP -PIN PACKAGE). SINGLE V SPPLY L/L TA RELATED PARTS PART NMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION -Bit Serial I/O ADCs LTC/LTC9.ksps/.ksps.mW/.mW -Channel with Ref. Input (LTC), -Channel (LTC9), V LTC ksps mw -Channel, Bipolar or nipolar Operation, Internal Reference, V LTC ksps mw SO- with Internal Reference, V LTC.Msps 9mW Serial I/O, Bipolar or nipolar, Internal Reference LTC ksps mw SO- with Internal Reference, Bipolar or nipolar, V LTC/LTC ksps.mw SO-, MS, -Channel, V/SO-, MS, -Channel, V -Bit Serial I/O ADCs LTC ksps mw -Pin SSOP, nipolar or Bipolar, Reference, V LTC ksps mw Serial/Parallel I/O, Internal Reference, V -Bit Serial I/O ADCs LTC9 ksps mw Configurable Bipolar or nipolar Input Ranges, V LTC/LTC ksps.mw SO-, MS, -Channel, V/SO-, MS, -Channel, V LTCL/LTCL ksps.mw SO-, MS, -Channel, V/SO-, MS, -Channel, V References LT Micropower Precision Series Reference Bandgap, µa Supply Current, ppm/ C, Available in SOT- LT9 Micropower Low Dropout Reference µa Supply Current, ppm/ C, SOT- Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - Lf LT/TP K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION

FEATURES DESCRIPTIO TYPICAL APPLICATIO. LTC1864L/LTC1865L µpower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP APPLICATIO S

FEATURES DESCRIPTIO TYPICAL APPLICATIO. LTC1864L/LTC1865L µpower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP APPLICATIO S LTCL/LTCL µpower, V, -Bit, ksps - and -Channel ADCs in MSOP FEATRES -Bit ksps ADCs in MSOP Package Single V Supply Low Supply Current: µa (Typ) Auto Shutdown Reduces Supply Current to µa at ksps True Differential