DESCRIPTIO FEATURES APPLICATIO S. LTC1063 DC Accurate, Clock-Tunable 5th Order Butterworth Lowpass Filter TYPICAL APPLICATIO

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1 FEATRES Clock-Tunable Cutoff Frequency mv DC Offset (Typical) db CMRR (Typical) Internal or External Clock µv RMS Clock Feedthrough : Clock-to-Cutoff Frequency Ratio 9µV RMS Total Wideband Noise.% THD at V RMS Output Level khz Maximum Cutoff Frequency Cascadable for Faster Roll-Off Operates from ±. to ±V Power Supplies Self-Clocking with RC Available in -Pin DIP and -Pin SO Wide Packages APPLICATIO S Audio Strain Gauge Amplifiers Anti-Aliasing Filters Low Level Filtering Digital Voltmeters Hz Lowpass Filters Smoothing Filters Reconstruction Filters, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. LTC DC Accurate, Clock-Tunable th Order Butterworth Lowpass Filter DESCRIPTIO The LTC is the first monolithic filter providing both clock-tunability, low DC output offset and over -bit DC accuracy. The frequency response of the LTC closely approximates a th order Butterworth polynomial. With appropriate PCB layout techniques the output DC offset is typically mv and is constant over a wide range of clock frequencies. With ±V supplies and ±V input voltage range, the CMR of the device is db. The filter cutoff frequency is controlled either by an internal or external clock. The clock-to-cutoff frequency ratio is :. The on-board clock is power supply independent, and it is programmed via an external RC. The µv RMS clock feedthrough is considerably reduced over existing monolithic filters. The LTC wideband noise is 9µV RMS, and it can process large AC input signals with low distortion. With ±.V supplies, for instance, the filter handles up to V RMS (9dB S/N ratio) while the standard khz THD is below.%; db dynamic ranges (S/N +THD) is obtained with input levels between V RMS and.v RMS. The LTC is available in -pin minidip and -pin SO wide packages. For a linear phase response, see LTC data sheet. TYPICAL APPLICATIO V ** LTC.kHz th Order Lowpass Filter V.µF GAIN (db) Frequency Response.µF *9.k pf* * SELF-CLOCKING SCHEME ** IF THE INPT VOLTAGE CAN EXCEED V +, CONNECT A SIGNAL DIODE BETWEEN PIN AND V +. TA 9 FREQENCY (khz) TA fa

2 LTC ABSOLTE MAXIMM RATINGS W W W (Note ) Total Supply Voltage (V + to V )....V Power Dissipation... mw Voltage at Any Input... (V.V) (V + +.V) Burn-In Voltage... V Operating Temperature Range... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR GND V CLK OT TOP VIEW N PACKAGE -LEAD PLASTIC DIP T JMAX = C, θ JA = C/W (N) J PACKAGE -LEAD CERAMIC DIP T JMAX = C, θ JA = C/W (J) V OS ADJ V + CLK IN W OBSOLETE PACKAGE Consider the N Package for Alternate Source Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: ATIO ORDER PART NMBER LTCCN LTCCJ LTCMJ Consult LTC Marketing for parts specified with wider operating temperature ranges. TOP VIEW NC GND NC V NC NC CLK OT 9 V OS ADJ NC NC V + NC NC CLK IN SW PACKAGE -LEAD PLASTIC SO WIDE T JMAX = C, θ JA = C/W ORDER PART NMBER LTCCSW ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at V S = ±V, f CLK = khz, f C = khz, R L = k, T A = C, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX NITS Clock-to-Cutoff Frequency Ratio (f CLK /f C ) ±.V V S ±.V ±. Maximum Clock Frequency (Note ) V S = ±.V MHz V S = ±V MHz V S = ±.V MHz Minimum Clock Frequency (Note ) ±.V V S ±.V, T A < C Hz Input Frequency Range.9f CLK Filter Gain V S = ±V, f CLK = khz, f C = Hz f IN = Hz... db... db V S = ±V, f CLK = khz, f C = khz f IN = Hz db f IN = khz =.f C... db... db f IN =.khz =.f C.9.. db... db f IN = khz =.f C... db... db fa

3 ELECTRICAL CHARACTERISTICS LTC The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at V S = ±V, f CLK = khz, f C = khz, R L = k, T A = C, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX NITS Filter Gain f IN = khz = f C... db... db f IN = khz = f C... db... db V S = ±.V, f CLK = khz, f C = khz f IN = khz... db...9 db f IN =.khz... db.9.. db f IN = khz... db... db f IN = khz... db... db Clock Feedthrough ±. V S ±.V µv RMS Wideband Noise (Note ) ±. V S ±.V, Hz < f < f CLK µv RMS THD + Wideband Noise (Note ) V S = ±.V, f C = khz, f IN = khz, db V RMS.V RMS Filter Output ± DC Swing V S = ±.V./../. V./. V V S = ±V./../. V./. V V S = ±.V./../. V./. V Input Bias Current na Dynamic Input Impedance MΩ Output DC Offset (Note ) V S = ±.V mv V S = ±V ± mv V S = ±.V mv Output DC Offset Drift V S = ±.V µv/ C V S = ±V µv/ C V S = ±.V µv/ C Self-Clocking Frequency (f OSC ) R (Pin to ) = k, C (Pin to GND) = pf V S = ±.V 99 khz 9 khz V S = ±V khz 9 khz V S = ±.V khz 9 khz External CLK Pin Logic Thresholds V S = ±.V Min Logical. V Max Logical. V V S = ±V Min Logical V Max Logical V V S = ±.V Min Logical. V Max Logical. V fa

4 LTC ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at V S = ±V, f CLK = khz, f C = khz, R L = k, T A = C, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX NITS Power Supply Current V S = ±.V, f CLK = khz.. ma. ma V S = ±V, f CLK = khz. ma ma V S = ±.V, f CLK = khz. ma. ma Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : The maximum clock frequency criterion is arbitrarily defined as: The frequency at which the filter AC response exhibits db of gain peaking. Note : At limited temperature ranges (i.e., T A C) the minimum clock frequency can be as low as Hz. The minimum clock frequency is arbitrarily defined as: the clock frequency at which the output DC offset changes by more than mv. Note : The wideband noise specification does not include the clock feedthrough. Note : To properly evaluate the filter s harmonic distortion an inverting output buffer is recommended as shown in the Test Circuit. An output buffer is not necessarily needed when measuring output DC offset or wideband noise. Note : The output DC offset is optimized for ±V supply. The output DC offset shifts when the power supplies change; however this phenomenon is repeatable and predictable. TYPICAL PERFOR A CE CHARACTERISTICS W R PINS TO (kω) 9 Self-Clocking Frequency vs R LTC R C = pf f OSC /RC C OTPT OFFSET (mv) Output Offset vs Clock, Low Clock Rates V S = ±V A: T A = C B: T A = C OTPT OFFSET (mv) Output Offset vs Clock, Medium Clock Rates V S = ±.V V S = ±V FREQENCY (khz) B A EXTERNAL CLOCK FREQENCY (Hz) V S = ±.V EXTERNAL CLOCK FREQENCY (khz) G G G fa

5 LTC TYPICAL PERFOR A CE CHARACTERISTICS W GAIN (db) 9 Gain vs Frequency; V S = ±.V Gain vs Frequency; V S = ±V Gain vs Frequency; V S = ±.V A. f CLK =.MHz B. f CLK = MHz C. f CLK = MHz = mv RMS T A = C A B INPT FREQENCY (khz) C GAIN (db) 9 A. f CLK = MHz B. f CLK = MHz C. f CLK = MHz D. f CLK = MHz =.V RMS T A = C A B C D INPT FREQENCY (khz) GAIN (db) 9 A. f CLK = MHz B. f CLK = MHz C. f CLK = MHz D. f CLK = MHz E. f CLK = MHz =.V RMS T A = C D A B C E INPT FREQENCY (khz) G G G THD + NOISE (%).. THD + Noise vs Input Voltage; V S = Single V f IN = khz, T A = C REPRESENTATIVE NITS B A THD (%).. THD vs Frequency; V S = Single V =.V RMS f C = khz, f CLK = khz S/N = db, T A = C REPRESENTATIVE NITS THD + NOISE (%).. THD + Noise vs Input Voltage; V S = ±V f IN = khz, T A = C REPRESENTATIVE NITS B A.. A. f C = khz, f CLK =.MHz B. f C = khz, f CLK = MHz INPT (V RMS ). FREQENCY (khz).. A. f C = khz, f CLK = MHz B. f C = khz, f CLK = MHz INPT (V RMS ) G G G9 THD (%).. THD vs Frequency; V S = ±V =.V RMS f C = khz, f CLK = MHz S/N =.db, T A = C REPRESENTATIVE NITS THD + NOISE (%).. THD + Noise vs Input Voltage; V S = ±.V f IN = khz, T A = C REPRESENTATIVE NITS B A THD (%).. THD vs Frequency; V S = ±.V =.V RMS f C = khz, f CLK = MHz S/N = db, T A = C REPRESENTATIVE NITS. FREQENCY (khz).. A. f C = khz, f CLK = MHz B. f C = khz, f CLK = MHz INPT (V RMS ). FREQENCY (khz) G G G fa

6 LTC TYPICAL PERFOR A CE CHARACTERISTICS W PASSBAND GAIN (db) Passband Gain and Phase vs Input Frequency ±.V V S ±.V, T A = C A A B PHASE PHASE f CLK =khz f C =khz B f CLK =MHz f C =khz k k k INPT FREQENCY (Hz) G PHASE (DEG) PHASE MISMATCH (±DEG) Phase Matching V S = ±.V = V RMS f CLK = MHz f C = khz INPT FREQENCY (khz) G POWER SPPLY CRRENT (ma) 9 Power Supply Current vs Power Supply Voltage C C C TOTAL POWER SPPLY VOLTAGE (V) G Transient Response HORIZONTAL:.ms/DIV, VERTICAL: V/DIV V S = ±V, f C = khz, = khz ±V P SQARE WAVE G fa

7 LTC PI F CTIO S Power Supply Pins (Pins,, N Package) The positive and negative supply pin should be bypassed with a high quality.µf ceramic capacitor. In applications where the clock pin () is externally swept to provide several cutoff frequencies, the output DC offset variation is minimized by connecting an additional µf solid tantalum capacitor in parallel with the.µf disc ceramic. This technique was used to generate the graphs of the output DC offset variation versus clock; they are illustrated in the Typical Performance Characteristics section. When the power supply voltage exceeds ±V, and when V is applied before V +, if V + is allowed to go below ground, connect a signal diode between the positive supply pin and ground to prevent latch-up (see Typical Applications). Ground Pin (Pin, N Package) The ground pin merges the internal analog and digital ground paths. The potential of the ground pin is the reference for the internal switched-capacitor resistors, and the reference for the external clock. The positive input of the internal op amp is also tied to the ground pin. For dual supply operation, the ground pin should be connected to a high quality AC and DC ground. A ground plane, if possible, should be used. A poor ground will degrade DC offset and it will increase clock feedthrough, noise and distortion. A small amount of AC current flows out of the ground pin whether or not the internal oscillator is used. The frequency of the ground current equals the frequency of the internal or external clock. The average value of this current is approximately µa, µa, µa for ±.V, ±V and ±.V supplies respectively. For single supply operation, the ground pin should be preferably biased at half supply (see Typical Applications). V OS Adjust Pin (Pin, N Package) The V OS adjust pin can be used to trim any small amount of output DC offset voltage or to introduce a desired output DC level. The DC gain from the V OS adjust pin to the filter output pin equals two. Any DC voltage applied to this pin will reflect at the output pin of the filter multiplied by two. If the V OS adjust pin is not used, it should be shorted to the ground pin. The DC bias current flowing into the V OS adjust pin is typically pa. Pin should always be connected to an AC ground; AC signals applied to this pin will degrade the filter response. Input Pin (Pin, N Package) Pin is the filter input and it is connected to an internal switched-capacitor resistor. If the input pin is left floating, the filter output will saturate. The DC input impedance of pin is very high; with ±V supplies and MHz clock, the DC input impedance is typically GΩ. A resistor, R IN, in series, with the input pin will not alter the value of the filter s DC output offset (Figure ). R IN should, however, be limited to a maximum value (Table ), otherwise the filter s passband flatness will be affected. Refer to the Applications Information section for more details. R IN V LTC V + f CLK Figure. F Table. R IN(MAX) vs Clock and Power Supply R IN(MAX) V S = ±.V V S = ±V V S = ±.V f CLK = MHz.k f CLK = MHz.k.9k f CLK = MHz.k k.k f CLK = MHz k k 9.k f CLK = khz k k k f CLK = khz k k k fa

8 LTC PI F CTIO S Output Pin (Pin, N Package) Pin is the filter output. This pin can typically source over ma and sink ma. Pin should not drive long coax cables, otherwise the filter s total harmonic distortion will degrade. Clock Input Pin (Pin, N Package) An external clock when applied to pin tunes the filter cutoff frequency. The clock-to-cutoff frequency ratio is :. The high (V HIGH ) and low (V LOW ) clock logic threshold levels are illustrated in Table. Square wave clocks with duty cycles between % and % are strongly recommended. Sinewave clocks are not recommended. Table. Clock Pin Threshold Levels POWER SPPLY V HIGH V LOW V S = ±.V.V.V V S = ±V V V V S = ±.V.V.V V S = ±V.V.V V S = V, V V V V S =, V 9.V.V V S =V, V V 9V Clock Output Pin (Pin, N Package) Any external clock applied to the clock input pin appears at the clock output pin. The duty cycle of the clock output equals the duty cycle of the external clock applied to the clock input pin. The clock output pin swings to the power supply rails. When the LTC is used in a self-clocking mode, the clock of the internal oscillator appears at the clock output pin with a % duty cycle. The clock output pin can be used to drive other LTCs or other ICs. The maximum capacitance, C L(MAX), the clock output pin can drive is illustrated in Figure. MAXIMM LOAD CAPACITANCE (pf ) V S = ±.V T A = C V S = ±V V S = ±.V 9 CLOCK FREQENCY (MHz) F Figure. Maximum Load Capacitance at the Clock Output Pin TEST CIRCIT + k LT k V LTC V +.µf pf.µf CLOCK IN TC Figure. Test Circuit for THD fa

9 LTC APPLICATIO S I FOR ATIO Self-Clocking Operation The LTC features an internal oscillator which can be tuned via an external RC. The LTC s internal oscillator is primarily intended for generation of clock frequencies below khz. The first curve of the Typical Performance Characteristics section shows how to quickly choose the value of the RC for a given frequency. More precisely, the frequency of the internal oscillator is equal to: f CLK = K/RC W For clock frequencies (f CLK ) below khz, K equals.. Figure b shows the variation of the parameter K versus clock frequency and power supply. First choose the desired clock frequency, (f CLK < khz), then through Figure b pick the right value of K, set C = pf and solve for R. Example : f CTOFF = khz, f CLK = khz, V S = ±V, T A = C, K =., C = pf then, R = (.)/(khz pf) =.k. LTC V V + R Figure a. C Fa Note a pf parasitic capacitance is assumed in parallel with the external pf timing capacitor. Figure shows the clock frequency variation from C to C. The khz clock of Example will change by.% at C. f CLK CHANGE NORMALIZED TO ITS C VALE (%) C = pf V S = ±.V V S = ±.V T A = C V S = ±V V S = ±.V T A = C V S = ±.V V S = ±V CLOCK FREQENCY (khz) Figure. f CLK vs Temperature F For a very limited temperature range, the internal oscillator of the LTC can be used to generate clock frequencies above khz (Figures and ). The data of Figure is derived from several devices. For a given external (RC) value, the observed device-to-device clock frequency variation was ±% (V S = ±V), and ±.% for V S = ±.V. Example : f CTOFF = khz, f CLK = MHz, V S = ±.V, T A = C, C = pf from Figure, K =., and, R = (.)/(MHz pf) =.k. K F CLK = K/RC C = pf T A = C V S = ±.V V S = ±.V V S = ±V INTERNAL CLOCK FREQENCY (khz) Fb K V S = ±.V V S = ±.V..... CLOCK FREQENCY (MHz) f CLK = K/RC C = pf T A = C V S = ±V F Figure b. f CLK vs K Figure. f CLK vs K fa 9

10 LTC APPLICATIO S I FOR ATIO K W V S = ±.V V S = ±.V..... CLOCK FREQENCY (MHz) f CLK = K/RC C = pf T A = C V S = ±V Figure. f CLK vs K F A pf parasitic capacitance is assumed in parallel with the external pf capacitor. A ±% clock frequency variation from device to device can be expected. The MHz clock frequency designed above will typically drift to.mhz at C (Figure ). The internal clock of the LTC can be overridden by an external clock provided that the external clock source can drive the timing capacitor, C, which is connected from the clock input pin to ground. Output Offset The DC output offset of the LTC is trimmed to typically less than ±mv. The trimming is done at V S = ±V. To obtain optimum DC offset performance, appropriate PC layout techniques should be used and the filter IC should be soldered to the PC board. A socket will degrade the output DC offset by typically mv. The output DC offset is sensitive to the coupling of the clock output pin (N package) to the negative power supply pin (N package). The negative supply pin should be well decoupled. When the surface mount package is used, all the unused pins should be grounded. When the power supplies are fixed, the output DC offset should not change by more than ±µv over Hz to MHz clock frequency variation. When the filter clock frequency is fixed, the output DC offset will typically change by mv (mv) when the power supply varies from ±V to ±.V (±.V). See Typical Performance Characteristics. Common Mode Rejection Ratio The common mode rejection ratio is defined as the change of the output DC offset with respect to the DC change of the input voltage applied to the filter. CMRR = log ( V OS OT / )(db) Table illustrates the common mode rejection for three power supplies and three temperatures. The common mode rejection improves if the output offset is adjusted to approximately V. The output offset can be adjusted via pin (N package) (see Typical Applications). Table. CMRR Data, f CLK = khz C POWER SPPLY C C C (V OS Nulled) ±.V ±.V db db db db ±V ±V db 9dB db db ±.V ±V db db db db The above data is valid for clock frequencies up to khz, 9kHz, MHz, for V S = ±.V, ±V, ±.V respectively. Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics which are present at the filter s output pin. The clock feedthrough is tested with the filter input grounded and it depends on the quality of the PC board layout and power supply decoupling. Any parasitic switching transients, during the rise and fall of the incoming clock, are not part of the clock feedthrough specifications; their amplitude strongly depends on scope probing techniques as well as ground quality and power supply bypassing. For a power supply V S = ±V, the clock feedthrough of the LTC is µv RMS ; for V S = ±.V, the clock feedthrough approaches µv RMS. Figure shows a typical scope photo of the LTC output pin when the input pin is grounded. The filter cutoff frequency was khz, while scope bandwidth was chosen to be MHz such as switching transients above the khz clock frequency will show. Wideband Noise The wideband noise of the filter is the RMS value of the device s output noise spectral density. The wideband noise data is used to determine the operating signal-to- fa

11 LTC APPLICATIO S I FOR ATIO noise ratio at a given distortion level. The wideband noise (µv RMS ) is nearly independent of the value of the clock frequency and excludes the clock feedthrough. The LTC s typical wideband noise is 9µV RMS. Figure 9 shows the same scope photo as Figure but with a more sensitive vertical scale: The clock feedthrough is imbedded in the filter s wideband noise. The peak-to-peak wideband noise of the filter can be clearly seen; it is approximately µv P-P. Note that µv P-P equals the 9µV RMS wideband noise of the part, multiplied by a crest factor or.. mv/div.mv/div W µs/div f CLK = khz, f C = khz, V S = ±V, MHz SCOPE BW F Figure. LTC Output Clock Feedthrough + Noise Aliasing Aliasing is an inherent phenomenon of sampled data filters and it primarily occurs when the frequency of an input signal approaches the sampling frequency. For the LTC, an input signal whose frequency is in the range of f CLK ±% will generate an alias signal into the filter s passband and stopband. Table shows details. Example: LTC, f CLK = khz, f C = khz, f IN = (9.kHz, mv RMS ) f ALIAS = (Hz,.mV RMS ) An input RC can be used to attenuate incoming signals close to the filter clock frequency (Figure ). A Butterworth passband response will be maintained if the value of the input resistor follows Table. Table. Aliasing Data OTPT AMPLITDE REFERENCED TO INPT FREQENCY OTPT FREQENCY INPT SIGNAL.999f CLK. f CLK db.99 f CLK. f CLK db.99 f CLK. f CLK db.9f CLK. f CLK. db.9 f CLK. f CLK. db.9f CLK. f CLK. db.9 f CLK. f CLK db.9 f CLK. f CLK db.9 f CLK. f CLK db.9 f CLK. f CLK. db.9 f CLK. f CLK. db.9 f CLK. f CLK. db.9 f CLK. f CLK. db.9 f CLK. f CLK. db.9 f CLK. f CLK. db.9 f CLK. f CLK. db R µs/div f CLK = khz, f C = khz, V S = ±V, MHz SCOPE BW F9 C LTC V V +.µf f CLK.µF Figure 9. LTC Output Clock Feedthrough + Noise f CLK f CLK πrc F Figure. Adding an Input Anti-Aliasing RC fa

12 LTC APPLICATIO S I FOR ATIO W Group Delay The group delay of the LTC closely approximates the delay of an ideal -pole Butterworth lowpass filter (Figure, Curve A). To linearize the group delay of the LTC (Figure, Curve B), use an input resistor about six times higher than the maximum value of R IN, shown in Table. The passband response of the group delay corrected filter approximates a -pole Bessel response while its transition band rolls off like a Butterworth. (ms) 9 (A) LTC BTTERWORTH (B) GROP DELAY CORRECTED 9 INPT FREQENCY (khz) Figure. Group Delay F TYPICAL APPLICATIO S µf TANT + V.99k.k.µF Single V Supply Operation (f C =.khz) LTC k pf V.µF TA V.V µf TANT + Adjusting V OS(OT) for ±. Supply Operation LTC.µF * OPTIONAL, N k.mv V +.V f CLK.µF *.V k LT9 TA Cascading Two LTCs for Steeper Roll-Off * V.µF LTC R V.µF C Sharing Clock for Multichannel Applications * V.µF LTC R V.µF C V.µF LTC f C (/RC)(/) WIDEBAND NOISE = µv RMS ATTENATION AT f = f C = db V.µF V.µF * LTC V.µF * IF THE INPT VOLTAGE CAN EXCEED V +, CONNECT A SIGNAL DIODE BETWEEN PIN AND V +. TA * IF THE INPT VOLTAGE CAN EXCEED V +, CONNECT A SIGNAL DIODE BETWEEN PIN AND V +. TA fa

13 LTC PACKAGE DESCRIPTIO J Package -Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # --).. (..) FLL LEAD OPTION. BSC (. BSC) CORNER LEADS OPTION ( PLCS).. (..) HALF LEAD OPTION. (.) MIN. (.) RAD TYP. (.) MAX.. (..). (.) MAX.. (..).. (..) NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.. (..).. (..). (.) BSC.. MIN J OBSOLETE PACKAGE fa

14 LTC PACKAGE DESCRIPTIO N Package -Lead PDIP (Narrow. Inch) (Reference LTC DWG # --).* (.) MAX. ±.* (. ±.).. (..).. (..). ±. (. ±.).. (..) ( ). (.) TYP. (.) BSC NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) MIN. ±. (. ±.). (.) MIN N fa

15 LTC PACKAGE DESCRIPTIO SW Package -Lead Plastic Small Outline (Wide. Inch) (Reference LTC DWG # --). ±. TYP N. BSC. ±..9. (.9.9) NOTE 9 N. MIN. ±. NOTE.9.9 (..) N/ N/ RECOMMENDED SOLDER PAD LAYOT. (.) RAD MIN.9.99 (.9.9) NOTE..9 (..) TYP.9. (..).. (.9.)..9. (.) (.9.) NOTE BSC..9.. (..) (..) TYP NOTE: INCHES. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED." (.mm).. (..) S (WIDE) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fa

16 LTC TYPICAL APPLICATIO S Low Noise DC Accurate Clock-Tunable Notch R k ±.% V µf TANT + f f NOTCH = CLK 9. NOTCH DEPTH > db (LTC)V OPT DC OFFSET = OS µv OTPT NOISE = µv RMS f NOTCH f( db)bw =..µf LTC R 9.k ±.%.µf V + V f CLK + LT GAIN (db) Hz f CLK = khz f n = Hz INPT FREQENCY (Hz) TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC Clock-Tunable th Order Bessel Lowpass Filter mv Offset, db CMR LTC- khz Linear Phase Lowpass Filter Continuous Time, Fully Differential In/Out LTC- Low Noise,.MHz Lowpass Filter Continuous Time, Fully Differential In/Out LT Low Noise Op Amp and Inverter Building Block Single Ended to Differential Conv LT Low Noise, MHz th Order Building Block Lowpass or Bandpass, Differential Outputs LTC9- Linear Phase, DC Accurate, th Order Lowpass Resistor Set Clock, F C < khz LTC9- Linear Phase, DC Accurate, th Order Lowpass Resistor Set Clock, F C < khz LT-. Low Noise Differential Amp and MHz Lowpass µv RMS Noise khz-mhz V Supply LT- Low Noise Differential Amp and MHz Lowpass µv RMS Noise khz-mhz V Supply LT/LT 9 REV A PRINTED IN SA Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - LINEAR TECHNOLOGY CORPORATION 99 fa