DESCRIPTIO TYPICAL APPLICATIO LT1113 Dual Low Noise, Precision, JFET Input Op Amp FEATURES APPLICATIO S

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1 LT Dual Low Noise, Precision, JFET Input Op Amp FEATRES % Tested Low Voltage Noise: nv/ Hz Max SO- Package Standard Pinout Voltage Gain:. Million Min Offset Voltage:.mV Max Offset Voltage Drift: µv/ C Max Input Bias Current, Warmed p: pa Max Gain Bandwidth Product:.MHz Typ Guaranteed Specifications with ±V Supplies Guaranteed Matching Specifications APPLICATIO S Photocurrent Amplifiers Hydrophone Amplifiers High Sensitivity Piezoelectric Accelerometers Low Voltage and Current Noise Instrumentation Amplifier Front Ends Two and Three Op Amp Instrumentation Amplifiers Active Filters DESCRIPTIO The LT achieves a new standard of excellence in noise performance for a dual JFET op amp. The.nV/ Hz khz noise combined with low current noise and picoampere bias currents makes the LT an ideal choice for amplifying low level signals from high impedance capacitive transducers. The LT is unconditionally stable for gains of or more, even with load capacitances up to pf. Other key features are.mv V OS and a voltage gain of million. Each individual amplifier is % tested for voltage noise, slew rate and gain bandwidth. The design of the LT has been optimized to achieve true precision performance with an industry standard pinout in the S- package. A set of specifications are provided for ±V supplies and a full set of matching specifications are provided to facilitate the use of the LT in matching dependent applications such as instrumentation amplifier front ends., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO Low Noise Hydrophone Amplifier with DC Servo khz Input Noise Voltage Distribution R* M R.9k V TO V V S = ±V R C* Ω HYDRO- PHONE C T R M R M / LT V TO V R k C.µF / LT DC OTPT.mV FOR T A < C OTPT VOLTAGE NOISE = nv/ Hz AT khz (GAIN = ) C C T pf TO pf; RC > RC T ; *OPTIONAL R M R M OTPT TA PERCENT OF NITS (%) S OP AMPS TESTED INPT VOLTAGE NOISE (nv/ Hz) TA fb

2 LT ABSOLTE AXI RATI GS W W W Supply Voltage C to C... ±V C to C... ±V Differential Input Voltage... ±V Input Voltage (Equal to Supply Voltage)... ±V Output Short Circuit Duration... Minute Storage Temperature Range... C to C (Note ) Operating Temperature Range LTAC/LTC (Note )... C to C LTAM/LTM (OBSOLETE) C to C Specified Temperature Range LTAC/LTC (Note )... C to C LTAM/LTM (OBSOLETE) C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR OT A IN A IN A V A TOP VIEW N PACKAGE -LEAD PDIP T JMAX = C, θ JA = C/W (N) J PACKAGE -LEAD CERDIP T JMAX = C, θ JA = C/W (J) B V OT B IN B IN B W OBSOLETE PACKAGE Consider the N Package for Alternate Source ATIO ORDER PART NMBER LTACN LTCN LTAMJ LTMJ OT A IN A IN A V A TOP VIEW S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/W B V OT B IN B IN B ORDER PART NMBER LTCS S PART MARKING Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS LTAM/AC LTM/C SYMBOL PARAMETER CONDITIONS (Note ) MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage.... mv V S = ±V.... mv I OS Input Offset Current Warmed p (Note ) pa I B Input Bias Current Warmed p (Note ) pa e n Input Noise Voltage.Hz to Hz.. µv P-P Input Noise Voltage Density f O = Hz nv/ Hz f O = Hz.... nv/ Hz i n Input Noise Current Density f O = Hz, f O = Hz (Note ) fa/ Hz R IN Input Resistance Differential Mode Ω Common Mode V CM = V to V Ω V CM = V to V Ω C IN Input Capacitance pf V S = ±V pf V CM Input Voltage Range (Note ).... V.... V CMRR Common Mode Rejection Ratio V CM = V to V 9 9 db V S = ±V, V CM = V,, unless otherwise noted. fb

3 ELECTRICAL CHARACTERISTICS V S = ±V, V CM = V,, unless otherwise noted. LT LTAM/AC LTM/C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS PSRR Power Supply Rejection Ratio V S = ±.V to ± V 9 db A VOL Large-Signal Voltage Gain V O = ±V, R L = k V/mV V O = ±V, R L = k V/mV V OT Output Voltage Swing R L = k ±. ±. ±. ±. V R L = k ±. ±. ±. ±. V SR Slew Rate R L k (Note 9) V/µs GBW Gain Bandwidth Product f O = khz.... MHz t S Settling Time.%, A V =, R L = k,.. µs C L pf, V Step Channel Separation f O = Hz, V O = ±V, R L = k db I S Supply Current per Amplifier.... ma V S = ±V.... ma V OS Offset Voltage Match.... mv I B Noninverting Bias Current Match Warmed p (Note ) pa CMRR Common Mode Rejection Match (Note ) 9 9 db PSRR Power Supply Rejection Match (Note ) 9 9 db The denotes specifications which apply over the temperature range C T A C. V S = ±V, V CM = V, unless otherwise noted. (Note ) LTAC LTC SYMBOL PARAMETER CONDITIONS (Note ) MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage.... mv V S = ±V.... mv V OS Average Input Offset (Note ) µv/ C Temp Voltage Drift I OS Input Offset Current pa I B Input Bias Current pa V CM Input Voltage Range V.... V CMRR Common Mode Rejection Ratio V CM = V to.9v db PSRR Power Supply Rejection Ratio V S = ±.V to ±V 99 9 db A VOL Large-Signal Voltage Gain V O = ±V, R L = k 9 V/mV V O = ±V, R L = k V/mV V OT Output Voltage Swing R L = k ±. ±. ±. ±. V R L = k ±. ±. ±. ±. V SR Slew Rate R L k (Note 9).... V/µs GBW Gain Bandwidth Product f O = khz.... MHz I S Supply Current per Amplifier.... ma V S = ±V.... ma V OS Offset Voltage Match mv I B Noninverting Bias Current Match pa CMRR Common Mode Rejection Match (Note ) 9 9 db PSRR Power Supply Rejection Match (Note ) db fb

4 LT ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the temperature range C T A C. V S = ±V, V CM = V, unless otherwise noted. (Note ) LTAC LTC SYMBOL PARAMETER CONDITIONS (Note ) MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage.... mv V S = ±V...9. mv V OS Average Input Offset µv/ C Temp Voltage Drift I OS Input Offset Current 9 pa I B Input Bias Current pa V CM Input Voltage Range.... V.... V CMRR Common Mode Rejection Ratio V CM = V to.v 9 9 db PSRR Power Supply Rejection Ratio V S = ±.V to ± V db A VOL Large-Signal Voltage Gain V O = ±V, R L = k V/mV V O = ±V, R L = k V/mV V OT Output Voltage Swing R L = k ±. ±. ±. ±. V R L = k ±. ±. ±. ±. V SR Slew Rate R L k.... V/µs GBW Gain Bandwidth Product f O = khz MHz I S Supply Current per Amplifier.... ma V S = ±V.... ma V OS Offset Voltage Match.... mv I B Noninverting Bias Current Match 9 pa CMRR Common Mode Rejection Match (Note ) 9 9 db PSRR Power Supply Rejection Match (Note ) 9 9 db The denotes specifications which apply over the temperature range C T A C. V S = ±V, V CM = V, unless otherwise noted. (Note ) LTAM LTM SYMBOL PARAMETER CONDITIONS (Note ) MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage...9. mv V S = ±V...9. mv V OS Average Input Offset (Note ) µv/ C Temp Voltage Drift I OS Input Offset Current.. na I B Input Bias Current na V CM Input Voltage Range.... V.... V CMRR Common Mode Rejection Ratio V CM = V to.v db PSRR Power Supply Rejection Ratio V S = ±.V to ±V 9 9 db fb

5 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the temperature range C T A C. V S = ±V, V CM = V, unless otherwise noted. (Note ) LT LTAM LTM SYMBOL PARAMETER CONDITIONS (Note ) MIN TYP MAX MIN TYP MAX NITS A VOL Large-Signal Voltage Gain V O = ±V, R L = k V/mV V O = ±V, R L = k V/mV V OT Output Voltage Swing R L = k ±. ±. ±. ±. V R L = k ±. ±. ±. ±. V SR Slew Rate R L k (Note 9).9... V/µs GBW Gain Bandwidth Product f O = khz.... MHz I S Supply Current Per Amplifier.... ma V S = ±V.... ma V OS Offset Voltage Match.... mv I B Noninverting Bias Current Match.. na CMRR Common Mode Rejection Match (Note ) 9 9 db PSRR Power Supply Rejection Match (Note ) 9 9 db Note : Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note : The LTC is guaranteed functional over the Operating Temperature Range of C to C. The LTM is guaranteed functional over the Operating Temperature Range of C to C. Note : The LTC is guaranteed to meet specified performance from C to C. The LTC is designed, characterized and expected to meet specified performance from C to C but is not tested or QA sampled at these temperatures. For guaranteed I grade parts, consult the factory. The LTM is guaranteed to meet specified performance from C to C. Note : Typical parameters are defined as the % yield of parameter distributions of individual amplifiers, i.e., out of LTs ( op amps) typically op amps will be better than the indicated specification. Note : Warmed-up I B and I OS readings are extrapolated to a chip temperature of C from C measurements and C characterization data. Note : Current noise is calculated from the formula: i n = (qi B ) / where q =. 9 coulomb. The noise of source resistors up to M swamps the contribution of current noise. Note : Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of.mv (A grade) to.mv (C grade). Note : This parameter is not % tested. Note 9: Slew rate is measured in A V = ; input signal is ±.V, output measured at ±.V. Note : The LT is designed, characterized and expected to meet these extended temperature limits, but is not tested at C and C. Guaranteed I grade parts are available. Consult factory. Note : CMRR and PSRR are defined as follows: () CMRR and PSRR are measured in µv/v on the individual amplifiers. () The difference is calculated between the matching sides in µv/v. () The result is converted to db. Note : The LT is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed-up chip temperature can be C to C higher than the ambient temperature. fb

6 LT TYPICAL PERFOR A W CE CHARACTERISTICS VOLTAGE NOISE (µv/div).hz to Hz Voltage Noise TIME (SEC) G TOTAL khz VOLTAGE NOISE DENSITY (nv/ Hz) k k khz Output Voltage Noise Density vs Source Resistance R SORCE V N SORCE RESISTANCE ONLY V S = ±V k k k M M M G SORCE RESISTANCE (Ω) V N G RMS VOLTAGE NOISE DENSITY (nv/ Hz) Voltage Noise vs Frequency /f CORNER Hz V S = ±V TYPICAL k k FREQENCY (Hz) G VOLTAGE NOISE (ATkHz)(nV/ Hz) 9 Voltage Noise vs Chip Temperature V S = ±V TEMPERATRE ( C) INPT BIAS AND OFFSET CRRENTS (A) Input Bias and Offset Currents vs Chip Temperature n n V S = ±V n n I B, V CM = V n I B, V CM = V p p p p p I OS, V CM = V I OS, V CM = V p TEMPERATRE ( C) INPT BIAS AND OFFSET CRRENTS (pa) Input Bias and Offset Currents Over the Common Mode Range V S = ±V NOT WARMED P BIAS CRRENT OFFSET CRRENT COMMON MODE RANGE (V) G G G COMMON MODE LIMIT (V) REFERRED TO POWER SPPLY V V. Common Mode Limit vs Temperature V = V TO V V = V TO V TEMPERATRE ( C) G COMMON-MODE REJECTION RATIO (db) Common Mode Rejection Ratio vs Frequency V S = ±V k k k M M FREQENCY (Hz) G POWER SPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency PSRR PSRR k k k FREQENCY (Hz) M G9 M fb

7 LT TYPICAL PERFOR VOLTAGE GAIN (db). Voltage Gain vs Frequency k M M FREQENCY (Hz) A W V S = ±V CE VOLTAGE GAIN (V/µV) CHARACTERISTICS 9 Voltage Gain vs Chip Temperature R L = k V S = ±V V O = ±V, R L = k V O = ±V, R L = k R L =k CHIP TEMPERATRE ( C) VOLTAGE GAIN (db). Gain and Phase Shift vs Frequency GAIN V S = ±V C L = pf PHASE FREQENCY (MHz) PHASE SHIFT (DEG) G G G Small-Signal Transient Response Large-Signal Transient Response Supply Current vs Supply Voltage mv/div A V = C L = pf V S = ±V, ±V µs/div G V/DIV A V = C L = pf V S = ±V µs/div G SPPLY CRRENT PER AMPLIFIER (ma) C C C ± ± ± SPPLY VOLTAGE (V) ± G V. OTPT VOLTAGE SWING (V) Output Voltage Swing vs Load Current C C V S = ±V TO ±V C C Capacitive Load Handling. C A V C V =.. I SINK I OTPT CRRENT (ma) SORCE CAPACITIVE LOAD (pf) G OVERSHOOT (%) V S = ±V R L k V O = mv P-P A V =, R F = k, C F = pf A V = G SLEW RATE (V/µs) Slew Rate and Gain Bandwidth Product vs Temperature SLEW RATE GBW TEMPERATRE ( C) G GAIN BANDWIDTH PRODCT (f O = khz)(mhz) fb

8 LT TYPICAL PERFOR A W CE CHARACTERISTICS PERCENT OF NITS Distribution of Offset Voltage Drift with Temperature (J) V S = ±V J OP AMPS OFFSET VOLTAGE DRIFT WITH TEMPERATRE (µv/ C) G9 PERCENT OF NITS Distribution of Offset Voltage Drift with Temperature (N, S) V S = ±V S N OP AMPS OFFSET VOLTAGE DRIFT WITH TEMPERATRE (µv/ C) G CHANGE IN OFFSET VOLTAGE (µv) Warm-p Drift V S = ±V S PACKAGE N PACKAGE J PACKAGE IN STILL AIR (S PACKAGE SOLDERED ONTO BOARD) TIME AFTER POWER ON (MINTES) G TOTAL HARMONIC DISTORTION NOISE (%) TOTAL HARMONIC DISTORTION NOISE (%)... THD and Noise vs Frequency for Noninverting Gain Z L = k pf V O = V P-P A V =,, MEASREMENT BANDWIDTH = Hz TO khz A V = A V = NOISE FLOOR. k k k FREQENCY (Hz)... A V = G THD and Noise vs Output Amplitude for Noninverting Gain Z L = k pf, f O = khz A V =,, MEASREMENT BANDWIDTH = Hz TO khz A V = A V = A V = NOISE FLOOR.. OTPT SWING (V P-P ) G TOTAL HARMONIC DISTORTION NOISE (%) TOTAL HARMONIC DISTORTION NOISE (%)... THD and Noise vs Frequency for Inverting Gain Z L = k pf V O = V P-P A V =,, MEASREMENT BANDWIDTH = Hz TO khz A V = A V = NOISE FLOOR. k k k FREQENCY (Hz)... THD and Noise vs Output Amplitude for Inverting Gain Z L = k pf, f O = khz A V =,, MEASREMENT BANDWIDTH = Hz TO khz A V = A V = A V = A V = NOISE FLOOR G.. OTPT SWING (V P-P ) G CHANNEL SEPARATION (db) INTERMODLATION DISTORTION (AT khz)(%)... Channel Separation vs Frequency V S = ±V R L = k V O = V P-P LIMITED BY THERMAL INTERACTION LIMITED BY PIN-TO-PIN CAPACITANCE k k k M M FREQENCY (Hz) V S = ±V R L = k A V = ± G CCIF IMD Test (Equal Amplitude Tones at khz, khz)*. m. OTPT SWING (V P-P ) G * See LT data sheet for definition of CCIF testing. fb

9 LT APPLICATI O S I FOR W ATIO The LT dual in the plastic and ceramic DIP packages are pin compatible with and directly replace such JFET op amps as the OPA and OPA with improved noise performance. Being the lowest noise dual JFET op amp available to date, the LT can replace many bipolar op amps that are used in amplifying low level signals from high impedance transducers. The best bipolar op amps will eventually loose out to the LT when transducer impedance increases due to higher current noise. The low voltage noise of the LT allows it to surpass every dual and most single JFET op amps available. For the best performance versus area available anywhere, the LT is offered in the narrow SO- surface mount package with standard pinout and no degradation in performance. The low voltage and current noise offered by the LT makes it useful in a wide range of applications, especially where high impedance, capacitive transducers are used such as hydrophones, precision accelerometers and photo diodes. The total output noise in such a system is the gain times the RMS sum of the op amp input referred voltage noise, the thermal noise of the transducer, and the op amp bias current noise times the transducer impedance. Figure shows total input voltage noise versus source resistance. In a low source resistance (<k) application the op amp voltage noise will dominate the total noise. This means the LT will beat out any dual JFET op amp, only the lowest noise bipolar op amps have the edge (at low source resistances). As the source resistance increases from k to k, the LT will match the best bipolar op amps for noise performance, since the thermal noise of the transducer (ktr) begins to dominate the total noise. A further increase in source resistance, above k, is where the op amp s current noise component (qi B R TRANS ) will eventually dominate the total noise. At these high source resistances, the LT will out perform the lowest noise bipolar op amp due to the inherently low current noise of FET input op amps. Clearly, the LT will extend the range of high impedance transducers that can be used for high signal to noise ratios. This makes the LT the best choice for high impedance, capacitive transducers. The high input impedance JFET front end makes the LT suitable in applications where very high charge sensitivity is required. Figure illustrates the LT in its inverting and noninverting modes of operation. A charge amplifier is shown in the inverting mode example; here the gain depends on the principal of charge conservation at the input of the LT. The charge across the transducer capacitance, C S, is transferred to the feedback capacitor C F, resulting in a change in voltage, dv, equal to dq/c F. k LT* INPT NOISE VOLTAGE (nv/ Hz) C S R S V O R S C S LT* LT LT SORCE RESISTANCE = R S = R * PLS RESISTOR PLS RESISTOR pf CAPACITOR V n = A V V n (OP AMP) ktr q I B R LT LT RESISTOR NOISE ONLY k k k M M SORCE RESISTANCE (Ω) M F Figure. Comparison of LT and LT Total Output khz Voltage Noise Versus Source Resistance fb 9

10 LT APPLICATI O S I FOR W ATIO R R F C B C F R B R OTPT C S R S OTPT C S R S R B = R S C B C S R S > R OR R TRANSDCER C B R B C B = C F C S R B = R F R S dq Q = CV; d t = I = C dv d t TRANSDCER F Figure. Noninverting and Inverting Gain Configurations The gain therefore is C F /C S. For unity gain, C F should equal the transducer capacitance plus the input capacitance of the LT and R F should equal R S. In the noninverting mode example, the transducer current is converted to a change in voltage by the transducer capacitance; this voltage is then buffered by the LT with a gain of R/R. A DC path is provided by R S, which is either the transducer impedance or an external resistor. Since R S is usually several orders of magnitude greater than the parallel combination of R and R, R B is added to balance the DC offset caused by the noninverting input bias current and R S. The input bias currents, although small at room temperature, can create significant errors over increasing temperature, especially with transducer resistances of up to M or more. The optimum value for R B is determined by equating the thermal noise (ktr S ) to the current noise (qi B ) times R S. Solving for R S results in R B = R S = V T /I B kt VT = = mv at C. q A parallel capacitor, C B, is used to cancel the phase shift caused by the op amp input capacitance and R B. Reduced Power Supply Operation The LT can be operated from ±V supplies for lower power dissipation resulting in lower I B and noise at the expense of reduced dynamic range. To illustrate this benefit, let s look at the following example: An LTCS operates at an ambient temperature of C with ±V supplies, dissipating mw of power (typical supply current =.ma for the dual). The SO- package has a θ JA of 9 C/W, which results in a die temperature increase of. C or a room temperature die operating temperature of. C. At ±V supplies, the die temperature increases by only one third of the previous amount or. C resulting in a typical die operating temperature of only. C. A degree reduction of die temperature is achieved at the expense of a V reduction in dynamic range. If no DC correction resistor is used at the input, the input referred offset will be the input bias current at the operating die temperature times the transducer resistance (refer to Input Bias and Offset Currents vs Chip Temperature graph in Typical Performance Characteristics section). A mv input V OS is the result of a na I B (at C) dropped across a M transducer resistance; at ±V supplies, the input offset is only mv (I B at C is pa). Careful selection of a DC correction fb

11 LT APPLICATI O S I FOR W ATIO INPT: ±.V Sine Wave LT Output OPA Output Figure. Voltage Follower with Input Exceeding the Common Mode Range ( V S = ±V) resistor (R B ) will reduce the IR errors due to I B by an order of magnitude. A further reduction of IR errors can be achieved by using a DC servo circuit shown in the applications section of this data sheet. The DC servo has the advantage of reducing a wide range of IR errors to the millivolt level over a wide temperature variation. The preservation of dynamic range is especially important when reduced supplies are used, since input bias currents can exceed the nanoamp level for die temperatures over C. To take full advantage of a wide input common mode range, the LT was designed to eliminate phase reversal. Referring to the photographs shown in Figure, the LT is shown operating in the follower mode (A V = ) at ±V supplies with the input swinging ±.V. The output of the LT clips cleanly and recovers with no phase reversal, unlike the competition as shown by the last photograph. This has the benefit of preventing lock-up in servo systems and minimizing distortion components. The effect of input and output overdrive on one amplifier has no effect on the other, as each amplifier is biased independently. Advantages of Matched Dual Op Amps In many applications the performance of a system depends on the matching between two operational amplifiers rather than the individual characteristics of the two op amps. Two or three op amp instrumentation amplifiers, tracking voltage references and low drift active filters are some of the circuits requiring matching between two op amps. The well-known triple op amp configuration in Figure illustrates these concepts. Output offset is a function of the difference between the two halves of the LT. This error cancellation principle holds for a considerable number of input referred parameters in addition to offset voltage and bias current. Input bias current will be the average of the two noninverting input currents (I B ). The difference between these two currents ( I B ) is the offset current of the instrumentation amplifier. Common mode and power supply rejections will be dependent only on the match between the two amplifiers (assuming perfect resistor matching). fb

12 LT APPLICATI IN V / LT IC V O S R k I FOR W R k ATIO R k C pf Typical performance of the instrumentation amplifier: Input offset voltage =.mv Input bias current = pa Input offset current = pa Input resistance = Ω / LT IC IN R k GAIN = BANDWIDTH = khz INPT REFERRED NOISE =.nv/ Hz AT khz WIDEBAND NOISE DC TO khz =. µv RMS C L.µF R Ω R k R k Figure. Three Op Amp Instrumentation Amplifier OTPT F The concepts of common mode and power supply rejection ratio match ( CMRR and PSRR) are best demonstrated with a numerical example: Assume CMRR A = µv/v or db, and CMRR B = 9µV/V or db, then CMRR = µv/v or 99dB; if CMRR B = -9µV/V which is still db, then CMRR = 9µV/V or db Clearly the LT, by specifying and guaranteeing all of these matching parameters, can significantly improve the performance of matching-dependent circuits. / LT IC C L Input noise =.µv P-P High Speed Operation The low noise performance of the LT was achieved by making the input JFET differential pair large to maximize the first stage gain. Increasing the JFET geometry also increases the parasitic gate capacitance, which if left unchecked, can result in increased overshoot and ringing. When the feedback around the op amp is resistive (R F ), a pole will be created with R F, the source resistance and capacitance (R S,C S ), and the amplifier input capacitance (C IN = pf). In closed loop gain configurations and with R S and R F in the kilohm range (Figure ), this pole can create excess phase shift and even oscillation. A small capacitor (C F ) in parallel with R F eliminates this problem. With R S (C S C IN ) = R F C F, the effect of the feedback pole is completely removed. R S C S C F R F C IN Figure. OTPT F fb

13 LT TYPICAL APPLICATI O S Accelerometer Amplifier with DC Servo C pf R M R k R k C µf V TO V ACCELEROMETER B & K MODEL OR EQIVALENT / LT V TO V / LT C µf R M R M RC = RC > R ( R/R) C OTPT =.mv/pc* =.mv/g** DC OTPT.mV OTPT NOISE = nv/ Hz AT khz *PICOCOLOMBS **g = EARTH S GRAVITATIONAL CONSTANT OTPT TA Paralleling Amplifiers to Reduce Voltage Noise Ω A / LT k k k Ω A / LT k k V / LT OTPT V V Ω An / LT V k k. ASSME VOLTAGE NOISE OF LT AND Ω SORCE RESISTOR =.nv/ Hz. GAIN WITH n LTs IN PARALLEL = n. OTPT NOISE = n.nv/ Hz. INPT REFERRED NOISE = OTPT NOISE =. nv/ Hz n n. NOISE CRRENT AT INPT INCREASES n TIMES. IF n =, GAIN =, BANDWIDTH = MHz, RMS NOISE, DC TO MHz = 9µV = µv TA fb

14 LT TYPICAL APPLICATI O S Low Noise Light Sensor with DC Servo C pf R M D N9 / LT C.µF OTPT HAMAMATS S-BK C D N9 V R k R k D N9 R k V V RC > CR C D = PARASITIC PHOTODIODE CAPACITANCE V O = mv/µwatt FOR nm WAVE LENGTH mv/µwatt FOR nm WAVE LENGTH / LT R k TA Hz Fourth Order Chebyshev Lowpass Filter (.db Ripple) V IN R k R 9k C nf R k V / LT V C nf R k R 9k R k C nf C nf / LT V OT TYPICAL OFFSET.mV % TOLERANCES FOR V IN = V P-P, V OT = db AT f > Hz = db AT f =.Hz LOWER RESISTOR VALES WILL RESLT IN LOWER THERMAL NOISE AND LARGER CAPACITORS TA fb

15 LT PACKAGE DESCRIPTIO J Package -Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # --) CORNER LEADS OPTION ( PLCS). BSC (. BSC).. (..).. (..) FLL LEAD OPTION.. (..).. (..) NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.. (..) HALF LEAD OPTION.. (..). (.) BSC. (.) MAX.. MIN OBSOLETE PACKAGE. (.) MIN. (.) RAD TYP. (.) MAX.. (..) J 9 S Package -Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # --).. (..).. (..). ±. (. ±.).* (.) MAX.9. (.9.) ( ). (.) TYP. (.) BSC *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). ±.* (. ±.). (.) MIN. (.). ±. (. ±.) MIN N 9 N Package -Lead PDIP (Narrow. Inch) (Reference LTC DWG # --).9.9* (..).. (..).. (..) TYP..9 (..).. (..).. (..).. (.9.9)..9. (..) (.) TYP BSC * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE Information furnished by Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights...** (..9) SO 9 fb

16 LT TYPICAL APPLICATI O S Light Balance Detection Circuit R M I C pf TO pf I PD V OT = M (I I ) PD, PD = HAMAMATS S-BK WHEN EQAL LIGHT ENTERS PHOTODIODES, V OT < mv. PD / LT VOT TA nity Gain Buffer with Extended Load Capacitance Drive Capability R k C / LT R Ω V OT C = C L.µF OTPT SHORT-CIRCIT CRRENT ( ma) WILL LIMIT THE RATE AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS V IN C L (I = C dv ) dt TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LT Single Low Noise Precision Op Amp V NOISE =.nv/ Hz Max LT Dual Low Noise Precision Op Amp V NOISE =.nv/ Hz Max LT9 Dual Low Noise Precision JFET Op Amp pa I B LT Dual Picoamp I B C-Load TM Op Amp I B = pa Max, pf C-Load, I S = µa LT Dual Picoamp I B C-Load Op Amp I B = pa Max, pf C-Load, I S = µa LT9 Single Low Noise Precision Op Amp Single LT LT9 Single Low Noise Precision Op Amp Single LT9 C-Load is a trademark of Linear Technology Corporation. fb LT/CPI.K REV B PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 99 Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () -