DESCRIPTION FEATURES APPLICATIONS. LT1457 Dual, Precision JFET Input Op Amp TYPICAL PERFORMANCE CHARACTERISTICS

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1 Dual, Precision JFET Input Op Amp FEATURES Handles 1,pF Capacitive Load 4µV Max Offset Voltage 1µV Max Offset Voltage in S8 Package pa Bias Current at 7 C 1nV/ Hz Voltage Noise 4V/µs Slew Rate 4µV/ C Drift 1dB Channel Separation APPLICATIONS U Sample-and-Hold (Drives Large Hold Capacitors) A/D and D/A Converters Photodiode Amplifiers Voltage-to-Frequency Converters DESCRIPTION U The is a dual, JFET input op amp optimized for handling large capacitive loads in combination with precision performance. Precision specifications include µv offset voltage in plastic and surface mount packages. At 7 C input bias current is pa, input offset current is pa. Channel separation is 1dB. Other dual JFET input op amps from Linear Technology include the LT17, which is three times faster than the but at the expense of significantly lower capacitive load handling capability; and the LT111 with 4.nV/ Hz voltage noise. TYPICAL PERFORMANCE CHARACTERISTICS U W Capacitive Load Handling Input Offset Voltage Distribution S8 Package OVERSHOOT (%) A V = +1 PERCENT OF UNITS DUALS ( OP AMPS) TESTED FROM RUNS CAPACITIVE LOAD (nf) INPUT OFFSET VOLTAGE (mv) 1. LT1147 TA1 TA 1

2 ABSOLUTE MAXIMUM RATINGS W W W Supply Voltage... ±V Differential Input Voltage... ±V Input Voltage... Equal to Supply Voltages Output Short-Circuit Duration... Indefinite Operating Temperature Range... C to 8 C Storage Temperature Range... C to C Lead Temperature (Soldering, 1 sec)... C U PACKAGE/ORDER INFORMATION OUT A IN A +IN A V 1 4 A TOP VIEW 8 7 N8 PACKAGE 8-LEAD PLASTIC DIP T JMAX = 1 C, θ JA = 1 C/ W B V + OUT B IN B +IN B U W U ORDER PART NUMBER ACN8 CN8 +IN A V +IN B IN B 1 4 TOP VIEW A B S8 PACKAGE 8-LEAD PLASTIC SOIC 8 7 IN A OUT A V + OUT B NOTE: THIS PIN CONFIGURATION DIFFERS FROM THE 8-LEAD DIP PIN LOCATIONS. INSTEAD, IT FOLLOWS THE INDUSTRY STANDARD LT11DS8 SO PACKAGE CONFIGURATION. T JMAX = 1 C, θ JA = 19 C/ W Consult factory for Industrial and Military grade parts. S8 S8 PART MARKING 147 ELECTRICAL CHARACTERISTICS,,V CM = V unless otherwise noted. (Note 1) AC C/S8 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V OS Input Offset Voltage AC/C 4 µv S8 1 µv I OS Input Offset Current Fully Warmed Up 4 pa I B Input Bias Current Fully Warmed Up ± ± ±7 ±7 pa Input Resistance-Differential Ω -Common-Mode V CM = 11V to 8V Ω V CM = 8V to 11V Ω Input Capacitance 4 4 pf e n Input Noise Voltage.1Hz to 1Hz..1 µv P P e n Input Noise Voltage Density f O = 1Hz 8 nv/ Hz f O = 1kHz (Note ) nv/ Hz i n Input Noise Current Density f O = 1Hz, 1kHz (Note ) fa/ Hz A VOL Large-Signal Voltage Gain V O = ±1V, R L = k V/mV V O = ±1V, R L = 1k 1 V/mV Input Voltage Range ± ± V V CMRR Common-Mode Rejection Ratio V CM = ±1.V db PSRR Power Supply Rejection Ratio V S = ±4.V to ±18V db V OUT Output Voltage Swing R L = k ±1 ±1 ±1 ±1 V SR Slew Rate 4 4 V/µs

3 ELECTRICAL CHARACTERISTICS,,V CM = V unless otherwise noted. (Note 1) AC C/S8 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS GBW Gain-Bandwidth Product (Note ) MHz I S Supply Current Per Amplifier ma Channel Separation DC to khz, V IN = ±1V 1 1 db ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS, V CM = V, C T A 7 C, unless otherwise noted. AC C/S8 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V OS Input Offset Voltage AC/C 9 µv S8 19 µv Average Temperature Coefficient of µv/ C Input Offset Voltage (Note 4) I OS Input Offset Current Warmed Up, T A = 7 C 18 pa I B Input Bias Current Warmed Up, T A = 7 C ± ± ± ± pa A VOL Large-Signal Voltage Gain V O = ±1V, R L = k 7 V/mV CMRR Common-Mode Rejection Ratio V CM = ±1.4V db PSRR Power Supply Rejection Ratio V S = ±4.V to ±18V db V OUT Output Voltage Swing R L = k ±1 ±1.8 ±1 ±1.8 V I S Supply Current Per Amplifier.. ma T A = 7 C ma, V CM = V, C T A 8 C, unless otherwise noted. (Note ) AC C/S8 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V OS Input Offset Voltage AC/C 1 1 µv S8 µv Average Temperature Coefficient of µv/ C Input Offset Voltage I OS Input Offset Current Warmed Up, T A = 8 C na I B Input Bias Current Warmed Up, T A = 8 C ±. ±.7 ±. ±.9 na A VOL Large-Signal Voltage Gain V O = ±1V, R L = k 1 11 V/mV CMRR Common-Mode Rejection Ratio V CM = ±1.4V db PSRR Power Supply Rejection Ratio V S = ±V to ±17V db V OUT Output Voltage Swing R L = k ±1 ±1.7 ±1 ±1. V I S Supply Current Per Amplifier T A = C.8.8 ma T A = 8 C ma The denotes the specifications which apply over the full operating temperature range. Note 1: Typical parameters are defined as the % yield of distributions of individual amplifiers; i.e., out of s ( op amps) typically 1 will be better than the indicated specification. Note : This parameter is tested on a sample basis only. Note : Current noise is calculated from the formula: i n = (qi b ) 1/, where q = 1. x 1 19 coulomb. The noise of source resistors up to 1GΩ swamps the contribution of current noise. Note 4: This parameter is not % tested. Note : Gain-Bandwidth product is not tested. It is guaranteed by design and by inference from the slew rate measurement. Note : The is not tested and not quality-assurance-sampled at C and at 8 C. These specifications are guaranteed by design, correlation, and/or inference from C, C, and 7 C tests.

4 TYPICAL PERFORMANCE CHARACTERISTICS U W INPUT BIAS AND OFFSET CURRENT (pa) 1 Input Bias and Offset Current vs Temperature V CM = V WARMED UP BIAS CURRENT OFFSET CURRENT INPUT BIAS CURRENT (pa) Input Bias Current Over the Common-Mode Range T A = 7 C CHANGE IN OFFSET VOLTAGE (µv) 1 9 Warm-Up Drift S8 PACKAGE N8 PACKAGE 7 AMBIENT 1 1 COMMON-MODE INPUT VOLTAGE (V) 1 4 TIME AFTER POWER ON (MINUTES) TPC1 TPC TPC PERCENT OF UNITS Input Offset Voltage Distribution N8 Package 9 DUALS (1 OP AMPS) TESTED FROM RUNS VOLTAGE GAIN (V/mV) Voltage Gain vs Temperature R L = k R L = 1k V O = ±1V OFFSET VOLTAGE CHANGE (µv) 1 1 Long Term Drift of Representative Units INPUT OFFSET VOLTAGE (mv) TIME (MONTHS) TPC4 TPC TPC RMS VOLTAGE NOISE DENSITY (nv/ Hz) 7 Voltage Noise vs Frequency 1/f CORNER = 8Hz 1 1 1k k 1k NOISE VOLTAGE (1µV/DIV).1Hz to 1Hz Noise 4 8 TIME (SECONDS) 1 CHANNEL SEPARATION (db) Channel Separation vs Frequency LIMITED BY THERMAL INTERACTION AT DC = 1dB LIMITED BY PIN TO PIN CAPACITANCE R S = 1Ω V IN = V P-P TO khz R S = 1k R L = k 1 1 1k 1k k 1M TPC7 TPC8 TPC9 4

5 TYPICAL PERFORMANCE CHARACTERISTICS U W CMRR (db) 1 Common-Mode Rejection Ratio vs Frequency COMMON -MODE RANGE (V) ± Common-Mode Range vs Temperature CMRR, PSRR (db) 1 11 Common-Mode and Power Supply Rejections vs Temperature V S = ±V TO ±17V FOR PSRR, V CM = ±1.V FOR CMRR PSRR CMRR 1 1k 1k k 1M 1M TPC1 TPC11 TPC1 1 Slew Rate, Gain-Bandwidth Product vs Temperature Supply Current vs Temperature Short-Circuit Current vs Time (One Output Shorted to Ground) SLEW RATE (V/µs) 8 4 SLEW FALL GBW SLEW RISE GBW (MHz) SUPPLY CURRENT PER AMPLIFIER (ma) 1 V S = ±V SHORT-CIRCUIT CURRENT (ma) 1 1 T A = C T A = 8 C T A = 8 C T A = C TIME FROM OUTPUT SHORT TO GROUND (MINUTES) TPC18 TPC14 TPC VOLTAGE GAIN (db) 1 1 Gain, Phase vs Frequency PHASE MARGIN =, C L = 1pF PHASE MARGIN = 1, C L = pf GAIN C L = pf C L = 1pF.1 1. FREQUENCY (MHz) PHASE C L = 1pF C L = pf 1 PHASE MARGIN (DEG) PEAK TO PEAK OUTPUT SWING (V) Undistorted Output Swing vs Frequency 1k k 1M 1M PSRR (db) 1 1 Power Supply Rejection Ratio vs Frequency NEGATIVE SUPPLY POSITIVE SUPPLY 1 1k 1k k 1M 1M TPC1 LT1147 TPC17 TPC1

TYPICAL PERFORMANCE CHARACTERISTICS U W Large-Signal Response A V = 1, C L = pf Small-Signal Response A V = 1,

Reversal Protection Most industry standard JFET input singl

, LF, LF1, LF, LF411, LF41, OP-, OP-1, OP-, and TL84) exhibit phase reversal at the output when the negative

The photos show a ±1V sine wave input (A), the response of an LF41A in the unity gain follower mode (B), and

6 TYPICAL PERFORMANCE CHARACTERISTICS U W Large-Signal Response A V = 1, C L = pf Small-Signal Response A V = 1, C L = pf Small-Signal Response A V = 1, C L = 1,pF TPC19 TPC TPC1 APPLICATIONS INFORMATION U W U U Phase Reversal Protection Most industry standard JFET input single, dual, and quad op amps (e.g., LF, LF1, LF, LF411, LF41, OP-, OP-1, OP-, and TL84) exhibit phase reversal at the output when the negative common-mode limit at the input is exceeded (i.e., below 1V with ±V supplies). The photos show a ±1V sine wave input (A), the response of an LF41A in the unity gain follower mode (B), and the response of the (C). The phase reversal of photo (B) can cause lock-up in servo systems. The does not phase-reverse due to a unique phase reversal protection circuit. AI1 AI AI (A) ±1V Sine Wave Input (B) LF41A Output (C) Output All Photos V/Div Vertical Scale, µs/div Horizontal Scale

7 APPLICATIONS INFORMATION U W U U High Speed Operation When the feedback around the op amp is resisitive (R F ), a pole will be created with R F, the source resistance and capacitance (R S, C S ), and the amplifier input capacitance (C IN 4pF). In low closed loop gain configurations and with R S and R F in the kilohm range, this pole can create excess phase shift and even oscillation on high speed amplifiers. Because the s phase margin is very high, this problem is minimal. However, a small capacitor (C F ) in parallel with R F eliminates this problem. With R S (C S + C IN ) = R F C F, the effect of the feedback pole is completely removed. R S + C F R F C S C IN OUTPUT AI4 PACKAGE DESCRIPTION U Dimension in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP.. ( ).4. ( ).1 ±. (. ±.17). (1.1) MAX.9. (.9.81) ( ). (1.1) TYP.4 ±. (1.14 ±.81). ±.1 (. ±.4).1 (.17) MIN.18 ±. (.47 ±.7). (.8) MIN ±.1 (. ±.4) N (.4.8).8.1 (..4)..9 ( ) S8 Package 8-Lead Plastic SOIC.4.1 (.11.4) (4.1.4) TYP (..48). (1.7) BSC.8.44 ( )..7 ( ) 1 4 SO8 9 Information furnished by is believed to be accurate and reliable. However, no responsibility is assumed for its use. makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7

8 NORTHEAST REGION One Oxford Valley E. Lincoln Hwy.,Suite Langhorne, PA 1947 Phone: () FAX: () 77-1 Lowell St., Suite B-8 Wilmington, MA 1887 Phone: (8) FAX: (8) 8-71 U.S. Area Sales Offices SOUTHEAST REGION 17 Dallas Parkway Suite 8 Dallas, TX 748 Phone: (14) 7-71 FAX: (14) -18 CENTRAL REGION Chesapeake Square 9 Mitchell Court, Suite A- Addison, IL 11 Phone: (78) -91 FAX: (78) -977 SOUTHWEST REGION 141 Ventura Blvd. Suite Woodland Hills, CA 914 Phone: (818) 7-8 FAX: (818) 7-17 NORTHWEST REGION 78 Sycamore Dr. Milpitas, CA 9 Phone: (8) 48- FAX: (8) 4-1 FRANCE Linear Technology S.A.R.L. Immeuble "Le Quartz" 8 Chemin de la Justice 99 Chatenay Malabry France Phone: FAX: GERMANY Linear Techonolgy GmbH Untere Hauptstr. 9 D-88 Eching Germany Phone: FAX: JAPAN Linear Technology KK F YZ Bldg Iidabashi, Chiyoda-Ku Tokyo, 1 Japan Phone: FAX: International Sales Offices KOREA Linear Technology Korea Branch Namsong Building, # Itaewon-Dong -199 Yongsan-Ku, Seoul Korea Phone: FAX: SINGAPORE Linear Technology Pte. Ltd. 11 Boon Keng Road #- Kallang Ind. Estates Singapore 1 Phone: -9- FAX: TAIWAN Rm. 1, No. 4, Sec. Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: FAX: UNITED KINGDOM Linear Technology (UK) Ltd. The Coliseum, Riverside Way Camberley, Surrey GU YL United Kingdom Phone: FAX: World Headquarters 1 McCarthy Blvd. Milpitas, CA Phone: (8) 4-19 FAX: (8) McCarthy Blvd., Milpitas, CA (8) 4-19 FAX: (8) 44-7 TELEX: LT/GP 94 1K PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1994

LT1208/LT1209 Dual and Quad 45MHz, 400V/µs Op Amps U S DESCRIPTIO

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