LT1208/LT1209 Dual and Quad 45MHz, 400V/µs Op Amps U S DESCRIPTIO

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LT18/LT19 Dual and Quad 45MHz, 4V/µs Op Amps FEATRES 45MHz Gain-Bandwidth 4V/µs Slew Rate nity-gain Stable 7V/mV DC Gain, R L = 5Ω 3mV Maximum Input Offset Voltage ±1V Minimum Output Swing into 5Ω

1 LT18/LT19 Dual and Quad 45MHz, 4V/µs Op Amps FEATRES 45MHz Gain-Bandwidth 4V/µs Slew Rate nity-gain Stable 7V/mV DC Gain, R L = 5Ω 3mV Maximum Input Offset Voltage ±1V Minimum Output Swing into 5Ω Wide Supply Range: ±.5V to ±15V 7mA Supply Current per Amplifier 9ns Settling Time to.1%, 1V Step Drives All Capacitive Loads APPLICATI O S Wideband Amplifiers Buffers Active Filters Video and RF Amplification Cable Drivers Data Acquisition Systems DESCRIPTIO The LT18/LT19 are dual and quad very high speed operational amplifiers with excellent DC performance. The LT18/LT19 feature reduced input offset voltage and higher DC gain than devices with comparable bandwidth and slew rate. Each amplifier is a single gain stage with outstanding settling characteristics. The fast settling time makes the circuit an ideal choice for data acquisition systems. Each output is capable of driving a 5Ω load to ±1V with ±15V supplies and a 15Ω load to ±3V on ±5V supplies. The amplifiers are also capable of driving large capacitive loads which make them useful in buffer or cable driver applications. The LT18/LT19 are members of a family of fast, high performance amplifiers that employ Linear Technology Corporation s advanced bipolar complementary processing. TYPICAL APPLICATI O 1MHz, 4th Order Butterworth Filter Inverter Pulse Response 99Ω 1. V IN 99Ω.67k pf LT18 47pF 1.. pf 47pF LT18 V OT 18/9 TA1 18/9 TA 1

2 LT18/LT19 ABSOLTE AXI RATI GS W W W Total Supply Voltage (V to V )... 36V Differential Input Voltage... ±6V Input Voltage... ±V S Output Short-Circuit Duration (Note 1)... Indefinite Operating Temperature Range LT18C/LT19C... 4 C to 85 C Maximum Junction Temperature Plastic Package C Storage Temperature Range C to 15 C Lead Temperature (Soldering, 1 sec)... 3 C PACKAGE/ORDER I FOR OT A 1 IN A IN A 3 V 4 A TOP VIEW B N8 PACKAGE 8-LEAD PLASTIC DIP T JMAX = 15 C, θ JA = 1 C/W 8 V 7 OT B 6 IN B 5 IN B W ATIO ORDER PART NMBER LT18CN8 CONTACT FACTORY FOR MILITARY/883B PARTS OT A 1 IN A IN A 3 V 4 A TOP VIEW S8 PACKAGE 8-LEAD PLASTIC SOIC T JMAX = 15 C, θ JA = 15 C/W B 8 V 7 OT B 6 IN B 5 IN B ORDER PART NMBER LT18CS8 S8 PART MARKING 18 TOP VIEW OT A IN A IN A V IN B A B D C 14 OT D 13 IN D 1 IN D 11 V 1 IN C IN B 6 9 IN C OT B 7 8 OT C N PACKAGE 14-LEAD PLASTIC DIP ORDER PART NMBER LT19CN TOP VIEW OT A 1 16 OT D IN A 15 IN D A D IN A 3 14 IN D V 4 13 V IN B 5 1 IN C B C IN B 6 11 IN C OT B 7 1 OT C NC 8 9 NC S PACKAGE 16-LEAD PLASTIC SOIC ORDER PART NMBER LT19CS T JMAX = 15 C, θ JA = 7 C/W T JMAX = 15 C, θ JA = 1 C/W ELECTRICAL CHARA CTERISTICS,, R L =, V CM = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage V S = ±5V (Note ).5 3. mv C to 7 C 4. mv (Note ) mv C to 7 C 6. mv Input V OS Drift 5 µv/ C I OS Input Offset Current V S = ±5V and 1 4 na C to 7 C 6 na I B Input Bias Current V S = ±5V and 4 8 µa C to 7 C 9 µa e n Input Noise Voltage f = Hz nv/ Hz i n Input Noise Current f = Hz 1.1 pa/ Hz

3 LT18/LT19 ELECTRICAL CHARA CTERISTICS,, R L =, V CM = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS R IN Input Resistance V CM = ±1V 4 MΩ Differential 5 kω C IN Input Capacitance pf CMRR Common-Mode Rejection Ratio, V CM = ±1V; V S = ±5V, db V CM = ±.5V, C to 7 C 83 db PSRR Power Supply Rejection Ratio V S = ±5V to ±15V db C to 7 C 75 db Input Voltage Range ±1 ±13 V V S = ±5V ±.5 ±3 V A VOL Large-Signal Voltage Gain, V OT = ±1V, R L = 5Ω V/mV C to 7 C.5 V/mV V S = ±5V, V OT = ±.5V, R L = 5Ω.5 7 V/mV C to 7 C. V/mV V S = ±5V, V OT = ±.5V, R L = 15Ω 3 V/mV V OT Output Swing, R L = 5Ω, C to 7 C ±V V S = ±5V, R L = 15Ω, C to 7 C ±V I OT Output Current, V OT = ±1V, C to 7 C 4 4 ma V S = ±5V, V OT = ± 3V, C to 7 C 4 ma SR Slew Rate, A VCL =, (Note 3) 5 4 V/µs C to 7 C V/µs V S = ±5V, A VCL =, (Note 3) 15 5 V/µs C to 7 C 13 V/µs Full Power Bandwidth 1V Peak, (Note 4) 6.4 MHz GBW Gain-Bandwidth, f = 1MHz 45 MHz V S = ±5V, f = 1MHz 34 MHz t r, t f Rise Time, Fall Time, A VCL = 1, 1% to 9%,.1V 5 ns V S = ± 5V, A VCL = 1, 1% to 9%,.1V 7 ns Overshoot V S = ± 15V, A VCL = 1,.1V 3 % V S = ± 5V, A VCL = 1,.1V % Propagation Delay V S = ± 15V, 5% V IN to 5%V OT 5 ns V S = ± 5V, 5% V IN to 5%V OT 7 ns t s Settling Time V S = ± 15V, 1V Step, V S = ±5V, 9 ns 5V Step,.1% Differential Gain f = 3.58MHz, R L = 15Ω 1.3 % f = 3.58MHz, R L =.9 % Differential Phase f = 3.58MHz, R L = 15Ω 1.8 Deg f = 3.58MHz, R L =.1 Deg R O Output Resistance A VCL = 1, f = 1MHz.5 Ω Crosstalk V OT = ±1V, R L = 5Ω 1 94 db I S Supply Current Each Amplifier, V S = ±5V and 7 9 ma C to 7 C 1.5 ma The denotes the specifications which apply over the full operating temperature range. Note 1: A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. Note : Input offset voltage is tested with automated test equipment and is exclusive of warm-up drift. Note 3: Slew rate is measured in a gain of. For ±15V supplies measure between ±1V on the output with ±6V on the input. For ±5V supplies measure between ±V on the output with ±1.75V on the input. Note 4: Full power bandwidth is calculated from the slew rate measurement: FPBW = SR/πV P. 3

4 LT18/LT19 TYPICAL PERFOR A W CE CHARA CTERISTICS MAGNITDE OF INPT VOLTAGE (V) Input Common-Mode Range vs Supply Current vs Supply Voltage Output Voltage Swing vs Supply Voltage and Temperature Supply Voltage V OS < 1mV V CM VCM SPPLY CRRENT (ma) C 5 C 55 C OTPT VOLTAGE SWING (V) R L = 5Ω V OS = 3mV V SW V SW SPPLY VOLTAGE (±V) 18/9 G SPPLY VOLTAGE (±V) 18/9 G SPPLY VOLTAGE (±V) 18/9 G3 OTPT VOLTAGE SWING (VP-P) Output Voltage Swing vs Input Bias Current vs Input Open-Loop Gain vs Resistive Load Common-Mode Voltage Resistive Load V OS = 3mV V S = ±5V INPT BIAS CRRENT (µa) I B IB I B = OPEN-LOOP GAIN (db) V S = ±5V 1 1 LOAD RESISTANCE (Ω) 18/9 G INPT COMMON-MODE VOLTAGE (V) 18/9 G LOAD RESISTANCE (Ω) 18/9 G6 INPT BIAS CRRENT (µa) Output Short-Circuit Current Input Bias Current vs Temperature vs Temperature Input Noise Spectral Density I B IB I B = TEMPERATRE ( C) 18/9 G7 OTPT SHORT-CIRCIT CRRENT (ma) SORCE SINK V S = ±5V TEMPERATRE ( C) 18/9 G8 INPT VOLTAGE NOISE (nv/ Hz) i n e n FREQENCY (Hz) A V = 11 R S = /9 G9 1 INPT CRRENT NOISE (pa/ Hz) 4

5 LT18/LT19 TYPICAL PERFOR A W CE CHARA CTERISTICS CROSSTALK (db) Power Supply Rejection Ratio Common-Mode Rejection Ratio Crosstalk vs Frequency vs Frequency vs Frequency V IN = dbm A V = 1 V S = ±5V R L = 5Ω R L = 1M 1M 1M FREQENCY (Hz) 18/9 G1 POWER SPPLY REJECTION RATIO (db) PSRR PSRR 1M 1M 1M FREQENCY (Hz) 18/9 G11 COMMON-MODE REJECTION RATIO (db) M 1M 1M FREQENCY (Hz) 18/9 G1 VOLTAGE GAIN (db) Voltage Gain and Phase vs Frequency Response vs Frequency Output Swing vs Settling Time Capacitive Load V S = ±5V V S = ±5V 1M 1M 1M FREQENCY (Hz) 18/9 B PHASE MARGIN (DEG) OTPT SWING (V) A V = 1 A V = 1 1mV SETTLING A V = 1 A V = SETTLING TIME (ns) 18/9 G14 VOLTAGE MAGNITDE (db) M A V = 1 C = 5pF C = 1pF 1M FREQENCY (Hz) C = 1pF C = 5pF C = 1M 18/9 G15 OTPT IMPEDANCE (Ω) Closed-Loop Output Impedance vs Frequency Gain-Bandwidth vs Temperature Slew Rate vs Temperature A V = 1 GAIN-BANDWIDTH (MHz) SLEW RATE (V/µs) A V = SR SR.1 1M 1M 1M FREQENCY (Hz) 18/9 G TEMPERATRE ( C) 18/9 G TEMPERATRE ( C) 18/9 G18 5

6 LT18/LT19 TYPICAL PERFOR A W CE CHARA CTERISTICS GAIN-BANDWIDTH (MHz) Gain-Bandwidth and Phase Margin Total Harmonic Distortion vs Supply Voltage Slew Rate vs Supply Voltage vs Frequency PHASE MARGIN GAIN BANDWIDTH SPPLY VOLTAGE (±V) 18/9 G PHASE MARGIN (DEG) SLEW RATE (V/µs) A V = 1 SR SR SPPLY VOLTAGE (±V) 18/9 G TOTAL HARMONIC DISTORTION (%).1 V OT = 3V RMS R L = 5Ω A V = 1 A V = FREQENCY (Hz) 18/9 G1 APPLICATI O S I FOR W ATIO Layout and Passive Components As with any high speed operational amplifier, care must be taken in board layout in order to obtain maximum performance. Key layout issues include: use of a ground plane, minimization of stray capacitance at the input pins, short lead lengths, RF-quality bypass capacitors located close to the device (typically.1µf to.1µf), and use of low ESR bypass capacitors for high drive current applications (typically 1µF to 1µF tantalum). Sockets should be avoided when maximum frequency performance is required, although low profile sockets can provide reasonable performance up to 5MHz. For more details see Design Note 5. The parallel combination of the feedback resistor and gain setting resistor on the inverting input combine with the input capacitance to form a pole which can cause peaking. If feedback resistors greater than 5k are used, a parallel capacitor of value Capacitive Loading The LT18/LT19 amplifiers are stable with capacitive loads. This is accomplished by sensing the load induced output pole and adding compensation at the amplifier gain node. As the capacitive load increases, both the bandwidth and phase margin decrease so there will be peaking in the frequency domain and in the transient response. The photo of the small-signal response with 1pF load shows 5% peaking. The large-signal response with a 1,pF load shows the output slew rate being limited by the short-circuit current. To reduce peaking with capacitive loads, insert a small decoupling resistor between the output and the load, and add a capacitor between the output and inverting input to provide an AC feedback path. Coaxial cable can be driven directly, but for best pulse fidelity the cable should be doubly terminated with a resistor in series with the output. C F R G C IN /R F should be used to cancel the input pole and optimize dynamic performance. For unity-gain applications where a large feedback resistor is used, C F should be greater than or equal to C IN. 6

LT18/LT19 APPLICATI O S I FOR W Small-Signal Capacitive Loading ATIO caused by a second pole beyond the unity-gain crossover.

Higher noise gain configurations exhibit less overshoot as seen in the inverting gain of one response.

Normally the noninverting response has a much faster rising edge due to the rapid change in input commonmode voltage which affects the tail current of the input differential pair.

7 LT18/LT19 APPLICATI O S I FOR W Small-Signal Capacitive Loading ATIO caused by a second pole beyond the unity-gain crossover. This is reflected in the 5 phase margin and shows up as overshoot in the unity-gain small-signal transient response. Higher noise gain configurations exhibit less overshoot as seen in the inverting gain of one response. A V = 1 C L = 1pF Large-Signal Capacitive Loading 18/9 AI1 The large-signal response in both inverting and noninverting gain show symmetrical slewing characteristics. Normally the noninverting response has a much faster rising edge due to the rapid change in input commonmode voltage which affects the tail current of the input differential pair. Slew enhancement circuitry has been added to the LT18/LT19 so that the falling edge slew rate is balanced. Small-Signal Transient Response A V = 1 C L = 1,pF 18/9 AI Input Considerations Resistors in series with the inputs are recommended for the LT18/LT19 in applications where the differential input voltage exceeds ±6V continuously or on a transient basis. An example would be in noninverting configurations with high input slew rates or when driving heavy capacitive loads. The use of balanced source resistance at each input is recommended for applications where DC accuracy must be maximized. A V = 1 Small-Signal Transient Response 18/9 AI3 Transient Response The LT18/LT19 gain-bandwidth is 45MHz when measured at Hz. The actual frequency response in unitygain is considerably higher than 45MHz due to peaking A V = 1 18/9 AI4 7

8 LT18/LT19 APPLICATI A V = 1 O S I FOR W Large-Signal Transient Response Large-Signal Transient Response ATIO 18/9 AI4 Power Dissipation The LT18/LT19 combine high speed and large output current drive in small packages. Because of the wide supply voltage range, it is possible to exceed the maximum junction temperature under certain conditions. Maximum junction temperature (T J ) is calculated from the ambient temperature (T A ) and power dissipation (P D ) as follows: LT18CN8: LT18CS8: LT19CN: LT19CS: T J = T A (P D 1 C/W) T J = T A (P D 15 C/W) T J = T A (P D 7 C/W) T J = T A (P D 1 C/W) Maximum power dissipation occurs at the maximum supply current and when the output voltage is at of either supply voltage (or the maximum swing if less than supply voltage). For each amplifier P DMAX is as follows: P DMAX = (V V )(I SMAX ) (.5V ) R L Example: LT18 in S8 at 7 C, V S = ±1V, R L = 5Ω A V = 1 18/9 AI6 P DMAX = (V)(1.5mA) (5V) 5Ω = 6mW T J = 7 C ( 6mW)(15 C/W) = 148 C Low Voltage Operation The LT18/LT19 are functional at room temperature with only 3V of total supply voltage. nder this condition, however, the undistorted output swing is only.8v P-P. A more realistic condition is operation at ±.5V supplies (or 5V and ground). nder these conditions, at room temperature, the typical input common-mode range is 1.9V to 1.3V (for a V OS change of 1mV), and a 5MHz, V P-P sine wave can be faithfully reproduced. With 5V total supply voltage the gain-bandwidth is reduced to 6MHz and the slew rate is reduced to 135V/µs. DAC Current-to-Voltage Converter The wide bandwidth, high slew rate and fast settling time of the LT18/LT19 make them well-suited for currentto-voltage conversion after current output D/A converters. A typical application with a DAC-8 type converter (fullscale output of ma) uses a 5k feedback resistor. A 7pF compensation capacitor across the feedback resistor is used to null the pole at the inverting input caused by the DAC output capacitance. The combination of the LT18/ LT19 and DAC settles to less than 4mV (1LSB) in 14ns for a 1V step. 8

9 LT18/LT19 TYPICAL APPLICATI O S DAC Current-to-Voltage Converter Cable Driving 7pF DAC-8 TYPE.1µF 5k 5k LT18 V OT 1 LSB SETTLING = 14ns V IN R LT18 R1 R3 75Ω 75Ω CABLE R4 75Ω V OT 18/9 TA6 18/9 TA4 Instrumentation Amplifier R5 Ω R4 R1 R V IN LT18 ( ) R3 R4 A V = 1 1 R R3 R R3 = 1 R3 R1 R4 R5 TRIM R5 FOR GAIN TRIM R1 FOR COMMON-MODE REJECTION BW = 43kHz LT18 18/9 TA3 V OT Full-Wave Rectifier 1N4148 V IN LT18 1N4148 5Ω LT18 V OT 18/9 TA5 9

10 LT18/LT19 SI W PLII FED SCHE W ATIC V BIAS 1 IN IN BIAS OT V 18/9 SS PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted..3.3 ( ) ( ) N8 Package 8-Lead Plastic DIP.13 ±.5 (3.3 ±.17).4 (1.16) MAX (.9.381) ( ).65 (1.651) TYP.45 ±.15 (1.143 ±.381).1 ±.1 (.54 ±.54).15 (3.175) MIN.18 ±.3 (.457 ±.76). (.58) MIN ±.1 (6.35 ±.54) N (.54.58).8.1 (.3.54) ( ) S8 Package 8-Lead Plastic SOIC.4.1 (.11.54) ( ) TYP ( ).5 (1.7) BSC.8.44 ( ) ( ) SO8 39 1

11 LT18/LT19 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 14-Lead Plastic DIP.77 (19.558) MAX ±.1 (6.64 ±.54) ( ).13 ±.5 (3.3 ±.17) ( ).9.15 (.9.381).15 (.38) MIN.65 (1.651) TYP ( ).15 (3.175) MIN.75 ±.15 (1.95 ±.381).1 ±.1 (.54 ±.54).18 ±.3 (.457 ±.76) N14 39 S Package 16-Lead Plastic SOIC * ( ) ( ) * ( ) (.54.58).8.1 (.3.54) ( ) (.11.54) 8 TYP ( ).5 (1.7) TYP SO16 39 *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.6 INCH (.15mm). Information furnished by is believed to be accurate and reliable. However, no responsibility is assumed for its use. makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11

12 LT18/LT19 NORTHEAST REGION One Oxford Valley 3 E. Lincoln Hwy.,Suite 36 Langhorne, PA 1947 Phone: (15) FAX: (15) Lowell St., Suite B-8 Wilmington, MA 1887 Phone: (58) FAX: (58) S. Area Sales Offices SOTHEAST REGION 176 Dallas Parkway Suite 8 Dallas, TX 7548 Phone: (14) FAX: (14) CENTRAL REGION Chesapeake Square 9 Mitchell Court, Suite A-5 Addison, IL 611 Phone: (78) FAX: (78) SOTHWEST REGION 141 Ventura Blvd. Suite 6 Woodland Hills, CA Phone: (818) FAX: (818) NORTHWEST REGION 78 Sycamore Dr. Milpitas, CA 9535 Phone: (48) 48-5 FAX: (48) FRANCE Linear Technology S.A.R.L. Immeuble "Le Quartz" 58 Chemin de la Justice 99 Chatenay Malabry France Phone: FAX: GERMANY Linear Techonolgy GMBH ntere Hauptstr. 9 D-857 Eching Germany Phone: FAX: JAPAN Linear Technology KK 5F YZ Bldg. Iidabashi, Chiyoda-Ku Tokyo, 1 Japan Phone: FAX: International Sales Offices KOREA Linear Technology Korea Branch Namsong Building, #55 Itaewon-Dong Yongsan-Ku, Seoul Korea Phone: FAX: SINGAPORE Linear Technology Pte. Ltd. 11 Boon Keng Road #-15 Kallang Ind. Estates Singapore 133 Phone: FAX: TAIWAN Rm. 81, No. 46, Sec. Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: FAX: NITED KINGDOM Linear Technology (K) Ltd. The Coliseum, Riverside Way Camberley, Surrey G15 3YL nited Kingdom Phone: FAX: World Headquarters 163 McCarthy Blvd. Milpitas, CA Phone: (48) FAX: (48) /1/93 1 LT/GP 493 1K REV 163 McCarthy Blvd., Milpitas, CA (48) FAX: (48) TELEX: LINEAR TECHNOLOGY CORPORATION 1993

DESCRIPTION FEATURES APPLICATIONS. LT1457 Dual, Precision JFET Input Op Amp TYPICAL PERFORMANCE CHARACTERISTICS

DESCRIPTION FEATURES APPLICATIONS. LT1457 Dual, Precision JFET Input Op Amp TYPICAL PERFORMANCE CHARACTERISTICS Dual, Precision JFET Input Op Amp FEATURES Handles 1,pF Capacitive Load 4µV Max Offset Voltage 1µV Max Offset Voltage in S8 Package pa Bias Current at 7 C 1nV/ Hz Voltage Noise 4V/µs Slew Rate 4µV/ C Drift