APPLICATIO S TYPICAL APPLICATIO. LTC2051/LTC2052 Dual/Quad Zero-Drift Operational Amplifiers FEATURES DESCRIPTIO

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1 LTC/LTC Dual/Quad Zero-Drift Operational Amplifiers FEATRES Maximum Offset Voltage of μv Maximum Offset Voltage Drift of nv/ C Small Footprint, Low Profile MS/GN Packages Single Supply Operation:.V to ±.V Noise:.μV P-P (.Hz to Hz Typ) Voltage Gain: db (Typ) PSRR: db (Typ) CMRR: db (Typ) Supply Current:.mA (Typ) per Amplifier Extended Common Mode Input Range Output Swings Rail-to-Rail Operating Temperature Range C to C Available in mm mm.mm DFN Package APPLICATIO S Thermocouple Amplifiers Electronic Scales Medical Instrumentation Strain Gauge Amplifiers High Resolution Data Acquisition DC Accurate RC Active Filters Low Side Current Sense DESCRIPTIO The LTC /LTC are dual/quad zero-drift operational amplifiers available in the MS and SO-/GN and S packages. For space limited applications, the LTC is available in a mm mm.mm dual fine pitch leadless package (DFN). They operate from a single.v supply and support ±V applications. The current consumption is μa per op amp. The LTC/LTC, despite their miniature size, feature uncompromising DC performance. The typical input offset voltage and offset drift are.μv and nv/ C. The almost zero DC offset and drift are supported with a power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) of more than db. The input common mode voltage ranges from the negative supply up to typically V from the positive supply. The LTC/LTC also have an enhanced output stage capable of driving loads as low as kω to both supply rails. The open-loop gain is typically db. The LTC/ LTC also feature a.μv P-P DC to Hz noise and a MHz gain-bandwidth product., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ICAL APPLICATIO High Performance Low Cost Instrumentation Amplifier R k.% R Ω.% V R Ω.% R k.% / LTCHV / V IN LTCHV VIN AV = V TA μv Input Referred Noise.Hz to Hz TIME (SEC) TA fd

2 LTC/LTC ABSOLTE AXI RATI GS W W W (Note ) Total Supply Voltage (V to V ) LTC/LTC... V LTCHV/LTCHV... V Input Voltage (Note )... (V.V) to (V.V) Output Short-Circuit Duration... Indefinite Operating Temperature Range... C to C Specified Temperature Range (Note ) C to C Storage Temperature Range... C to C DD Package... C to C Lead Temperature (Soldering, sec)... C W PACKAGE/ORDER I FOR ATIO TOP VIEW OT A IN A IN A V 9 DD PACKAGE -LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = C/W EXPOSED PAD (PIN 9) IS CONNECTED TO V (PIN ) V OT B IN B IN B OT A IN A IN A V TOP VIEW MS PACKAGE -LEAD PLASTIC MSOP V OT B IN B IN B T JMAX = C, θ JA = C/W OT A IN A IN A V SHDN A TOP VIEW 9 MS PACKAGE -LEAD PLASTIC MSOP T JMAX = C, θ JA = C/W V OT B IN B IN B SHDN B ORDER PART NMBER* LTCCDD LTCIDD LTCHVCDD LTCHVIDD OT A IN A IN A V DD PART MARKING LAAN LAEL TOP VIEW S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/W V OT B IN B IN B Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: ORDER PART NMBER LTCCMS LTCIMS LTCHVCMS LTCHVIMS LTCHMS LTCHVHMS Consult LTC Marketing for parts specified with wider operating temperature ranges. MS PART MARKING LTMN LTMP LTPJ LTPK LTVF LTVH ORDER PART NMBER LTCCS LTCIS LTCHVCS LTCHVIS LTCHS LTCHVHS ORDER PART NMBER LTCCMS LTCIMS LTCHVCMS LTCHVIMS MS PART MARKING LTMQ LTMR LTRB LTRC S PART MARKING I HV HVI H HVH fd

3 LTC/LTC W PACKAGE/ORDER I FOR ATIO OT A IN A IN A V IN B IN B OT B NC TOP VIEW GN PACKAGE -LEAD PLASTIC SSOP OT D IN D IN D V IN C IN C OT C 9 NC T JMAX = C, θ JA = C/W ORDER PART NMBER LTCCGN LTCIGN LTCHVCGN LTCHVIGN LTCHGN LTCHVHGN GN PART MARKING I HV HVI H HVH OT A IN A IN A V IN B IN B OT B TOP VIEW S PACKAGE -LEAD PLASTIC SO OT D IN D IN D V IN C 9 IN C OT C T JMAX = C, θ JA = C/W ORDER PART NMBER LTCCS LTCIS LTCHVCS LTCHVIS LTCHS LTCHVHS AVAILABLE OPTIO S PART NMBER AMPS/PACKAGE SPECIFIED TEMP RANGE SPECIFIED VOLTAGE PACKAGE LTCCDD C to C V, V DD LTCCS C to C V, V SO- LTCCMS C to C V, V -Lead MSOP LTCCMS C to C V, V -Lead MSOP LTCHVCDD C to C V, V, ±V DD LTCHVCS C to C V, V, ±V SO- LTCHVCMS C to C V, V, ±V -Lead MSOP LTCHVCMS C to C V, V, ±V -Lead MSOP LTCIDD C to C V, V DD LTCIS C to C V, V SO- LTCIMS C to C V, V -Lead MSOP LTCIMS C to C V, V -Lead MSOP LTCHVIDD C to C V, V, ±V DD LTCHVIS C to C V, V, ±V SO- LTCHVIMS C to C V, V, ±V -Lead MSOP LTCHVIMS C to C V, V, ±V -Lead MSOP LTCHS C to C V, V SO- LTCHMS C to C V, V -Lead MSOP LTCHVHS C to C V, V, ±V SO- LTCHVHMS C to C V, V, ±V -Lead MSOP LTCCS C to C V, V -Lead SO LTCCGN C to C V, V -Lead SSOP LTCHVCS C to C V, V, ±V -Lead SO LTCHVCGN C to C V, V, ±V -Lead SSOP fd

4 LTC/LTC AVAILABLE OPTIO S PART NMBER AMPS/PACKAGE SPECIFIED TEMP RANGE SPECIFIED VOLTAGE PACKAGE LTCIS C to C V, V -Lead SO LTCIGN C to C V, V -Lead SSOP LTCHVIS C to C V, V, ±V -Lead SO LTCHVIGN C to C V, V, ±V -Lead SSOP LTCHS C to C V, V -Lead SO LTCHGN C to C V, V -Lead SSOP LTCHVHS C to C V, V, ±V -Lead SO LTCHVHGN C to C V, V, ±V -Lead SSOP ELECTRICAL CHARACTERISTICS (LTC/LTC, LTCHV/LTCHV) The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V S = V, V unless otherwise noted. (Note ) LTCC/LTCC LTCI/LTCI LTCH/LTCH PARAMETER CONDITIONS MIN MAX MIN MAX NITS Input Offset Voltage (Note ) ±. ± ±. ± μv Average Input Offset Drift (Note ). ±.. ±. μv/ C Long-Term Offset Drift nv/ mo Input Bias Current (Note ) V S = V ± ± ± ± pa V S = V ± ± pa V S = V ± ± ± ± pa V S = V ± ± pa Input Offset Current (Note ) V S = V ± ± pa V S = V ± ± pa V S = V ± ± pa V S = V ± ± pa Input Noise Voltage R S = Ω, DC to Hz.. μv P-P Common Mode Rejection Ratio V CM = GND to V., db V S = V db V CM = GND to V., db V S = V db Power Supply Rejection Ratio db db Large-Signal Voltage Gain R L = k, V S = V db db R L = k, V S = V db db Output Voltage Swing High R L = k to GND V. V. V. V. V R L = k to GND V. V. V. V. V Output Voltage Swing Low R L = k to GND mv R L = k to GND mv Slew Rate V/μs Gain Bandwidth Product MHz Supply Current (Per Amplifier) No Load, V S = V, V SHDN = V IH.... ma No Load, V S = V, V SHDN = V IH.... ma Supply Current, Shutdown V SHDN = V IL, V S = V μa V SHDN = V IL, V S = V μa fd

5 ELECTRICAL CHARACTERISTICS LTC/LTC (LTC/LTC, LTCHV/LTCHV) The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V S = V, V unless otherwise noted. (Note ) LTCC/LTCC LTCI/LTCI LTCH/LTCH PARAMETER CONDITIONS MIN MAX MIN MAX NITS Shutdown Pin Input Low Voltage (V IL ) V. V. V Shutdown Pin Input High Voltage (V IH ) V. V. V Shutdown Pin Input Current V SHDN = V IL, V S = V μa V SHDN = V IL, V S = V μa Internal Sampling Frequency.. khz (LTCHV/LTCHV) The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V S = ±V unless otherwise noted. (Note ) LTCC/LTCC LTCI/LTCI LTCH/LTCH PARAMETER CONDITIONS MIN MAX MIN MAX NITS Input Offset Voltage (Note ) ± ± ± ± μv Average Input Offset Drift (Note ). ±.. ±. μv/ C Long-Term Offset Drift nv/ mo Input Bias Current (Note ) ±9 ± ±9 ± pa ± ± pa Input Offset Current (Note ) ± ± pa ± ± pa Input Noise Voltage R S = Ω, DC to Hz.. μv P-P Common Mode Rejection Ratio V CM = V to V. db db Power Supply Rejection Ratio db db Large-Signal Voltage Gain R L = k db db Maximum Output Voltage Swing R L = k to GND ±. ±.9 ±. ±.9 V R L = k to GND ±.9 ±.9 ±. ±.9 V Slew Rate V/μs Gain Bandwidth Product MHz Supply Current (Per Amplifier) No Load, V SHDN = V IH.. ma Supply Current, Shutdown V SHDN = V IL μa Shutdown Pin Input Low Voltage (V IL ) V. V. V Shutdown Pin Input High Voltage (V IH ) V. V. V Shutdown Pin Input Current V SHDN = V IL μa Internal Sampling Frequency.. khz Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : These parameters are guaranteed by design. Thermocouple effects preclude measurements of these voltage levels during automated testing. Note : All versions of the LTC/LTC are designed, characterized and expected to meet the extended temperature limits of C and C. The LTCC/LTCC/LTCHVC/LTCHVC are guaranteed to meet the temperature limits of C and C. The LTCI/LTCI/ LTCHVI/LTCHVI are guaranteed to meet temperature limits of C and C. The LTCH/LTCHVH and LTCH/LTCHVH are guaranteed to meet the temperature limits of C and C. Note : The bias current measurement accuracy depends on the proximity of the negative supply bypass capacitors to the device under test. Because of this, only the bias current of channel B (LTC) and channels A and B (LTC) are % tested to the data sheet specifications. The bias currents of the remaining channels are % tested to relaxed limits, however, their values are guaranteed by design to meet the data sheet limits. Note : This parameter is guaranteed to meet specified performance through design and characterization. It has not been tested. Note : The θ JA specified for the DD package is with minimal PCB heat spreading metal. sing expanded metal area on all layers of a board reduces this value. fd

6 LTC/LTC ICAL PERFOR A CE CHARACTERISTICS W CMRR (db) Common Mode Rejection Ratio vs Frequency V S = V OR ±V V CM =.V P-P CMRR (db) DC CMRR vs Common Mode Input Range V S = V V S = V V S = V PSRR (db) PSRR vs Frequency PSRR PSRR k k k FREQENCY (Hz) G V CM (V) G k k k M FREQENCY (Hz) G Output Voltage Swing vs Load Resistance R L TO GND V S = V Output Swing vs Output Current V S = V Output Swing vs Load Resistance ±V R L TO GND OTPT SWING (V) V S = V OTPT VOLTAGE (V) V S = V OTPT VOLTAGE (V) LOAD RESISTANCE (kω).. OTPT CRRENT (ma) LOAD RESISTANCE (kω) G G G OTPT SWING (V). Output Swing vs Output Current, ±V Supply R L TO GND. OTPT CRRENT (ma) G GAIN (db) Gain/Phase vs Frequency PHASE GAIN V S = V OR ±V C L = pf R L = k k k k M M FREQENCY (Hz) G PHASE (DEG) BIAS CRRENT (pa) k k Bias Current vs Temperature V S = ±V V S = V V S = V TEMPERATRE ( C) G9 fd

LTC/LTC ICAL PERFOR A CE CHARACTERISTICS W Input Bias Current vs Input Common Mode Voltage Transient Response Input Overload Recovery INPT BIAS CRRENT (pa) V S = ±V V S = V V S

. A V = R L = k C L = pf V S = V μs/div G G Sampling Frequency vs Supply Voltage Sampling Frequency vs Temperature SAMPLING FREQENCY (khz) 9 SAMPLING FREQENCY (khz) 9 V S = ±V V

7 LTC/LTC ICAL PERFOR A CE CHARACTERISTICS W Input Bias Current vs Input Common Mode Voltage Transient Response Input Overload Recovery INPT BIAS CRRENT (pa) V S = ±V V S = V V S = V INPT COMMON MODE VOLTAGE (V) V/DIV A V = R L = k C L = pf V S = ±V μs/div G INPT (V) OTPT (V).. A V = R L = k C L = pf V S = V μs/div G G Sampling Frequency vs Supply Voltage Sampling Frequency vs Temperature SAMPLING FREQENCY (khz) 9 SAMPLING FREQENCY (khz) 9 V S = ±V V S = V 9 SPPLY VOLTAGE (V) TEMPERATRE ( C) G G.. Supply Current (Per Amplifier) vs Supply Voltage.. Supply Current (Per Amplifier) vs Temperature V S = ±V SPPLY CRRENT (ma)... SPPLY CRRENT (ma)... V S = V V S = V SPPLY VOLTAGE (V) TEMPERATRE ( C) G G fd

8 LTC/LTC APPLICATIO S I FOR ATIO Shutdown W The LTC includes a shutdown pin in the -lead MSOP. When this active low pin is high or allowed to float, the device operates normally. When the shutdown pin is pulled low, the device enters shutdown mode; supply current drops to μa, all clocking stops and the output assumes a high impedance state. Clock Feedthrough, Input Bias Current The LTC/LTC use autozeroing circuitry to achieve an almost zero DC offset over temperature, common mode voltage and power supply voltage. The frequency of the clock used for autozeroing is typically.khz. The term clock feedthrough is broadly used to indicate visibility of this clock frequency in the op amp output spectrum. There are typically two types of clock feedthrough in autozeroed op amps like the LTC/LTC. The first form of clock feedthough is caused by the settling of the internal sampling capacitor and is input referred; that is, it is multiplied by the closed-loop gain of the op amp. This form of clock feedthrough is independent of the magnitude of the input source resistance or the magnitude of the gain setting resistors. The LTC/LTC have a residue clock feedthrough of less than μv RMS input referred at.khz. The second form of clock feedthrough is caused by the small amount of charge injection occurring during the sampling and holding of the op amps input offset voltage. The current spikes are multiplied by the impedance seen at the input terminals of the op amp, appearing at the output multiplied by the closed-loop gain of the op amp. To reduce this form of clock feedthrough, use smaller valued gain setting resistors and minimize the source resistance at the input. If the resistance seen at the inputs is less than k, this form of clock feedthrough is less than μv RMS input referred at.khz, or less than the amount of residue clock feedthrough from the first form previously described. Placing a capacitor across the feedback resistor reduces either form of clock feedthrough by limiting the bandwidth of the closed-loop gain. Input bias current is defined as the DC current into the input pins of the op amp. The same current spikes that cause the second form of clock feedthrough previously described, when averaged, dominate the DC input bias current of the op amp below C. At temperatures above C, the leakage of the ESD protection diodes on the inputs increase the input bias currents of both inputs in the positive direction, while the current caused by the charge injection stays relatively constant. At elevated temperatures (above C) the leakage current begins to dominate and both the negative and positive pin s input bias currents are in the positive direction (into the pins). Input Pins, ESD Sensitivity ESD voltages above V on the input pins of the op amp will cause the input bias currents to increase (more DC current into the pins). At these voltages, it is possible to damage the device to a point where the input bias current exceeds the maximums specified in this data sheet. ICAL APPLICATIO The dual chopper op amp buffers the inputs of A and corrects its offset voltage and offset voltage drift. With the RC values shown, the power-up warm-up time is typically seconds. The step response of the composite amplifier does not present settling tails. The LT should be used when extremely low noise, V OS and V OS drift are needed and the input source resistance is low. (For instance a Ω strain gauge bridge.) The LT or equivalent should be used when low bias current (pa) is also required in conjunction with DC to Hz low noise, low V OS and V OS drift. The measured typical input offset voltages are less than μv. fd

9 LTC/LTC ICAL APPLICATIO Obtaining ltralow V OS Drift and Low Noise / LTC R V R R / LTC C R C R F OT A OT A R R R R R C C e IN (DC Hz) e IN (DC Hz) LT.9k.k k k k.μf.μf.μv P-P.μV P-P LT Ω Ω k k k.μf.μf.μv P-P.μV P-P PACKAGE DESCRIPTIO DD Package -Lead Plastic DFN (mm mm) (Reference LTC DWG # --9) R =.. ±.. ±. PIN TOP MARK (NOTE ). REF. ±. ( SIDES). ±.... ±. ( SIDES). ±.. ±. ( SIDES) BOTTOM VIEW EXPOSED PAD NOTE:. DRAWING TO BE MADE A JEDEC PACKAGE OTLINE M-9 VARIATION OF (WEED-). DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON TOP AND BOTTOM OF PACKAGE.. ±.. ±.. ±. ( SIDES) PACKAGE OTLINE. ±... ±. ( SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS (DD) DFN fd 9

10 LTC/LTC PACKAGE DESCRIPTIO MS Package -Lead Plastic MSOP (Reference LTC DWG # --). (.) DETAIL A GAGE PLANE. (.) DETAIL A NOTE:. DIMENSIONS IN MILLIMETER/(INCH). DRAWING NOT TO SCALE. ±. (. ±.) SEATING PLANE. (.) MAX.. (.9.). (.). (.) REF. DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED.mm (.") PER SIDE. DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED.mm (.") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.mm (.") MAX. ±. (. ±.). ±. (. ±.) (NOTE ).9 ±. (.9 ±.). (.) REF. ±. (. ±.) (NOTE ). (.) MIN. ±. (. ±.).9 ±. (. ±.).. (..). (.) RECOMMENDED SOLDER PAD LAYOT MSOP (MS) MS Package -Lead Plastic MSOP (Reference LTC DWG # --). ±. (. ±.) (NOTE ) 9.9 ±. (.9 ±.) REF.9 ±. (. ±.) GAGE PLANE. (.). (.) DETAIL A DETAIL A NOTE:. DIMENSIONS IN MILLIMETER/(INCH). DRAWING NOT TO SCALE. ±. (. ±.) SEATING PLANE.9 ±. (.9 ±.). (.) MAX.. (..). (.9). DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED.mm (.") PER SIDE. DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED.mm (.") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.mm (.") MAX. ±. (. ±.) (NOTE ). (.) REF. ±. (. ±.). (.) MIN. ±. (. ±.).. (..). (.9) RECOMMENDED SOLDER PAD LAYOT MSOP (MS) fd

11 LTC/LTC PACKAGE DESCRIPTIO S Package -Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # --).. (..).. (..)..9 (..)....9 (..) (..) NOTE: INCHES. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED." (.mm).. (..). (.).. (.9.9).9.9 (..) NOTE GN Package -Lead Plastic SSOP (Narrow. Inch) (Reference LTC DWG # --).. (..9) NOTE. MIN. ±.. SO RECOMMENDED SOLDER PAD LAYOT. ±.. ±...9 (..9). ±. (. ±.).. (..)..9 (..9).9.9* (..9) 9.9 (.9) REF. ±... (..) NOTE:. CONTROLLING DIMENSION: INCHES INCHES. DIMENSIONS ARE IN (MILLIMETERS).. (..). (.). DRAWING NOT TO SCALE * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.9. (..9)..** (..9). MIN... ±.. RECOMMENDED SOLDER PAD LAYOT GN (SSOP) S Package -Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # --).. ±... (..) NOTE N 9. MIN N/. ±... (.9.9) N N/.. (..9) NOTE. ±. RECOMMENDED SOLDER PAD LAYOT.. (..).. (..)..9 (..).. (..)....9 (..) (..) NOTE: INCHES. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED." (.mm). (.) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. S fd

12 LTC/LTC ICAL APPLICATIO Paralleling Amplifiers to Improve Noise R R / LTC R R R V R V IN R / LTC / LTC R 9 R / LTC R V.μF.μF V OT V OT R NOISE OF EACH PARALLEL OP AMP = ; INPT DC Hz NOISE.μV V P-P = IN R F RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC/LTC Precision Zero-Drift Op Amp Dual/Quad LTC ±V Zero-Drift Op Amp Dual High Voltage Operation ±V LTC Rail-to-Rail Input and Output Zero-Drift Op Amp Single Zero-Drift Op Amp with Rail-to-Rail Input and Output and Shutdown LTC Zero-Drift Op Amp in SOT- Single Supply Operation.V to ±V, Shutdown LTC Zero-Drift Precision Instrumentation Amp MS, db CMRR, Two External Resistors Set Gain LTC Rail-to-Rail Input and Output Instrumentation Amp Low Cost, MS, Two External Resistors Set Gain Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - fd LT REV D PRINTED IN SA LINEAR TECHNOLOGY CORPORATION

FEATURES DESCRIPTIO APPLICATIO S. LTC2050/LTC2050HV Zero-Drift Operational Amplifiers in SOT-23 TYPICAL APPLICATION

FEATURES DESCRIPTIO APPLICATIO S. LTC2050/LTC2050HV Zero-Drift Operational Amplifiers in SOT-23 TYPICAL APPLICATION FEATRES Maximum Offset Voltage of µv Maximum Offset Voltage Drift of nv/ C Noise:.µV P-P (.Hz to Hz Typ) Voltage Gain: db (Typ) PSRR: db (Typ) CMRR: db (Typ) Supply Current:.8mA (Typ) Supply Operation:.7V