LTC6081/LTC6082 Precision Dual/Quad CMOS Rail-to-Rail Input/ Output Amplifi ers DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

Size: px

Start display at page:

Download "LTC6081/LTC6082 Precision Dual/Quad CMOS Rail-to-Rail Input/ Output Amplifi ers DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION"

Millicent Ray
5 years ago
Views:

1 FEATURES Maximum Offset Voltage: 7μV (2 C) Maximum Offset Drift:.8μV/ C Maximum Input Bias: pa (2 C) 4pA (T A 8 C) Open Loop Voltage Gain: 2dB Typ Gain Bandwidth Product: 3.6MHz CMRR: db Min PSRR: 98dB Min.Hz to Hz Noise:.3μV P-P Supply Current: 33μA Rail-to-Rail Inputs and Outputs Unity Gain Stable 2.7V to.v Operation Voltage Dual LTC68 in 8-Lead MSOP and -Lead DFN Packages; Quad LTC682 in 6-Lead SSOP and DFN Packages APPLICATIONS Photodiode Amplifi er Strain Gauge High Impedance Sensor Amplifi er Microvolt Accuracy Threshold Detection Instrumentation Amplifi ers Thermocouple Amplifi ers TYPICAL APPLICATION Shock Sensor Amplifi er (Accelerometer) DESCRIPTION LTC68/LTC682 Precision Dual/Quad CMOS Rail-to-Rail Input/ Output Amplifi ers The LTC 68/LTC682 are dual/quad low offset, low drift, low noise CMOS operational amplifiers with rail-to-rail input/output swing. The 7μV maximum offset, pa input bias current, 2dB open loop gain and.3μv P-P.Hz to Hz noise make it perfect for precision signal conditioning. The LTC68/ LTC682 features db CMRR and 98dB PSRR. Each amplifier consumes only 33μA of current on a 3V supply. The -lead DFN has an independent shutdown function that reduces each amplifier s supply current to μa. LTC68/LTC682 is specified for power supply voltages of 3V and V from 4 C to 2 C. The dual LTC68 is available in 8-lead MSOP and -lead DFN packages. The quad LTC682 is available in 6-lead SSOP and DFN packages. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. V OS Drift Histogram MURATA PKGS-LD 77pF SENSOR G 8.2pF 2M 3.9pF M 2M 3.9pF k V V 47pF.μF /2 LTC68.μF M V OUT = 9mV/g BW ~ 2.2kHz 682 TA NUMBER OF AMPLIFIERS (OUT OF ) LTC68MS8 T A = 4 C TO 2 C V CM =.V.2.. V OSDRIFT (μv/ C) TAb 682fc

2 LTC68/LTC682 ABSOLUTE MAXIMUM RATINGS (Note ) Total Supply Voltage (V to V )...6V Input Voltage... V to V Output Short Circuit Duration (Note 2)... Indefinite Operating Temperature Range (Note 3) LTC68C, LTC682C... 4 C to 8 C LTC68I, LTC682I... 4 C to 8 C LTC68H, LTC682H... 4 C to 2 C (H Temperature Range Not Available in DFN Package) Specified Temperature Range (Note 4) LTC68C, LTC682C... C to 7 C LTC68I, LTC682I... 4 C to 8 C LTC68H, LTC682H... 4 C to 2 C Junction Temperature DFN Packages... 2 C All Other Packages... C Storage Temperature Range DFN Packages... 6 C to 2 C All Other Packages... 6 C to C Lead Temperature (Soldering, Sec)... 3 C PIN CONFIGURATION TOP VIEW OUTA INA INA V SHDN_A V 2 A 9 OUTB 3 B 8 INB INB SHDN_B DD PACKAGE -LEAD (3mm 3mm) PLASTIC DFN T JMAX = 2 C, θ JA = 43 C/W UNDERSIDE METAL CONNECTED TO V OUTA INA 2 INA 3 V 4 TOP VIEW A 8 V 7 OUTB 6 INB INB MS8 PACKAGE 8-LEAD PLASTIC MSOP T JMAX = C, θ JA = 2 C/W B TOP VIEW TOP VIEW OUTA INA INA V INB INB OUTB NC A B D C OUTD IND IND V INC INC OUTC NC OUTA INA INA V INB INB OUTB NC A B D C OUTD IND IND V INC INC OUTC NC DHC PACKAGE 6-LEAD (mm 3mm) PLASTIC DFN T JMAX = 2 C, θ JA = 43 C/W UNDERSIDE METAL CONNECTED TO V GN PACKAGE 6-LEAD PLASTIC SSOP T JMAX = C, θ JA = C/W 2 682fc

3 LTC68/LTC682 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC68CDD#PBF LTC68CDD#TRPBF LCJP -Lead (3mm 3mm) Plastic DFN C to 7 C LTC68IDD#PBF LTC68IDD#TRPBF LCJP -Lead (3mm 3mm) Plastic DFN 4 C to 8 C LTC68CMS8#PBF LTC68CMS8#TRPBF LTCJN 8-Lead Plastic MSOP C to 7 C LTC68IMS8#PBF LTC68IMS8#TRPBF LTCJN 8-Lead Plastic MSOP 4 C to 8 C LTC68HMS8#PBF LTC68HMS8#TRPBF LTCJN 8-Lead Plastic MSOP 4 C to 2 C LTC682CDHC#PBF LTC682CDHC#TRPBF Lead (mm 3mm) Plastic DFN C to 7 C LTC682IDHC#PBF LTC682IDHC#TRPBF Lead (mm 3mm) Plastic DFN 4 C to 8 C LTC682CGN#PBF LTC682CGN#TRPBF Lead Plastic SSOP C to 7 C LTC682IGN#PBF LTC682IGN#TRPBF 682I 6-Lead Plastic SSOP 4 C to 8 C LTC682HGN#PBF LTC682HGN#TRPBF 682H 6-Lead Plastic SSOP 4 C to 2 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: For more information on tape and reel specifi cations, go to: 682fc 3

4 LTC68/LTC682 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. Test conditions are V = 3V, V = V, V CM =.V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V OS Offset Voltage LTC68MS8, LTC682GN V CM =.V, 2.V LTC68MS8, LTC682GN V CM =.V, 2.V LTC68DD, LTC682DHC V CM =.V, 2.V LTC68DD, LTC682DHC V CM =.V, 2.V ΔV OS ΔT Input Offset Voltage Drift (Note ) I B Input Bias Current (Note 6) I OS Input Offset Current e n Input Referred Noise Noise Density at f = khz Integrated Noise From.Hz to Hz I n Input Noise Current Density (Note 7) C, I SUFFIXES H SUFFIX MIN TYP MAX MIN TYP MAX UNITS μv μv 7 7 μv 9 9 μv ±.2 ±.8 ±.2 ±.8 μv/ C pa pa pa pa nv/ Hz μv P-P.. fa/ Hz Input Common Mode Range V V V V V C DIFF Differential Input Capacitance 3 3 pf C CM Common Mode Input 7 7 pf Capacitance CMRR Common Mode Rejection V CM = V to.v 9 9 db Ratio V CM = V to.v V CM = V to 3V V CM = V to 3V db db db PSRR Power Supply Rejection Ratio V S = 2.7V to.v V OUT Output Voltage, High, Either Output Pin Output Voltage, Low, Either Output Pin (Referred to V ) No Load I SOURCE =.ma I SOURCE = ma No Load I SINK =.ma I SINK = ma db db mv mv mv A VOL Large-Signal Voltage Gain R LOAD = k,.v < V OUT < 2.V 2 2 db I SC Output Short-Circuit Current Source Sink SR Slew Rate A V = V/μs GBW Gain-Bandwidth Product R L = k MHz (f TEST = khz).8. MHz Φ Phase Margin R L = k 7 7 Deg t S Settling Time.% A V =, V Step 6 6 μs I S Supply Current No Load μa (Per Amplifier) μa Shutdown Current Shutdown, V SHDN.8V. μa (Per Amplifier) 2 μa V S Supply Voltage Range Guaranteed by the PSRR Test V Channel Separation f s = khz, R L = k 2 2 db mv mv mv ma ma 4 682fc

5 LTC68/LTC682 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. Test conditions are V = 3V, V = V, V CM =.V unless otherwise noted. C, I SUFFIXES H SUFFIX SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Shutdown Logic SHDN High 2 2 V SHDN Low.8.8 V THD Total Harmonic Distortion f = khz, V = 3V, V OUT = V P-P, R L = k 9 9 db t ON Turn-On Time V SHDN =.8V to 2V μs t OFF Turn-Off Time V SHDN = 2V to.8v 2 2 μs SHDN Pin Current V SHDN = V 2 μa The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. Test conditions are V = V, V = V, V CM =.V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V OS Offset Voltage LTC68MS8, LTC682GN V CM =.V LTC68MS8, LTC682GN V CM =.V LTC68DD, LTC682DHC V CM =.V LTC68DD, LTC682DHC V CM =.V ΔV OS ΔT Input Offset Voltage Drift (Note 8) I B Input Bias Current I OS Input Offset Current e n Input Referred Noise f = khz.hz to Hz I n Input Noise Current Density (Note 7) C, I SUFFIXES H SUFFIX MIN TYP MAX MIN TYP MAX UNITS μv μv 7 7 μv 9 9 μv ±.2 ±.8 ±.2 ±.8 μv/ C pa pa pa pa nv/ Hz μv P-P.. fa/ Hz Input Common Mode Range V V V V V C DIFF Differential Input Capacitance 3 3 pf C CM Common Mode Input 7 7 pf Capacitance CMRR Common Mode Rejection Ratio V CM = V to 3.V V CM = V to 3.V V CM = V to V PSRR Power Supply Rejection Ratio V S = 2.7V to.v V OUT Output Voltage, High, Either Output Pin (Referred to V ) Output Voltage, Low, Either Output Pin (Referred to V ) No Load I SOURCE =.ma I SOURCE = ma No Load I SINK =.ma I SINK = ma db db db db db mv mv mv A VOL Large-Signal Voltage Gain R LOAD = k,.v < V OUT < 4.V 2 2 db mv mv mv 682fc

6 LTC68/LTC682 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. Test conditions are V = V, V = V, V CM =.V unless otherwise noted. C, I SUFFIXES H SUFFIX SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS I SC Output Short-Circuit Current Source Sink ma ma SR Slew Rate A V = V/μs GBW Gain-Bandwidth Product R L = k MHz (f TEST = khz).8. MHz Φ Phase Margin R L = k 7 7 Deg t S Settling Time.% A V =, V Step 6 6 μs I S Supply Current No Load μa (Per Amplifier) μa Shutdown Current Shutdown, V SHDN.2V 6 μa (Per Amplifier) V S Supply Voltage Range Guaranteed by the PSRR Test V Channel Separation f s = khz, R L = k 2 2 db Shutdown Logic SHDN High V SHDN Low.2.2 V THD Total Harmonic Distortion f = khz, V = V, V OUT = 2V P-P, R L = k 9 9 db t ON Turn-On Time V SHDN =.2V to 3.V μs t OFF Turn-Off Time V SHDN = 3.V to.2v 2 2 μs SHDN Pin Current V SHDN = V 2 μa Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many amplifiers are shorted. Note 3: The LTC68C/LTC682C and LTC68I/LTC682I are guaranteed functional over the operating temperature range of 4 C to 8 C. The LTC68H/LTC682H are guaranteed functional over the operating temperature range of 4 C to 2 C. Note 4: The LTC68C/LTC682C are guaranteed to meet specifi ed performance from C to 7 C. The LTC68C/LTC682C are designed, characterized and expected to meet specifi ed performance from 4 C to 8 C but are not tested or QA sampled at these temperatures. The LTC68I/LTC682I are guaranteed to meet specifi ed performance from 4 C to 8 C. The LTC68H/LTC682H are guaranteed to meet specified performance from 4 C to 2 C. Note : Input offset drift is computed from the limits of the V OS test divided by the temperature range. This is a conservative estimate of worst case drift. Consult the Typical Performance Characteristics section for more information on input offset drift. Note 6: I B guaranteed by the test. Note 7: Current noise is calculated from I n = 2qI B, where q =.6 9 coulomb. Note 8: V OS drift is guaranteed by the test fc

7 TYPICAL PERFORMANCE CHARACTERISTICS LTC68/LTC682 V OS Drift Histogram V OS Drift Histogram V OS vs Temperature NUMBER OF AMPS (OUT OF ) LTC68MS8 T A = 4 C TO 2 C V CM =.V NUMBER OF AMPS (OUT OF ) 2 2 LTC68DFN T A = 4 C TO 2 C V CM =.V V OS (μv) 2 2 LTC68MS8 V CM =.V REPRESENTATIVE PARTS.2.. V OSDRIFT (μv/ C) G V OSDRIFT (μv/ C) G TEMPERATURE ( C) G3 V OS Histogram V OS vs V CM V OS vs V CM NUMBER OF AMPS (OUT OF ) LTC68MS8 V CM =.V V OS (μv) REPRESENTATIVE PARTS V OS (μv) REPRESENTATIVE PARTS V OS (μv) G V CM (V) G V CM (V) G6 V OS vs Output Current Warm-Up Drift vs Time Noise Voltage vs Frequency V OS (μv) 2 V CM = 2.V T A = 2 C T A = C SINKING SOURCING CURRENT CURRENT OUTPUT CURRENT (ma) 682 G7 CHANGE IN OFFSET VOLTAGE (μv) 2 2 V CM =.V TIME AFTER POWER UP (s) 682 G8 NOISE VOLTAGE (nv/ Hz) V CM =.V V CM =.V k k k FREQUENCY (Hz) 682 G9 682fc 7

LTC68/LTC682 TYPICAL PERFORMANCE CHARACTERISTICS NOISE VOLTAGE (nv/ Hz) 3 28 26 24 22 2 8 6 4 2 8 6 4 2 Noise Voltage vs Frequency PMOS INPUTS V CM =.V NMOS INPUTS V CM = 2.

V 2 2 3 3 4 4 TIME (s) 682 G2 Input Bias Current vs Temperature I BIAS vs V CM I BIAS vs V CM INPUT BIAS CURRENT (pa) V CM = 2.

8 LTC68/LTC682 TYPICAL PERFORMANCE CHARACTERISTICS NOISE VOLTAGE (nv/ Hz) Noise Voltage vs Frequency PMOS INPUTS V CM =.V NMOS INPUTS V CM = 2.V k k k FREQUENCY (Hz) 682 G OUTPUT NOISE (nv/div).hz to Hz Output Voltage Noise V CM =.V TIME (s) 682 G OUTPUT NOISE (μv/div).hz to Hz Output Voltage Noise V CM = 2.V TIME (s) 682 G2 Input Bias Current vs Temperature I BIAS vs V CM I BIAS vs V CM INPUT BIAS CURRENT (pa) V CM = 2.V I BIAS (pa) LTC68MS8 T A = 7 C T A = 8 C I BIAS (pa) LTC68MS8 T A = 2 C TEMPERATURE ( C) 682 G V CM (V) G V CM (V) G Large Signal Transient Small Signal Transient Overshoot vs C L 4 V CM =.V.V/DIV V S = ±.V R L = k C L = pf 2μs/DIV GND 682 G6 2mV/DIV V S = ±.V R L = k C L = pf 2μs/DIV GND 682 G7 OVERSHOOT (%) A V = CAPACITIVE LOAD (pf) A V = 682 G fc

9 TYPICAL PERFORMANCE CHARACTERISTICS LTC68/LTC682 Supply Current vs Temperature Supply Current vs Time Output Impedance vs Frequency SUPPLY CURRENT (μa) V CM =.V PER AMPLIFIER TEMPERATURE ( C) 682 G9 SUPPLY CURRENT OPAMP (μa) NO BYPASS CAPACITOR SUPPLY VOLTAGE SUPPLY CURRENT TIME (μs) 682 G SUPPLY VOLTAGE (V) OUTPUT IMPEDANCE (Ω) A V = A V = A V =. V CM =.V. k k k M M M FREQUENCY (Hz) 682 G2 Open Loop Gain Open Loop Gain Open Loop Gain vs Frequency INPUT VOLTAGE (μv) OUTPUT VOLTAGE (V) R L = k R L = k R L = 2k G22 INPUT VOLTAGE (μv) R L = k R L = k R L = 2k OUTPUT VOLTAGE (V) 682 G23 GAIN (db) V CM =.V 4 k k PHASE GAIN k M FREQUENCY (Hz) R L = k R L = k M M 682 G24 PHASE (DEG) 6 4 Open Loop Gain vs Frequency CMRR vs Frequency PSRR vs Frequency PHASE R L = k R L = k V CM =.V R L = k 2 8 V CM =.V GAIN (db) 2 V 2 S = V V CM =.V C L = 2pF 4 k k GAIN k M FREQUENCY (Hz) M M 682 G2 PHASE (DEG) CMRR (db) k k k M M M FREQUENCY (Hz) PSRR (db) k k k M M M FREQUENCY (Hz) 682 G G27 682fc 9

10 LTC68/LTC682 TYPICAL PERFORMANCE CHARACTERISTICS CHANNEL SEPARATION (db) Channel Separation vs Frequency V CM =.V R L = k 4 k k k M M M FREQUENCY (Hz) 682 G28 OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGE) V S V S. V S. V S. V S 2. V S 2. V S. Output Voltage Swing vs Load Current V CM =.V SOURCE V S. T A = 2 C T SINK V S. A = 2 C T A = C V S.. LOAD CURRENT (ma) 6789 G29 DISTORTION (dbc) Distortion vs Frequency A V = R L = k V OUT = 2V P-P 2ND FREQUENCY (khz) 3RD 682 G3 PIN FUNCTIONS OUT: Amplifi er Output IN: Inverting Input IN: Noninverting Input V : Positive Supply V : Negative Supply SHDN_A: Shutdown Pin of Amplifier A, active low and only valid for LTC68DD. An internal current source pulls the pin to V when floating. SHDN_B: Shutdown Pin of Amplifier B, active low and only valid for LTC68DD. An internal current source pulls the pin to V when floating. NC: Not internally connected. Exposed Pad: Connected to V. 682fc

11 LTC68/LTC682 APPLICATIONS INFORMATION Preserving Input Precision Preserving input accuracy of the LTC68/LTC682 requires that the application circuit and PC board layout do not introduce errors comparable or greater than the μv typical offset of the amplifiers. Temperature differentials across the input connections can generate thermocouple voltages of s of microvolts so the connections to the input leads should be short, close together and away from heat dissipating components. Air current across the board can also generate temperature differentials. The extremely low input bias currents (.pa typical) allow high accuracy to be maintained with high impedance sources and feedback resistors. Leakage currents on the PC board can be higher than the input bias current. For example, GΩ of leakage between a V supply lead and an input lead will generate pa! Surround the input leads with a guard ring driven to the same potential as the input common mode voltage to avoid excessive leakage in high impedance applications. Capacitive Load LTC68/LTC682 can drive capactive load up to 2pF in unity gain. The capacitive load driving capability increases as the amplifier is used in higher gain confi gurations. A small series resistance between the output and the load further increases the amount of capacitance the amplifier can drive. SHDN Pins Pins and 6 are used for power shutdown on the LTC68 in the DD package. If they are fl oating, internal current sources pull Pins and 6 to V and the amplifiers operate normally. In shutdown, the amplifier output is high impedance, and each amplifi er draws less than 2μA current. Rail-to-Rail Input The input stage of LTC68/LTC682 combines both PMOS and NMOS differential pairs, extending its input common mode voltage range to both positive and negative supply voltages. At high input common mode range, the NMOS pair is on. At low common mode range, the PMOS pair is on. The transition happens when the common voltage is between.3v and.9v below the positive supply. LTC68 has better low frequency noise performance with PMOS input on due to its lower flicker noise (see Voltage Noise vs Frequency and.hz to Hz Input Voltage Noise in Typical Performance Characteristics). Thermal Hysteresis Figure shows the input offset voltage hysteresis of the LTC68IMS8 for 3 thermal cycles from 4 C to 9 C. The typical offset shift is ±4μV. The data was taken with the ICs in stress free sockets. Mounting to PC boards may cause additional hysteresis due to mechanical stress. The LTC68 will meet offset voltage specifications in the electrical characteristics table even after μv of additional error from thermal hysteresis. PERCENTAGE OF UNITS V OS CHANGE AFTER 3 THERMAL CYCLES V CM =.V V = 3V 3 UNITS V OS CHANGE (μv) F Figure. V OS Thermal Hysteresis of LTC68MS8 682fc

12 LTC68/LTC682 APPLICATIONS INFORMATION PC Board Layout Mechanical stress on a PC board and soldering-induced stress can cause the V OS and V OS drift to shift. The DD and DHC packages are more sensitive to stress. A simple way to reduce the stress-related shifts is to mount the IC near the short edge of the PC board, or in a corner. The board edge acts as a stress boundary, or a region where the flexure of the board is minimum. The package should always be mounted so that the leads absorb the stress and not the package. The package is generally aligned with the leads perpendicular to the long side of the PC board (see Figure 2). The most effective technique to relieve the PC board stress is to cut slots in the board around the op amp. These slots can be cut on three sides of the IC and the leads can exit on the fourth side. Figure 2 shows the layout of a LTC68DD with slots at three sides. LONG DIMENSION SLOTS Figure 2. Vertical Orientation of LTC68DD with Slots 682 F2 SIMPLIFIED SCHEMATIC Simplifi ed Schematic of the Amplifi er V M M R R2 M8 μa V I2 D4 V V BIAS M I A C V V D2 SHDN D V V IN IN BIAS GENERATION D3 V NOTE: SHDN IS ONLY AVAILABLE IN THE DFN PACKAGE CLAMP V D6 D V M M3 M2 M4 M6 M7 R3 A2 R4 OUTPUT CONTROL C2 D7 OUT D8 V M9 682 SS 2 682fc

13 TYPICAL APPLICATIONS LTC68/LTC682 Low Side Current Sense pf k V V DD I R SH LOAD k /2 LTC68 e NOISE = 3μV P-P, RTI BW ~ khz V OUT = R SH I 682 TA3 Two Op-Amp Instrumentation Amplifi er.96k GAIN TRIM k k CMRR TRIM k 976k V IN V.μF /2 LTC68 k /2 LTC68 M V OUT = V IN V.μF 682 TA4 682fc 3

14 LTC68/LTC682 TYPICAL APPLICATIONS Thermocouple Amplifi er V.μF M M μf /2 LTC68 V V OUT = mv/ C C TO C LT2 K R k 2.49M pf SENSOR: OMEGA TC-TT-K-3-36 K-TYPE THERMOCOUPLE M RESISTORS PROTECT CIRCUIT TO ±3V WITH NO PHASE REVERSAL OF AMPLIFIER OUTPUT pa MAX I BIAS TRANSLATES TO. C ERROR 2μV V OS. C OFFSET 682 TA Precision Nanoamp Bidirectional Current Source V IN k Ω k /4 LTC682 Ω.μF GAIN TRIM k 97.6k k -TURN 3.9pF k /4 LTC682 k 2.V.μF.μF /4 LTC682 mω I OUT = na na FOR V IN = V V TOTAL ERROR <±% (pa) 2.V 682 TA6 LOAD I OUT 4 682fc

15 PACKAGE DESCRIPTION DD Package -Lead Plastic DFN (3mm 3mm) (Reference LTC DWG # Rev B) LTC68/LTC (2 SIDES) PACKAGE OUTLINE.2.. BSC (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R =.2 TYP 6.4. PIN TOP MARK (SEE NOTE 6).2 REF 3.. (4 SIDES) (2 SIDES) (2 SIDES).2.. BSC BOTTOM VIEW EXPOSED PAD NOTE:. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE (DD) DFN REV B fc

16 LTC68/LTC682 PACKAGE DESCRIPTION DHC Package 6-Lead Plastic DFN (mm 3mm) (Reference LTC DWG # -8-76).6 ±. 3. ±. 2.2 ±..6 ±. (2 SIDES) PACKAGE OUTLINE 4.4 ±. (2 SIDES).2 ±.. BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS. ±. (2 SIDES) R =.2 TYP 9 R =. TYP 6.4 ±. PIN TOP MARK (SEE NOTE 6).2 REF 3. ±. (2 SIDES).7 ±..6 ±. (2 SIDES).. NOTE:. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-) IN JEDEC PACKAGE OUTLINE MO DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE ±. (2 SIDES).2 ±.. BSC BOTTOM VIEW EXPOSED PAD PIN NOTCH (DHC6) DFN fc

17 PACKAGE DESCRIPTION GN Package 6-Lead Plastic SSOP (Narrow. Inch) (Reference LTC DWG # -8-64) LTC68/LTC682.4 ± * ( ) (.229) REF.24 MIN ( )..7** ( ).6 ±. RECOMMENDED SOLDER PAD LAYOUT.2 BSC ( ). ±.4 4 (.38 ±.) 8 TYP (.3.7).4.98 (.2.249).6. (.46.27) NOTE:. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.2mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.24mm) PER SIDE.8.2 (.23.3) TYP.2 (.63) BSC GN6 (SSOP) fc 7

18 LTC68/LTC682 PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # Rev F).889 ±.27 (.3 ±.).23 (.26) MIN (.26.36).42 ±.38 (.6 ±.) TYP.6 (.26) BSC 3. ±.2 (.8 ±.4) (NOTE 3) (.2) REF RECOMMENDED SOLDER PAD LAYOUT GAUGE PLANE.8 (.7).24 (.) DETAIL A DETAIL A NOTE:. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 6 TYP.3 ±.2 (.2 ±.6) SEATING PLANE 4.9 ±.2 (.93 ±.6). (.43) MAX (.9.) TYP.6 (.26) BSC DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.2mm (.6") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.2mm (.6") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.2mm (.4") MAX 3. ±.2 (.8 ±.4) (NOTE 4).86 (.34) REF.6 ±.8 (.4 ±.2) MSOP (MS8) 37 REV F 8 682fc

19 LTC68/LTC682 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 3/ Change LT to LTC on all part numbers in Order Information Section. 3 C 7/ Update to Simplifi ed Schematic 2 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 682fc 9

20 LTC68/LTC682 TYPICAL APPLICATION Single Supply Strain Gauge Amplifi er 3Ω 3V M 9.76M CMRR TRIM k 3V Ω.μF k 3Ω M 3.2V.μF /2 LTC68 k.μf LT79B.2V.2V /2 LTC68 A V = M SENSOR: OMEGA SG-3/3-LY4 STRAIN GAUGE 682 TA2 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT678/LT679 Dual/Quad Precision Op Amps Low Noise, 2.7V to 36V Operation LTC2 Zero-Drift Op Amp 2.7V Operation, SOT-23 Package LTC2/LTC22 Dual/Quad Zero-Drift Op Amps MS8/GN6 Packages LTC24/LTC2 Single/Dual Zero-Drift Op Amp Micropower, SOT-23 and DFN Packages LTC678/LTC679 Dual/Quad Low Noise Precision CMOS Op Amps Micropower.7μV/ C V OS Drift LTC624/LTC6242 Dual/Quad Low Noise CMOS Op Amps 8MHz Bandwidth,V/μs Slew Rate LTC6244 Dual MHz CMOS Op Amp Low Noise, Rail-to-Rail Out, MS8 and DFN Packages 2 LT 7 REV C PRINTED IN USA Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION fc

LTC6087/LTC6088 Dual/Quad 14MHz, Rail-to-Rail CMOS Amplifi ers DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

LTC6087/LTC6088 Dual/Quad 14MHz, Rail-to-Rail CMOS Amplifi ers DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION LTC687/LTC688 Dual/Quad 4MHz, Rail-to-Rail CMOS Amplifi ers FEATURES n Low Offset Voltage: 7μV Maximum n Low Offset Drift: μv/ C Maximum n Input Bias Current: pa (Typical at 2 C) pa (Typical at 8 C) n