DESCRIPTIO TYPICAL APPLICATIO. LT MHz Gain of 1 Triple Video Buffer FEATURES APPLICATIO S

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1 LT MHz Gain of Triple Video Buffer FEATRES MHz db Small Signal Bandwidth MHz db V P-P Large Signal Bandwidth MHz ±.db Bandwidth High Slew Rate: V/µs Fixed Gain of Requires No External Resistors 9dB Channel Separation at MHz db Channel Separation at MHz dbc nd Harmonic Distortion at MHz, V P-P 9dBc rd Harmonic Distortion at MHz, V P-P Low Supply Current: ma per Amplifier ns.% Settling Time for V Step TTL Compatible Enable: I SS µa When Disabled Differential Gain of.%, Differential Phase of. Wide Supply Range: ±.V (.V) to ±V (V) Available in -Lead SSOP Package APPLICATIO S RGB Buffers A/D Drivers LCD Projectors DESCRIPTIO The LT is a high-speed triple video buffer with an internally fixed gain of. The individual buffers are optimized for performance with a k load and feature a V P P full signal bandwidth of MHz, making them ideal for driving very high-resolution video signals. Separate power supply pins for each amplifier boost channel separation to 9dB, allowing the LT to excel in many highspeed applications. While the performance of the LT is optimized for dual supply operation, it can also be used on a single supply as low as.v. sing dual V supplies, each amplifier draws only ma. When disabled, the amplifiers draw less than µa and the outputs become high impedance. Furthermore, the amplifiers are capable of turning on in less than ns, making them suitable for multiplexing and portable applications. The LT is manufactured on Linear Technology s proprietary low voltage complementary bipolar process and is available in the -lead SSOP package that fits in the same PCB area as an SO- package., LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO R IN G IN B IN V 7 Triple Video Buffer and A/D Driver LT + Ω Ω + Ω + V V 9 V V k k k TAa OTPT (V)..... Large Signal Transient Response V OT = V P P R L = k. TIME (ns) TAb fa

2 LT ABSOLTE AXI RATI GS (Note ) W W W Total Supply Voltage ( to )....V Input Current (Note )... ±ma Output Current (Continuous)... ±7mA EN to DGND Voltage (Note )....V Output Short-Circuit Duration (Note )... Indefinite Operating Temperature Range (Note )... C to C Specified Temperature Range (Note )... C to C Storage Temperature Range... C to C Junction Temperature... C Lead Temperature (Soldering, sec)... C W PACKAGE/ORDER I FOR ATIO EN DGND INR ING INB 7 TOP VIEW G = + G = + G = + OTR OTG OTB 9 GN PACKAGE -LEAD PLASTIC SSOP T JMAX = C, θ JA = C/W ORDER PART NMBER LTCGN LTIGN GN PART MARKING I Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at., R L = k, C L =.pf, V EN =.V, V, V DGND = V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Offset Voltage V IN = V, V OS = V OT ± mv ±7 mv I IN Input Current 7 ± µa e n Output Noise Voltage f = khz nv Hz i n Input Noise Current f = khz. pa Hz R IN Input Resistance V IN = ±V kω C IN Input Capacitance f = khz pf PSRR Power Supply Rejection Ratio V S (Total) =.V to V (Note ) db I PSRR Input Current Power Supply V S (Total) =.V to V (Note ) ± µa/v Rejection A V ERR Gain Error V OT = ±V.. % A V MATCH Gain Matching Any One Channel to Another ±. % V OT Maximum Output Voltage Swing ±.7 ±. V I S Supply Current, Per Amplifier R L = ma R L = ma Supply Current, Disabled, Total V EN = V µa V EN = Open. µa I EN Enable Pin Current V EN =.V 9 µa V EN =. µa I SC Output Short-Circuit Current R L = Ω, V IN = ±V ± ± ma SR Slew Rate V P-P Output Step (Note 9) 7 V/µs db BW Small Signal db Bandwidth V OT = mv P-P MHz.dB BW Gain Flatness ±.db Bandwidth V OT = mv P-P MHz fa

3 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at., R L = k, C L =.pf, V EN =.V, V, V DGND = V. LT SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS LSBW Large Signal Bandwidth V OT = V P-P (Note 7) 7 MHz V OT = V P-P (Note 7) MHz All-Hostile Crosstalk f = MHz, V OT = V P-P 9 db f = MHz, V OT = V P-P db t S Settling Time.% of V FINAL, V STEP = V ns t R, t F Small-Signal Rise and Fall Time % to 9%, V OT = mv P-P ps dg Differential Gain (Note ). % dp Differential Phase (Note ). Deg HD nd Harmonic Distortion f = MHz, V OT = V P-P dbc HD rd Harmonic Distortion f = MHz, V OT = V P-P 9 dbc Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : This parameter is guaranteed to meet specified performance through design and characterization. It is not production tested. Note : As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Depending on the supply voltage, a heat sink may be required. Note : The LTC is guaranteed functional over the operating temperature range of C to C. Note : The LTC is guaranteed to meet specified performance from C to 7 C. The LTC is designed, characterized and expected to meet specified performance from C and C but is not tested or QA sampled at these temperatures. The LTI is guaranteed to meet specified performance from C to C. Note : The two supply voltage settings for power supply rejection are shifted from the typical ±V S points for ease of testing. The first measurement is taken at = V, =.V to provide the required V headroom for the enable circuitry to function with EN, DGND, and all inputs connected to V. The second measurement is taken at = V, = V. Note 7: Large signal bandwidth is calculated from the slew rate: LSBW = SR/(π V P-P ) Note : Differential gain and phase are measured using a Tektronix TSGYC/NTSC signal generator and a Tektronix 7R video measurement set. The resolution of this equipment is better than.% and.. Nine identical amplifier stages were cascaded giving an effective resolution of better than.% and.. Note 9: Slew rate is % production tested on the G channel. Slew rate of the R and B channels is guaranteed through design and characterization. fa

4 LT TYPICAL PERFOR A CE CHARACTERISTICS W Supply Current per Amplifier vs Temperature Supply Current per Amplifier vs Supply Voltage Supply Current per Amplifier vs EN Pin Voltage SPPLY CRRENT (ma) V EN = V V EN =.V R L = V IN = V SPPLY CRRENT (ma) = V EN, V DGND, V IN = V SPPLY CRRENT (ma) T A = C T A = C V DGND = V V IN = V TEMPERATRE ( C) 7 9 TOTAL SPPLY VOLTAGE (V) EN PIN VOLTAGE (V) G G G Offset Voltage vs Temperature Input Bias Current vs Input Voltage EN Pin Current vs EN Pin Voltage OFFSET VOLTAGE (mv) V IN = V TYPICAL PART INPT BIAS CRRENT (µa) T A = C T A = C EN PIN CRRENT (µa) V DGND = V T A = C T A = C.. TEMPERATRE ( C) INPT VOLTAGE (V) EN PIN VOLTAGE (V) G G G OTPT VOLTAGE (V) Output Voltage vs Input Voltage R L = k T A = C OTPT VOLTAGE (V) Output Voltage Swing vs I LOAD (Output High) V IN = V T A = C T A = C OTPT VOLTAGE (V) Output Voltage Swing vs I LOAD (Output Low) V IN = V T A = C T A = C T A = C INPT VOLTAGE (V) 7 9 SORCE CRRENT (ma) 7 9 SINK CRRENT (ma) G7 G G9 fa

5 LT TYPICAL PERFOR A CE CHARACTERISTICS W INPT NOISE (nv/ Hz OR pa/ Hz) Input Noise Spectral Density Input Impedance vs Frequency PSRR vs Frequency e n i n INPT IMPEDANCE (kω) V IN = V REJECTION RATIO (db) 7 ±PSRR +PSRR PSRR... FREQENCY (khz) G... G... G AMPLITDE (db) R L = k C L =.pf. Frequency Response Gain Flatness vs Frequency Crosstalk vs Frequency V OT = mv P-P V OT = V P-P V OT = V P-P AMPLITDE (db) V OT = mv P-P R L = k C L =.pf TYPICAL PART G-CHANNEL R-CHANNEL B-CHANNEL.. G G AMPLITDE (db). V OT = V P-P R L = k ALL- HOSTILE WORST ADJACENT G AMPLITDE (db) V OT = mv P-P R L = k. Frequency Response with Capacitive Loads Harmonic Distortion vs Frequency Output Impedance vs Frequency C L = 9pF C L =.pf C L =.pf C L = pf C L =.pf DISTORTION (dbc) V OT = V P-P R L = k 7 HD 9 HD.. OTPT IMPEDANCE (Ω).. DISABLED V EN = V ENABLED V EN =.V R L = k. G G7 G fa

6 LT TYPICAL PERFOR A CE CHARACTERISTICS W Maximum Capacitive Load vs Output Series Resistor Small Signal Transient Response Video Amplitude Transient Response OTPT SERIES RESISTANCE (Ω) AC PEAKING >db V OT = V P P R L = k OTPT (V)..... V IN = mv P P R L = k OTPT (V) V IN = 7mV P P R L = k CAPACITIVE LOAD (pf). TIME (ns). TIME (ns) G G9 G OTPT (V)..... Large Signal Transient Response V IN = V P P R L = k OTPT (V) Large Signal Transient Response V IN = V P P R L = k. TIME (ns) TIME (ns) G G PERCENT OF NITS (%) Gain Error Distribution V OT = ±V R L = k PERCENT OF NITS (%) Gain Error Matching Distribution V OT = ±V R L = k GAIN ERROR INDIVIDAL CHANNEL (%) GAIN ERROR BETWEEN CHANNELS (%) G G fa

7 LT PI F CTIO S EN (Pin ): Enable Control Pin. An internal pull-up resistor of k defines the pin s impedance and will turn the part off if the pin is unconnected. When the pin is pulled low, the part is enabled. DGND (Pin ): Digital Ground Reference for Enable Pin. This pin is normally connected to ground. INR (Pin ): Red Channel Input. This pin has a nominal impedance of kω and does not have any internal termination resistor. (Pin ): Analog Ground for Isolation Between Red and Green Channel Inputs. The pins have ESD protection and therefore should not be connected to potentials outside the power supply range. ING (Pin ): Green Channel Input. This pin has a nominal impedance of kω and does not have any internal termination resistor. (Pin ): Analog Ground for Isolation Between Green and Blue Channel Inputs. The pins have ESD protection and therefore should not be connected to potentials outside the power supply range. INB (Pin 7): Blue Channel Input. This pin has a nominal impedance of kω and does not have any internal termination resistor. (Pin ): Negative Supply Voltage. pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. (Pin 9): Negative Supply Voltage for Blue Channel Output Stage. pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OTB (Pin ): Blue Channel Output. It is the buffered output of the blue channel input. (Pin ): Positive Supply Voltage for Blue and Green Channel Output Stages. pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OTG (Pin ): Green Channel Output. It is the buffered output of the green channel input. (Pin ): Negative Supply Voltage for Green and Red Channel Output Stages. pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OTR (Pin ): Red Channel Output. It is the buffered output of the red channel input. (Pin ): Positive Supply Voltage for Red Channel Output Stage. pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. (Pin ): Positive Supply Voltage. pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. fa 7

8 LT APPLICATIO S I FOR Power Supplies The LT is optimized for ±V supplies but can be operated on as little as ±.V or a single.v supply and as much as ±V or a single V supply. Internally, each supply is independent to improve channel isolation. Do not leave any supply pins disconnected! Enable/Shutdown The LT has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above V or allowing the internal k pull-up resistor to pull the EN pin to the top rail will disable the amplifier. When disabled, the output will become very high impedance. Supply current into the amplifier in the disabled state will be primarily through and approximately equal to ( V EN )/k. It is important that the two following constraints on the DGND pin and the EN pin are always followed: V DGND V V EN V DGND.V Split supplies of ±V to ±.V will satisfy these requirements with DGND connected to V. In single supply applications above.v, an additional resistor may be needed from the EN pin to DGND if the pin is ever allowed to float. For example, on a V single supply, a k resistor to ground would protect the pin from floating too high while still allowing the internal pull-up resistor to disable the part. On dual ±.V supplies, connecting the EN and DGND pins to is the easiest way of ensuring that V DGND is more than V. The DGND pin should not be pulled above the EN pin since doing so will turn on an ESD protection diode. If the EN pin voltage is forced a diode drop below the DGND pin, current should be limited to ma or less. The enable/disable times of the LT are fast when driven with a logic input. Turn on (from % EN input to % output) typically occurs in less than ns. Turn off is slower, but is nonetheless below ns. ATIO W Input Considerations The LT input voltage range is from + V to V and is therefore larger than the output swing. The inputs can be driven beyond the point at which the output clips so long as input currents are limited to below ±ma. Layout and Grounding It is imperative that care is taken in PCB layout in order to utilize the very high speed and very low crosstalk of the LT. Separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. If input traces must be run over a distance of several centimeters, they should use a controlled impedance with either series or shunt terminations (nominally Ω or 7Ω) to maintain signal fidelity. Care should be taken to minimize capacitance on the LT s output traces by increasing spacing between traces and adjacent metal and by eliminating metal planes in underlying layers. To drive cable or traces longer than several centimeters, using the LT with its fixed gain of + in conjunction with series and load termination resistors may provide better results. A plot of LT performance driving a k load with various trace lengths is shown in Figure. All data is from a -layer board with oz copper, mil of board layer thickness to the ground plane, a trace width of mils and spacing to adjacent metal of mils. The.cm output trace places the k resistor as close to the part as possible, while the other curves show the load resistor consecutively further away. The worst case, cm, trace has almost pf of parasitic capacitance. In order to counteract any peaking in the frequency response from driving a capacitive load, a series resistance can be inserted in the line at the output of the part to flatten the response. Figure shows the frequency response with the same cm trace from Figure, now with a Ω series resistor inserted near the output pin of the LT. Note that using a Ω series resistor with a k load only decreases the output amplitude by.db or % and has a minimal effect on the bandwidth of the system. See the graph labeled Maximum Capacitive Load vs Output Series Resistor in the Typical Performance Characteristics section for more information. fa

9 LT APPLICATIO S I FOR ATIO AMPLITDE (db) AMPLITDE (db). W Figure. Response vs Output Trace Length. V OT = mv P-P R L = k V OT = mv P-P R L = k cm TRACE cm TRACE.cm TRACE cm TRACE cm TRACE R S, OT = Ω F F Figure. Response vs Series Output Resistance While the pins on the LT are not connected to the amplifier circuitry, tying them to ground or another quiet node significantly increases channel isolation and is always recommended. The pins do have ESD protection and therefore should not be connected to potentials outside the power supply range. Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One 7pF ceramic capacitor is recommended for both and. Additional 7pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high current drive and large-signal transient applications, additional µf to µf tantalums should be added on each supply. The smallest value capacitors should be placed closest to the package. To maintain the LT s channel isolation, it is beneficial to shield parallel input and output traces using a ground plane or power supply traces. Vias between topside and backside metal are recommended to maintain a low inductance ground, especially between closely spaced signal traces. Single Supply Operation Figure illustrates how to use the LT with a single supply ranging from.v to V. Since the output range is comparable to the input range, the DC bias point at the input can be set anywhere between the supplies that will prevent the AC-coupled signal from running into the output range limits. As shown, the DC input level is midsupply. The only additional power dissipation in the single supply configuration is through the resistor bias string at the input and through any load resistance at the output. In many cases, the output can be used to directly drive other single supply devices without additional coupling and without any resistive load. ESD Protection The LT has reverse-biased ESD protection diodes on all pins. If any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may flow through these diodes. If the current is kept below ma, no damage to the device will occur. V IN µf k k / LT Figure. Single Supply Configuration, One Channel Shown IN.V TO V OT F fa 9

10 LT TYPICAL APPLICATIO RGB Buffer Demo Board The DC79 Demo Board illustrates optimal routing, bypassing and termination using the LT as an RGB video buffer. The schematic is shown in Figure. All inputs and outputs are routed to have a characteristic impedance of 7Ω. The 7Ω input shunt and output series terminations are connected as close to the part as possible. While the 7Ω back termination resistors at the outputs of the LT minimize signal reflections in the output traces and isolate the part from any capacitive loading in those traces, they also contribute to gain error if the output is not terminated with high impedance. For example, if the output is terminated with a k load, the 7Ω back termination will cause a 7% gain error. Decreasing the value of the back termination resistors will decrease the signal attenuation but may compromise the AC response. However, connecting the LT outputs to the output traces on the DC79 board without some series resistance is not recommended; Ω to Ω is generally sufficient. A fourth signal trace is provided at the bottom of the DC79 demo board with dimensions identical to the E EN combined input and output of the other channels. This trace can be used for calibrating the effects of electrical delay and impedance mismatching and is not necessary in an end-user application. Jumpers and additional connectors are also included to allow for evaluation of the enable feature and single supply operation. RGB Video Selector/Cable Driver A video multiplexer can be implemented using the EN pins of parallel LTs as shown in Figure. In this application, the corresponding outputs are connected together and one LT is switched on while the other is switched off. A fast inverter provides a complementary signal to ensure that only one set of R, G and B channels is buffered at any time. Since the output impedance of a disabled LT is very high, adding additional channels will not resistively load an enabled output. However, since the disabled LT has around pf of capacitance, it may be desirable to resistively isolate the outputs of each channel to maintain flat frequency response as shown in the graph labeled Maximum Capacitive Load vs Output Series Resistor in the Typical Performance Characteristics section. INR ING INB CAL J Ω BNC EN BNC J J J7 J BNC J BANANA JACK JP DGND FLOAT Z = 7 Z = 7 Z = 7 E R 7Ω SINGLE DAL JP SPPLY E DGND R 7Ω JP CONTROL ENABLE EXT R 7Ω C 7pF 7 C pf EN DGND INR ING INB LT C7 7pF OTR OTG OTB Figure. DC79 Demo Board Schematic 9 C 7pF C9 µf, V C 7pF R 7Ω R 7Ω R 7Ω C 7pF C 7pF Z = 7 Z = 7 Z = 7 Z = 7 ALL BNC: CANARE BCJ-BPLH C J µf, V BANANA JACK BNC x J9 OTR OTG J OTB J J BANANA JACK CAL J BNC F fa

11 LT SI PLIFIED SCHE ATIC W W BIAS TO OTHER AMPLIFIERS k EN k IN Ω Ω OT DGND SS PACKAGE DESCRIPTIO GN Package -Lead Plastic SSOP (Narrow. Inch) (Reference LTC DWG # --). ±..9.9* (..97) 9.9 (.9) REF. MIN...9. (.7.9)..7** (..9). ±. RECOMMENDED SOLDER PAD LAYOT. TYP (.7.9). ±. (. ±.) TYP.. (..77)..9 (..9).. (..7) NOTE:. CONTROLLING DIMENSION: INCHES INCHES. DIMENSIONS ARE IN (MILLIMETERS). DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE **DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..). (.) BSC GN (SSOP) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fa

12 LT TYPICAL APPLICATIO.V NC7SZ LT R G B 7Ω 7Ω 7Ω 7 9 R OT G OT SEL LT B OT R G B 7Ω 7Ω 7Ω 7 9 NOTE: POWER SPPLY BYPASS CAPACITORS NOT SHOWN FOR CLARITY.V F Figure. RGB Video Selector and A/D Driver RELATED PARTS PART NMBER DESCRIPTION COMMENTS LT9/LT Dual/Triple MHz Current Feedback Amplifiers Shutdown, Operates to ±V LT9/LT9/LT97 Single/Dual/Quad MHz Current Feedback Amplifiers V/µs Slew Rate LT9/LT99 Dual/Triple MHz Current Feedback Amplifiers.dB Gain Flatness to MHz, Shutdown LT7/LT7- MHz, Triple and Single RGB Multiplexer with MHz Pixel Switching, db Bandwidth: MHz, Current Feedback Amplifiers V/µs Slew Rate LT9/LT Single/Dual, MHz, Rail-to-Rail Input and V/µs Slew Rate, Shutdown, Output Amplifiers Low Distortion 9dBc at MHz LT/LT.V Triple and Quad Video Buffers MHz Gain of Buffers in MSOP Package LT MHz, Gain of, Triple Video Amplifier Same Pinout as LT LT/TP K REV A PRINTED IN SA Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9-77 () -9 FAX: () -7 LINEAR TECHNOLOGY CORPORATION fa

TYPICAL APPLICATIO. LT MHz, 250V/µs, A V 4 Operational Amplifier DESCRIPTIO FEATURES APPLICATIO S

TYPICAL APPLICATIO. LT MHz, 250V/µs, A V 4 Operational Amplifier DESCRIPTIO FEATURES APPLICATIO S 5MHz, 5V/µs, A V Operational Amplifier FEATRES Gain-Bandwidth: 5MHz Gain of Stable Slew Rate: 5V/µs Input Noise Voltage: nv/ Hz C-Load TM Op Amp Drives Capacitive Loads Maximum Input Offset Voltage: µv