LT MHz Differential ADC Driver/Dual Selectable Gain Amplifi er DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

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1 FEATURES 65MHz 3dB Small-Signal Bandwidth 6MHz 3dB Large-Signal Bandwidth High Slew Rate: 33V/µs Easily Configured for Single-Ended to Differential Conversion MHz ±.db Bandwidth User Selectable Gain of, and No External Resistors Required 46.5dBm Equivalent OIP3 at 3MHz When Driving an ADC IM3 with V P-P Composite, Differential Output: 87dBc at 3MHz, 83dBc at 7MHz 77dB SFDR at 3MHz, V P-P Differential Output 6ns.% Settling Time for V Step Low Supply Current: 8mA per Ampifier Differential Gain of.%, Differential Phase of. 5dB Channel Separation at MHz Wide Supply Range: ±.5V (4.5V) to ±6.3V (.6V) 3mm 3mm 6-Pin QFN Package APPLICATIONS Differential ADC Driver Single-Ended to Differential Conversion Differential Video Line Driver 65MHz Differential ADC Driver/Dual Selectable Gain Amplifi er DESCRIPTION The LT 64 is a dual amplifi er with individually selectable gains of, and. The amplifiers have excellent distortion performance for driving ADCs as well as excellent bandwidth and slew rate for video, data transmission and other high speed applications. Single-ended to differential conversion with a system gain of is particularly straightforward by configuring one amplifi er with a gain of and the other amplifier with a gain of. The can be used on split supplies as large as ±6V and on a single supply as low as 4.5V. Each amplifier draws only 8mA of quiescent current when enabled. When disabled, the output pins become high impedance and each amplifi er draws less than 35µA. The is manufactured on Linear Technology s proprietary, low voltage, complimentary, bipolar process and is available in the ultra-compact, 3mm 3mm, 6pin QFN package., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION.9V DC.9V DC 3MHz INPUT EN 5V 37Ω 37Ω DGND Differential ADC Driver 37Ω 37Ω 4Ω 4Ω A IN LTC49 4-BIT ADC 8Msps A IN 64 TAa AMPLITUDE (dbfs) 3MHz -Tone 3768 Point FFT, Driving an LTC 49 4-Bit ADC POINT FFT TONE AT 9.5MHz, 7dBFS TONE AT 3.5MHz, 7dBFS IM3 = 87dBc TAb

2 ABSOLUTE MAXIMUM RATINGS (Note ) Total Supply Voltage ( to )...6V Input Current (Note )...±ma Output Current (Continuous)...±7mA EN to DGND Voltage (Note )...5.5V Output Short-Circuit Duration (Note 3)... Indefi nite Operating Temperature Range (Note 4)... 4 C to 85 C Specified Temperature Range (Note 5)... 4 C to 85 C Storage Temperature Range C to 5 C Junction Temperature... 5 C PACKAGE/ORDER INFORMATION 3 NC 4 TOP VIEW IN IN IN IN OUT VCC OUT UD PACKAGE 6-LEAD (3mm 3mm) PLASTIC QFN T JMAX = 5 C, θ JA = 68 C/W, θ JC = 4. C/W EXPOSED PAD (PIN 7) IS, MUST BE SOLDERED TO PCB ORDER PART NUMBER CUD IUD DGND EN 7 9 VCC UD PART MARKING* LCGP LCGP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at.,, R L = 5Ω, C L =.5pF, V EN =.4V, V DGND = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Referred Offset Voltage V IN = V, V OS = V OUT / 3 ± mv ± mv I IN Input Current 7 ±5 µa R IN Input Resistance V IN = ±V 5 5 kω C IN Input Capacitance f = khz pf R Maximum Input Common Mode Voltage Minimum Input Common Mode Voltage V V PSRR Power Supply Rejection Ratio V S (Total) = 4.5V to V (Note 6) 56 6 db I PSRR Input Current Power Supply Rejection V S (Total) = 4.5V to V (Note 6) ±4 µa/v A V ERR Gain Error V OUT = ±V. ±5 % A V MATCH Gain Matching V OUT = ±V ± % V OUT Maximum Output Voltage Swing R L = k R L = 5Ω R L = 5Ω I S Supply Current, Per Amplifi er Supply Current, Disabled, per Amplifi er V EN = 4V V EN = Open I EN Enable Pin Current V EN =.4V V EN = V ±3.7 ±3.5 ±3. ±3.95 ± V V V ma ma µa µa µa µa

3 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at.,, R L = 5Ω, C L =.5pF, V EN =.4V, V DGND = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I SC Output Short-Circuit Current R L = Ω, V IN = ±V ±5 ±5 ma SR Slew Rate ±V on ±V Output Step (Note 9) 7 33 V/µs 3dB BW Small-Signal 3dB Bandwidth V OUT = mv P-P, Single Ended 65 MHz.dB BW Gain Flatness ±.db Bandwidth V OUT = mv P-P, Single Ended MHz FPBW Full Power Bandwidth V Differential V OUT = V P-P Differential, 3dB 6 MHz Full Power Bandwidth V V OUT = V P-P (Note 7) 7 55 MHz Full Power Bandwidth 4V V OUT = 4V P-P (Note 7) 63 MHz All Hostile Crosstalk f = MHz, V OUT = V P-P f = MHz, V OUT = V P-P 75 5 db db t s Settling Time.% to V FINAL, V STEP = V 6 ns t r, t f Small-Signal Rise and Fall Time % to 9%, V OUT = mv P-P 55 ps dg Differential Gain (Note 8). % dp Diffierential Phase (Note 8). Deg The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. = 5V, = V,, No R LOAD, V EN =.4V, V DGND = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Noise/Harmonic Performance Input/Output Characteristics MHz Signal HD Second/Third Harmonic Distortion V P-P Differential V P-P Differential, R L = Ω Differential IMD3 M Third-Order IMD V P-P Differential Composite, f =.95MHz, f =.5MHz V P-P Differential Composite, f =.95MHz, f =.5MHz, R L = Ω Differential dbc dbc 93 dbc 9 dbc OIP3 M Output Third-Order Intercept Differential, f =.95MHz, f =.5MHz (Note ) 49.5 dbm NF Noise Figure Single Ended 5. db e nm Input Referred Noise Voltage Density 8 nv/ Hz PdB db Compression Point (Note ) 9.5 dbm MHz Signal HD Second/Third Harmonic Distortion V P-P Differential V P-P Differential, R L = Ω Differential IMD3 M Third-Order IMD V P-P Differential Composite, R L = k, f = 9.5MHz, f =.5MHz V P-P Differential Composite, f = 9.5MHz, f =.5MHz, R L = Ω Differential dbc dbc 9 dbc 89 dbc OIP3 M Output Third-Order Intercept Differential, f = 9.5MHz, f =.5MHz (Note ) 49 dbm NF Noise Figure Single Ended 4.7 db e nm Input Referred Noise Voltage Density 7.7 nv/ Hz PdB db Compression Point (Note ) 9.5 dbm 3

4 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. = 5V, = V,, No R LOAD, V EN =.4V, V DGND = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 3MHz Signal HD Second/Third Harmonic Distortion V P-P Differential V P-P Differential, R L = Ω Differential IMD3 3M Third-Order IMD V P-P Differential Composite, f = 9.5MHz, Differential, f = 3.5MHz V P-P Differential Composite, f = 9.5MHz, f = 3.5MHz, R L = Ω Differential dbc dbc 87 dbc 75 dbc OIP3 3M Output Third-Order Intercept Differential, f = 9.5MHz, f = 3.5MHz (Note ) 46.5 dbm NF Noise Figure Single Ended 4.6 db e n3m Input Referred Noise Voltage Density 7.6 nv/ Hz PdB db Compression Point (Note ) 9.5 dbm 7MHz Signal HD Second/Third Harmonic Distortion V P-P Differential V P-P Differential, R L = Ω Differential IMD3 7M Third-Order IMD V P-P Differential Composite, f = 69.5MHz, Differential, f = 7.5MHz V P-P Differential Composite, f = 69.5MHz, f = 7.5MHz, R L = Ω Differential 63 5 dbc dbc 83 dbc 64 dbc OIP3 7M Output Third-Order Intercept Differential, f = 69.5MHz, f = 7.5MHz (Note ) 44.5 dbm NF Noise Figure Single Ended 4.7 db e n7m Input Referred Noise Voltage Density 7.7 nv/ Hz PdB db Compression Point (Note ) 9.5 dbm Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : This parameter is guaranteed to meet specifi ed performance through design and characterization. It is not production tested. Note 3: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Depending on the supply voltage, a heat sink may be required. Note 4: The C is guaranteed functional over the operating temperature range of 4 C to 85 C. Note 5: The C is guaranteed to meet specifi ed performance from C to 7 C. The C is designed, characterized and expected to meet specified performance from 4 C and 85 C but is not tested or QA sampled at these temperatures. The I is guaranteed to meet specified performance from 4 C to 85 C. Note 6: The two supply voltage settings for power supply rejection are shifted from the typical ±V S points for ease of testing. The fi rst measurement is taken at = 3V, =.5V to provide the required 3V headroom for the enable circuitry to function with EN, DGND and all inputs connected to V. The second measurement is taken at = 8V, = 4V. Note 7: Full power bandwidth is calculated from the slew rate: FPBW = SR/(π V P-P ) Note 8: Differential gain and phase are measured using a Tektronix TSGYC/NTSC signal generator and a Tektronix 78R video measurement set. The resolution of this equipment is better than.5% and.5. Ten identical amplifi er stages were cascaded giving an effective resolution of better than.5% and.5. Note 9: Slew rate is % production tested on channel. Slew rate of channel is guaranteed through design and characterization. Note : Since the is a feedback amplifi er with low output impedance, a resistive load is not required when driving an ADC. Therefore, typical output power is very small. In order to compare the with typical g m amplifi ers that require 5Ω output loading, the output voltage swing driving an ADC is converted to OIP3 and PdB as if it were driving a 5Ω load. 4

5 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifi er with single-ended outputs unless otherwise noted. Supply Current per Amplifi er vs Temperature R L = V IN, VIN = V Supply Current per Ampifi er vs Supply Voltage = V EN, V DGND, V IN, VIN = V Supply Current per Amplifi er vs EN Pin Voltage T A = 55 C V DGND = V V IN, VIN = V SUPPLY CURRENT (ma) V EN = V V EN =.4V SUPPLY CURRENT (ma) SUPPLY CURRENT (ma) T A = 5 C TEMPERATURE ( C) 64 G TOTAL SUPPLY VOLTAGE (V) 64 G EN PIN VOLTAGE (V) 64 G3 OFFSET VOLTAGE (mv) Output Offset Voltage vs Temperature V IN = V IN BIAS CURRENT (µa) 4 Positive Input Bias Current vs Input Voltage T A = 5 C T A = 55 C EN PIN CURRENT (µa) EN Pin Current vs EN Pin Voltage V DGND = V T A = 5 C T A = 55 C TEMPERATURE ( C) INPUT VOLTAGE (V) EN PIN VOLTAGE (V) 64 G4 64 G5 64 G6 Output Voltage vs Input Voltage Output Voltage Swing vs I LOAD (Output High) Output Voltage Swing vs I LOAD (Output Low) R L = k A V = 5 4 V IN = V V IN = V OUTPUT VOLTAGE (V) T A = 55 C OUTPUT VOLTAGE (V) 3 T A = 55 C T A = 5 C OUTPUT VOLTAGE (V) 3 T A = 55 C T A = 5 C T A = 5 C INPUT VOLTAGE (V) SOURCE CURRENT (ma) SINK CURRENT (ma) 64 G7 64 G8 64 G9 5

6 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifi er with single-ended outputs unless otherwise noted. INPUT NOISE (nv/ Hz OR pa/ Hz) Input Noise Spectral Density i n e n INPUT IMPEDANCE (kω) Positive Input Impedance vs Frequency V IN = V REJECTION RATIO (db) PSRR vs Frequency ±PSRR PSRR PSRR... FREQUENCY (khz) G 64 G 64 G GAIN (db) 9 6 Frequency Response vs Gain Confi guration, V OUT = V P-P, V OUT = mv P-P 3 A V =, A V =,V OUT = mv P-P A V =, V OUT = V P-P 3 A V =, V OUT = V P-P R L = 5Ω 6. NORMALIZED GAIN (db) Gain Flatness vs Frequency V OUT = mv P-P R L = 5Ω CHANNEL CHANNEL 5.5. AMPLITUDE (db) Frequency Response with Capacitive Loads V OUT = V P-P R L = 5Ω C L = 6.8pF C L =.pf C L = pf G3 64 G G5 DISTORTION (dbc) Harmonic Distortion vs Frequency, Differential Input V OUT = V P-P, DIFFERENTIAL, = 5V = V, =.6V DIFFERENTIAL R LOAD HD, R L = Ω HD3, R L = Ω HD3, R L = HD, R L = 64 G6 DISTORTION (dbc) Harmonic Distortion vs Amplitude, 3MHz, Differential Input, = 5V = V, =.6V R L = HD3 HD DIFFERENTIAL OUTPUT AMPLITUDE (V P-P ) 64 G7 DISTORTION (dbc) Harmonic Distortion vs Load, 3MHz, Differential Input V OUT = V P-P, DIFFERENTIAL, = 5V = V, =.6V HD3 8 HD DIFFERENTIAL R LOAD (Ω) G6 6

7 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifi er with single-ended outputs unless otherwise noted. THIRD ORDER IMD (dbc) Third Order Intermodulation Distortion vs Frequency, Differential Input V OUT = V P-P, COMPOSITE, DIFFERENTIAL MHz TONE SPACING, = 5V = V, =.6V DIFFERENTIAL R LOAD R L = Ω R L = OIP3 (dbm) Output Third Order Intercept vs Frequency, Differential Input R L = COMPUTED FOR 5Ω ENVIRONMENT R L = Ω V OUT = V P-P, COMPOSITE, DIFFERENTIAL MHz TONE SPACING, = 5V = V, =.6V DIFFERENTIAL R LOAD OUTPUT IMPEDANCE (Ω).. Output Impedance vs Frequency DISABLED V EN = 4V ENABLED V EN =.4V R L = 5Ω. 64 G9 64 G 64 G OUTPUT (V) Small-Signal Transient Response V IN = mv P-P R L = 5Ω OUTPUT (V) Video Amplitude Transient Response V IN = 7mV P-P R L = 5Ω OUTPUT (V) Large-Signal Transient Response V IN =.5V P-P R L = 5Ω TIME (ns) TIME (ns) TIME (ns) 64 G 64 G3 64 G4 AMPLITUDE (db) Crosstalk vs Frequency Gain Error Distribution Gain Matching Distribution V OUT = V P-P R L = 5Ω DRIVE LISTEN DRIVE LISTEN PERCENT OF UNITS (%) V OUT = ±V R L = 5Ω PERCENT OF UNITS (%) V OUT = ±V R L = 5Ω GAIN ERRORINDIVIDUAL CHANNEL (%) GAIN MATCHINGBETWEEN CHANNELS (%) 635 G5 64 G6 64 G7 7

8 PIN FUNCTIONS (Pins, ): Negative Supply Voltage. pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. (Pins 3, 7): Negative Supply Voltage for Output Stage. pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. NC (Pin 4): This pin is not internally connected. OUT (Pin 5): Output of Channel. The gain between the input and the output of this channel is set by the connection of the channel input pins. See Table in Applications Information for details. (Pins 6, 9): Positive Supply Voltage for Output Stage. pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUT (Pin 8): Output of Channel. The gain between the input and the output of this channel is set by the connection of the channel input pins. See Table in Applications Information for details. (Pin ): Positive Supply Voltage. pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. EN (Pin ): Enable Control Pin. An internal pull-up resistor of 46k will turn the part off if the pin is allowed to fl oat and defines the pin s impedance. When the pin is pulled low, the part is enabled. DGND (Pin ): Digital Ground Reference for Enable Pin. This pin is normally connected to ground. IN (Pin 3): Channel Positive Input. This pin has a nominal impedance of 4kΩ and does not have an internal termination resistor. IN (Pin 4): This pin connects to the internal resistor network of the channel amplifier, connecting by a 37Ω resistor to the inverting input. IN (Pin 5): This pin connects to the internal resistor network of the channel amplifier, connecting by a 37Ω resistor to the inverting input. IN (Pin 6): Channel Positive Input. This pin has a nominal impedance of 4kΩ and does not have an internal termination resistor. Exposed Pad (Pin 7): The pad is internally connected to (Pin ). If split supplies are used, do not tie the pad to ground. 8

9 APPLICATIONS INFORMATION Power Supplies The can be operated on as little as ±.5V or a single 4.5V supply and as much as ±6V or a single V supply. Internally, each supply is independent to improve channel isolation. Note that the Exposed Pad is internally connected to and must not be grounded when using split supplies. Do not leave any supply pins disconnected or the part may not function correctly! Enable/Shutdown The has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above V or allowing the internal 46k pull-up resistor to pull the EN pin to the top rail will disable the amplifier. When disabled, the DC output impedance will rise to approximately 74Ω through the internal feedback and gain resistors (assuming inputs at ground). Supply current into the amplifier in the disabled state will be primarily through and approximately equal to ( V EN )/46k. It is important that the two following constraints on the DGND pin and the EN pin are always followed: V DGND 3V.5V V EN V DGND 5.5V Split supplies of ±3V to ±5.5V will satisfy these requirements with DGND connected to V. In dual supply cases with less than 3V, DGND should be connected to a potential below ground such as. V V Since the EN pin is referenced to DGND, it may need to be pulled below ground in those cases. In order to protect the internal enable circuitry, the EN pin should not be forced more than.5v below DGND. In single supply applications above 5.5V, an additional resistor may be needed from the EN pin to DGND if the pin is ever allowed to fl oat. For example, on a V single supply, a 33k resistor would protect the pin from fl oating too high while still allowing the internal pull-up resistor to disable the part. The DGND pin should not be pulled above the EN pin since doing so will turn on an ESD protection diode. If the EN pin voltage is forced a diode drop below the DGND pin, current should be limited to ma or less. The enable/disable times of the are fast when driven with a logic input. Turn on (from 5% EN input to 5% output) typically occurs in less than 5ns. Turn off is slower, but is less than 3ns. Gain Selection The gain of the internal amplifiers of the is confi g- ured by connecting the IN and IN pins to the input signal or ground in the combinations shown in Figure. As shown in the Simplified Schematic, the IN pins connect to the internal gain resistor of each amplifier, and therefore, each pin can be configured independently. Floating the IN pins is not recommended as the parasitic capacitance causes an AC gain of at high frequencies, despite a DC gain of. Both inputs are connected together in the gain of confi guration to avoid this limitation. V IN OUT A V = IN OUT A V = IN OUT IN OUT IN OUT IN OUT 64 F V V V Figure. Confi gured in Noninverting Gain of, Noninverting Gain of and Inverting Gain of, All Shown with Dual Supplies 9

10 APPLICATIONS INFORMATION Input Considerations The input voltage range is from V to V. Therefore, on split supplies the input range is always as large as or larger than the output swing. On a single positive supply with a gain of and IN connected to ground, however, the input range limit of V limits the linear output low swing to V (V multiplied by the internal gain of ). The inputs can be driven beyond the point at which the output clips so long as input currents are limited to ±ma. Continuing to drive the input beyond the output limit can result in increased current drive and slightly increased swing, but will also increase supply current and may result in delays in transient response at larger levels of overdrive. DC Biasing Differential Amplifier Applications The inputs of the must be DC biased within the input common mode voltage range, typically V to V. If the inputs are AC coupled or DC biased beyond the input voltage range of a driven A-to-D converter, DC biasing or level shifting will be required. In the basic circuit configurations shown in Figure, the DC input common mode voltage and the differential input signal are both multiplied by the amplifier gain. In the gain of configuration, the DC common mode voltage gain can be set to unity by adding a capacitor at the IN pins as shown in Figure. If the inputs are AC coupled or the is preceded by a highpass filter, the input common mode voltage can be set by resistor dividers as shown in Figure 3. Adding V DC V DC IN C LARGE IN V 64 F OUT OUT Figure. Confi gured with a Differential Gain of and Unity DC Common Mode Gain V DC V DC the blocking capacitor to the gain setting resistors sets the input and output DC common mode voltages equal. When using the to drive an A-to-D converter, the DC common mode voltage level will affect the harmonic distortion of the combined amplifier/adc system. Figure 4 shows the measured distortion of an LTC49 ADC when driven by the at different common mode voltage levels with the inputs confi gured as shown in Figure 3. Adjusting the DC bias voltage can optimize the design for the lowest possible distortion. If the input signals are within the input voltage range and output swing of the, but outside the input range of an ADC or other circuit the is driving, OV OV IN IN C LARGE C LARGE V R V R R R V DC V DC V 64 F3 Figure 3. Using Resistor Dividers to Set the Input Common Mode Voltage When AC Coupling DISTORTION (dbc) = 5V, = V HD3 IM3 85 HD (V) 64 F4 OUT OUT Figure 4. Harmonic and Intermodulation Distortion of the Driving an LTC49 Versus DC Common Mode Voltage. Harmonic Distortion Measured with a dbfs Signal at 3.MHz. Intermodulation Distortion Measured with Two 7dBFS Tones at 3.MHz and 9.MHz VDC V DC

11 APPLICATIONS INFORMATION the output signals can be AC coupled and DC biased in a manner similar to what is shown at the inputs in Figure 3. A simpler alternative when using an ADC such as the LTC49 is to use the ADC s pin to set the optimal common mode voltage as shown in Figure 5. If unity common mode gain and difference mode response to DC is desired, there is another configuration available. Figure 6 shows the connected to provide a differential signal gain of 3 with unity common mode gain. For differential signal gain between unity and 3, three resistors can be added to provide attenuation and set the differential input impedance of the stage as illustrated in Figure 7. The general expression for the differential gain is: A VDIFF ( ) k = k Scaling factor k is the multiple between the two equalvalue series input resistors and the resistor connected between the two positive inputs. The correct value of R for the external resistors can be computed from the desired differential input impedance, Z IN, as a function of k and the 37Ω internal gain setting resistors, as described in the equation: Z R IN 37Ω = 37Ω k Z k ( ) ( ) IN IN IN V 64 F6 OUT OUT Figure 6. Confi gured for a Differential Gain of 3 and Unity Common Mode Gain with Response to DC IN IN R = 3.7Ω k R = 7.4Ω R = 3.7Ω V 64 F7 OUT OUT Figure 7. Confi gured with a Differential Input Impedance of 5Ω, a Differential Gain of and Unity Common Mode Gain In Figure 7 k = and R = 3.7Ω, setting the differential gain to and the differential input impedance to approximately 5Ω. V OV IN C LARGE k LTC49 IN C LARGE OV k.µf V Figure 5. Level Shifting the Output Common Mode Voltage of the Using the Pin of an LTC49 64 F5

12 APPLICATIONS INFORMATION Layout and Grounding It is imperative that care is taken in PCB layout in order to utilize the very high speed and very low crosstalk of the. Separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. If input or output traces must be run over a distance of several centimeters, they should use a controlled impedance with matching series and shunt resistances to maintain signal fidelity. Series termination resistors should be placed as close to the output pins as possible to minimize output capacitance. See the Typical Performance Characteristics section for a plot of frequency response with various output capacitors only pf of parasitic output capacitance causes 6dB of peaking in the frequency response! Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One 47pF ceramic capacitor is recommended for both and. Additional 47pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high current drive and large-signal transient applications, additional µf to µf tantalums should be added on each supply. The smallest value capacitors should be placed closest to the package. If the undriven input pins are not connected directly to a low impedance ground plane, they must be carefully bypassed to maintain minimal impedance over frequency. Although crosstalk will be very dependent on the board layout, a recommended starting point for bypass capacitors would be 47pF as close as possible to each input pin with one 47pF capacitor in parallel. To maintain the s channel isolation, it is beneficial to shield parallel input and output traces using a ground plane or power supply traces. Vias between topside and backside metal may be required to maintain a low inductance ground near the part where numerous traces converge. ESD Protection The has reverse-biased ESD protection diodes on all pins. If any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may fl ow through these diodes. If the current is kept below ma, no damage to the devices will occur. TYPICAL APPLICATIONS Single-Ended to Differential Converter Because the gains of each channel of the can be configured independently, the can be used to provide a gain of when amplifying differential signals and when converting single-ended signals to differential. With both channels connected to a single-ended input, one channel configured with a gain of and the other configured with a gain of, the output will be a differential version of the input with twice the peak-to-peak (differential) amplitude. Figure 8 shows the proper connections and Figure 9 displays the resulting performance when driving an LTC49. This configuration can preserve signal amplitude when converting single ended video signals to differential signals when driving double terminated cables. The k resistors in Figure 8 set the common mode voltage at the output. INPUT.µF µf 5V k k IN IN IN IN 5V 37Ω 37Ω 37Ω 37Ω DGND EN 64 F8 OUT OUT Figure 8. Single-Ended to Differential Converter with Gain of and Common Mode Control OUT OUT

13 TYPICAL APPLICATIONS AMPLITUDE (dbfs) POINT FFT TONE AT 9.5MHz, 7dBFS TONE AT 3.5MHz, 7dBFS IM3 = 9dBc F9 Figure 9. -Tone Response of the Confi gured with Single-Ended Inputs Driving the LTC49 at 9.5MHz, 3.5MHz Twisted-Pair Line Driver The is ideal when used for driving inexpensive unshielded twisted-pair wires as often found in telephone or communications infrastructure. The input can be composite video, or if three parts are used, RGB or similar and can be either single ended or differential. The has excellent performance with all formats. Double termination of the video cable will enhance fidelity and isolate the from capacitive loads. Although most twisted-pair cables have a characteristic impedance IN IN , 5V 6,9, 5V 5 5Ω 5Ω Figure. Twisted-Pair Driver Ω RECEIVER,,3,7 64 F of Ω, the cables can be terminated with a smaller series resistance or a larger shunt resistance in order to compensate for attenuation. A typical circuit for a twistedpair driver is shown in Figure. Single Supply Differential ADC Driver The is well suited for driving differential analog to digital converters. The low output impedance of the is capable of driving a variety of fi lters as well as interfacing with the typically high impedance inputs of ADCs. In addition, the s excellent distortion allows the part to perform with an SFDR below the limits of many high speed ADCs. The DC57 demo board, shown schematically in Figure and physically in Figure, allows implementation and testing of the with a variety of different Linear Technology high speed ADCs. 3

14 TYPICAL APPLICATIONS C D.µF C D 47pF C OPT B CASE E E GND J A IN J A IN R6 TBD 63 R6 Ω R4 OPT 63 T ETC-TTR R38 OPT R37 OPT R7 C8 TBD 63 R3 C C5 C C3 C9 C R7 OPT R OPT R3 R5 R R4 R8 C D5 47pF C D3 47pF C D4.µF IN EN DGND OUT 8 4 IN V 5 EE IN 6 IN OUT 5 NC C D6 C D7 47pF µf R Ω 63 JP ENABLE 3 R8 Ω % R Ω % C D8.µF 63 C6 L TBD 63 R9 Ω % L TBD R 63 Ω % L3 TBD 63 R9 Ω C4 C7 R35.Ω % R36.Ω % C C3 OPT B CASE TO ADC INPUTS A IN 64 F A IN E7 OPT E8 GND Figure. DC57 Demo Circuit Schematic 4 Figure. Layout of DC57 Demo Circuit

15 SIMPLIFIED SCHEMATIC BIAS TO OTHER AMPLIFIER IN 37Ω EN k 46k IN 5Ω 37Ω OUT DGND 64 SS PACKAGE DESCRIPTION UD Package 6-Lead Plastic QFN (3mm 3mm) (Reference LTC DWG # ) BOTTOM VIEW EXPOSED PAD.7 ±.5 3. ±. (4 SIDES) PIN TOP MARK (NOTE 6).75 ±.5 R =.5 TYP 5 6 PIN NOTCH R =. TYP OR.5 45 CHAMFER.4 ±. 3.5 ±.5.45 ±.5. ±.5 (4 SIDES).45 ±. (4-SIDES) PACKAGE OUTLINE.5 ±.5.5 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE:. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO- VARIATION (WEED-). DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.5mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE. REF..5 (UD6) QFN 94.5 ±.5.5 BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5

16 TYPICAL APPLICATION In cases where lowering the noise floor is paramount, adding higher order lowpass or bandpass filtering can significantly increase signal-to-noise ratio. In Figure 3, the is shown driving an LTC49 with a nd order lowpass filter that has been carefully chosen to ensure optimal intermodulation distortion. The response is shown in Figure 4. The filter improves the SNR over the unfiltered case by 6dB to 69.5dB. With the filter, the SNR of the ADC and the are comparable; better SNR can be achieved by using either a higher resolution ADC.9V DC.9V DC IN IN 5V 55Ω 55Ω 8.6Ω 39nH 5pF 39nH 8.6Ω LTC49 Figure 3. Optimized 3MHz Differential ADC Driver Ω Ω A IN A IN 64 F3 or additional filtering. Figure 5 shows the corresponding SFDR of 75.5dBc with a 3MHz tone. Figure 6 shows the -tone response of the with 9.5MHz and 3.5MHz inputs. Note that dbfs corresponds to a V P-P differential signal. GAIN (db) F4 Figure 4. Frequency Response of the and Filter AMPLITUDE (dbfs) POINT FFT f IN = 3MHz, dbfs SNR = 69.5dB SFDR = 75.5dB F5 AMPLITUDE (dbfs) POINT FFT TONE AT 9.5MHz, 7dBFS TONE AT 3.5MHz, 7dBFS IM3 = 89.7dBc F6 Figure 5. SNR and SFDR of the and Filter Driving the LTC49 Figure 6. -Tone Response of the and Filter Driving the LTC49 at 9.5MHz, 3.5MHz RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT993-8MHz Low Distortion, Low Noise ADC Driver, 3.8nV/ Hz Total Noise, Low Distortion to MHz LT MHz Low Distortion, Low Noise ADC Driver, A V = 4.4nV/ Hz Total Noise, Low Distortion to MHz LT993-7MHz Low Distortion, Low Noise ADC Driver, A V =.9nV/ Hz Total Noise, Low Distortion to MHz LT994 Low Noise, Low Distortion Fully Differential Amplfi er 7MHz Gain Bandwidth Differential In and Out LT64-6 3MHz Low Distortion, Low Noise ADC Driver, 3.8nV/ Hz Input Referred Noise, Low Distortion to 3MHz LT MHz Gain of Triple Video Amplifi er Triple Amplifi er with Fixed Gain LT MHz Gain of Triple Video Amplifi er Triple Amplifi er with Fixed Gain 6 LT 66 PRINTED IN USA Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA (48) 43-9 FAX: (48) LINEAR TECHNOLOGY CORPORATION 6