FEATURES TYPICAL APPLICATIO. LTC1164 Low Power, Low Noise, Quad Universal Filter Building Block DESCRIPTIO APPLICATIO S

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1 FEATRES Low Power 4 Filters in a.3" Wide Package / the Noise o the LTC59, 6, 6 Devices Wide Output Swing Clock-to-Center Frequency Ratios o 5: and : Operates rom ±.37V to ±8V Power Supplies Customized Version with Internal Resistors Available Ratio o 5: and : Simultaneously Available APPLICATIO S Antialiasing Filters Telecom Filters Spectral Analysis Loop Filters For Fixed Lowpass Filter Requirements use the LTC64-XX Series, LTC and LT are registered trademarks o Linear Technology Corporation. LTCMOS trademark o Linear Technology Corporation. LTC64 Low Power, Low Noise, Quad niversal Filter Building Block DESCRIPTIO The LTC 64 consists o our low power, low noise nd order switched capacitor ilter building blocks. Each building block typically consumes 85µA supply current. Low power is achieved without sacriicing noise and distortion. Each building block, together with 3 to 5 resistors, can provide nd order unctions like lowpass, highpass, bandpass, and notch. The center requency o each nd order section can be tuned with an external clock, or a clock and resistor ratio. For Q < 5, the center requency range is rom.hz to khz. p to 8th order ilters can be realized by cascading all our nd order sections. Any classical ilter realization (such as Butterworth, Cauer, Bessel, and Chebyshev) can be ormed. A customized monolithic version o the LTC64 including internal thin ilm resistors can be obtained. Consult LTC Marketing or details. The LTC64 is manuactured using Linear Technology s enhanced LTCMOS silicon gate process. TYPICAL APPLICATIO V Dual 5th Order Linear Phase Filter with Stopband Notch k k k 74k 33k 74k 33k k C =.33µF C =.68µF CLK = 5kHz WIDEBAND NOISE = 5µV RMS TOTAL SPPLY CRRENT = 3mA ALL RESISTORS ARE % METAL FILM LTC k 49.9k 78.7k CLK 78.7k 49.9k 549k 63.4k 36.5k 8.66k 8.66k 36.5k 63.4k C V V OT V OT C LTC64 TA GAIN (db) Dual 5th Order Linear Phase Filter with Stopband Notch, CLK = 5kHz k V OT V OT k FREQENCY (Hz) k LTC64 TA SPPLY TOTAL VOLTAGE HARMONIC DISTORTION SIGNAL/NOISE ±.5 V RMS.5% (76dB) 86dB ±5. V RMS.5% (7dB) 9dB ±7.5 4V RMS.4% (68dB) 98dB

2 ABSOLTE AXI RATI GS W W W Total Supply Voltage (V to V ) V Power Dissipation... 5mW Storage Temperature Range...65 C to 5 C Lead Temperature (Soldering, sec)... 3 C (Note ) Operating Temperature Range LTC64AM, LTC64M (OBSOLETE) C to 5 C LTC64AC, LTC64C...4 C to 85 C W PACKAGE/ORDER I FOR ATIO INV B HPB/NB BPB 3 LPB 4 SB 5 AGND 6 V 7 SA 8 LPA 9 BPA HPA INV A TOP VIEW N PACKAGE 4-LEAD PDIP T JMAX = C, θ JA = 65 C/W 4 INV C 3 HPC/NC BPC LPC SC 9 V 8 CLK 7 5/ 6 LPD 5 BPD 4 HPD 3 INV D J PACKAGE 4-LEAD CERDIP T JMAX = 5 C, θ JA = C/W OBSOLETE PACKAGE Consider the N4 Package as an Alternate Source ORDER PART NMBER LTC64ACN LTC64CN LTC64AMJ LTC64MJ LTC64ACJ LTC64CJ Consult LTC Marketing or parts speciied with wider operating temperature ranges. INV B HPB/NB BPB 3 LPB 4 SB 5 AGND 6 V 7 SA 8 LPA 9 BPA HPA INV A TOP VIEW SW PACKAGE 4-LEAD PLASTIC SO T JMAX = C, θ JA = 75 C/W 4 INV C 3 HPC/NC BPC LPC SC 9 V 8 CLK 7 5/ 6 LPD 5 BPD 4 HPD 3 INV D ORDER PART NMBER LTC64CSW LTC64ACSW LTC/ POI ELECTRICAL CHARACTERISTICS The denotes speciications which apply over the ull operating temperature range, otherwise speciications are at T A = 5 C. (Internal Op Amps) V S = ±5V, = 5kΩ unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX NITS Supply Voltage Range ±.37 ±8 V Voltage Swings V S = ±.5V ±.6 V V S = ±5.V ±3.8 ±4. V ±6. V Output Short Circuit Current (Source/Sink) V S = ±5.V ma DC Open Loop Gain V S = ±5.V 8 db GBW Product V S = ±5.V MHz Slew Rate V S = ±5.V.6 V/µs

3 ELECTRICAL CHARACTERISTICS LTC64 The denotes speciications which apply over the ull operating temperature range,otherwise speciications are at T A = 5 C. (Complete Filter) V S = ±5V, TTL Clock Input Level, unless otherwise speciied. PARAMETER CONDITIONS MIN TYP MAX NITS Center Frequency Range. to k Hz Input Frequency Range (Note ) 5: < CLK Hz : < CLK / Hz Clock-to-Center Frequency Ratio, CLK / O Sides A, B, C: Mode, = = 5k, = 5k, Side D: Mode 3, = = 5k, = = 5k O = 5kHz, Q = LTC64A 5:, CLK = 5kHz 5 ±.5 % LTC64 5:, CLK = 5kHz 5 ±.9 % LTC64A :, CLK = 5kHz ±.5 % LTC64 :, CLK = 5kHz ±.9 % Clock-to-Center Frequency Ratio, Sides A, B, C, Mode, O = 5kHz, Q = Side to Side Matching Side D Mode 3, O = 5kHz, Q = LTC64A 5:, CLK = 5kHz.5 % LTC64 5:, CLK = 5kHz. % Q Accuracy Sides A, B, C, Mode, O = 5kHz, Q = 5:, CLK = 5kHz ± ±5 % :, CLK = 5kHz ± ±5 % Side D Mode 3, O = 5kHz, Q = 5:, CLK = 5kHz ±3 ±6 % :, CLK = 5kHz ±6 ± % O Temperature Coeicient CLK 5kHz ± ppm/ C Q Temperature Coeicient CLK 5kHz ±5 ppm/ C Maximum Clock Frequency Mode, Q <.5 V S ±7.V, 5: or :.5 MHz Mode 3, Q < 5 V S ±5V, 5: or :. MHz Mode 3, Q < 5 V S = ±.5V, 5: or : 5 khz CLK Feedthrough CLK 5kHz, V S = ±5V µv RMS DC Oset Voltages V OS mv (See Figure and Table ) V OS 3 45 mv V OS mv Power Supply Current V S = ±.5V 4 ma Note : Absolute Maximum Ratings are those values beyond which the lie o a device may be impaired. Note: : Guaranteed by design. Not tested. V S = ±5V, Temp 5 C ma V S = ±5V ma, Temp 5 C 6 8 ma 9 ma 3

4 ELECTRICAL CHARACTERISTICS (, 3, 4) V OS (, 4, 3) (, 5, ) 3 V OS Σ V OS3 5 (8, ) (9, 6, ) 4 6 LTC64 BD Figure. Equivalent Input Osets o /4 LTC64 Filter Building Block Table. Output DC Osets One nd Order Section V OSN V OSBP V OSLP MODE PIN,, 4, 3 PINS 3,, 5, PINS 4, 9, 6, V OS [(/Q) H OLP ] V S3 /Q V OS3 V OSN V OS b V OS [(/Q) /] V S3 /Q V OS3 ~ (V OSN V OS ) ( R5/R6) [V OS ( / / /) V S3 (/)] V OS3 V OSN V OS [/( )] V S [/( )] [ ] 3 V S V OS3 V OS V OS V OS3 ( ) ( ) 4

5 BLOCK DIAGRA W HPA/NA() BPA() LPA(9) V (7) INV A() AGND(6) Σ HPB/NB() SA(8) BPB(3) LPB(4) 5/(7) CLK(8) INV B() Σ V (9) HPC/NC(3) SB(5) BPC() LPC() INV C(4) Σ INV D(3) HPD(4) SC() BPD(5) LPD(6) BY TYING PIN 7 TO V ALL SECTIONS OPERATE WITH ( CLK / O ) = (5:) BY TYING PIN 7 TO V ALL SECTIONS OPERATE WITH ( CLK / O ) = (:) BY TYING PIN 7 TO AGND SECTIONS A & D OPERATE WITH ( CLK / O ) = (:) AND SECTIONS B & C OPERATE AT (5:) LTC64 BD 5

6 TYPICAL PERFOR A CE CHARACTERISTICS O ERROR (%) Q ERROR (%) W Mode, ( CLK / O ) = 5: Mode, ( CLK / O ) = : Mode 3, ( CLK / O ) = 5: T A = 5 C V S = ±.5V V S = ±.5V CENTER FREQENCY, O (khz) O ERROR (%) Q ERROR (%) T A = 5 C V S = ±.5V V S = ±.5V CENTER FREQENCY, O (khz) O ERROR (%) Q ERROR (%) V S = ±.5V T A = 5 C V S = ±.5V.5 V.5 S = ±7.5V CENTER FREQENCY, O (khz) LTC64 TPC LTC64 TPC LTC64 TPC3 O ERROR (%) Q ERROR (%) Mode 3, ( CLK / O ) = : Mode 3 Q Error vs Ideal Q Wideband Noise vs Q V S = ±.5V T A = 5 C.5 V S = ±.5V CENTER FREQENCY, O (khz) Q ERROR (%) T A = 5 C V S = ±5V 9 5: : 5: CLK = khz : CLK = 4kHz IDEAL Q WIDEBAND NOISE (µv RMS ) ONE SECOND ORDER SECTION LP OR BP OTPT MODE,, OR 3 : OR 5: ±7.5V ±5.V ±.5V Q LTC64 TPC4 LTC64 TPC5 LTC64 TPC6 Total Harmonic Distortion vs Output Amplitude V S = ±.5V 8. Power Supply Current vs Voltage CLK 5kHz THD N (%).. V S = ±5V IN = khz CLK = 5kHz 5: = = = = 5k AMPLITDE (V RMS ) LTC64 TPC7 POWER SPPLY CRRENT (ma) C C 3. 5 C.6. ±.5 ±3.5 ±4.5 ±5.5 ±6.5 ±7.5 ±V SPPLY (V) LTC64 TPC8 6

7 PI F CTIO S Power Supplies (Pins 7,9) They should be bypassed with ceramic disc. Low noise, non-switching, power supplies are recommended. The device operates with a single 5V supply and with dual supplies. The absolute maximum operating power supply voltage is ±8.5V. Supply reversal is not allowed and can cause latch up. When using dual supplies, loads between the positive and negative supply (even light loads) can cause momentary supply reversal during power-up. A clamp diode rom each supply to ground will prevent reversal and latch problems. Clock (Pin 8) For ±5V supplies the logic threshold level is.8v. For ±8V and to 5V supplies the logic threshold level is.8v. The logic threshold levels vary ±mv over the ull military temperature range. The recommended duty cycle o the input clock is 5%, although or clock requencies below 5kHz the clock on time can be as low as ns. The maximum clock requency or single 5V supply and Q values <5 is 5kHz and or ±5V supplies and above is MHz. The clock input can be applied beore power is turned on as long as there is no chance the clock signal will go below the V supply. AGND (PIN 6) When the LTC64 operates with dual supplies, Pin 6 should be tied to system ground. When the LTC64 operates with a single positive supply, the analog ground pin should be tied to / supply and it should be bypassed with a 4.7µF solid tantalum in parallel with a ceramic disc, Figure. The positive input o all the internal op amps, as well as the common reerence o all the internal switches, are internally tied to the analog ground pin. Because o this, a very clean ground is recommended. 5/ (Pin 7) By tying Pin 7 to V, all ilter sections operate with a clockto-center requency ratio internally set at 5:. When Pin 7 is at mid-supplies, sections B and C operate with ( CLK / O ) = 5: and sections A and D operate at (:). When Pin 7 is shorted to the negative supply pin, all ilter sections operate with ( CLK / O ) = : LTC64 5 V / 6 AGND V 9 7 V CLK 8 8 5/ µF V 7.5k ANALOG GROND PLANE LT4* CLOCK INPT V = 5V, TRIP VOLTAGE = 7V V = V, TRIP VOLTAGE = 6.4V V = 5V, TRIP VOLTAGE = 3V TO DIGITAL GROND NOTE: PIN 5, 8,, IF NOT SED, SHOLD BE CONNECTED TO PIN 6. *LT4 CAN BE REPLACED WITH A 7.5k RESISTOR FOR V >6.5V LTC64 PD Figure. Single Supply Operation 7

8 APPLICATIO S I FOR ATIO ANALOG CONSIDERATIONS W. Grounding and Bypassing The LTC64 should be used with separated analog and digital ground planes and single point grounding techniques. Pin 6 (AGND) should be tied directly to the analog ground plane. Pin 7 (V ) should be bypassed to the ground plane with a ceramic disk with leads as short as possible. Pin 9 (V ) should be bypassed with a ceramic disk. For single supply applications, V can be tied to the analog ground plane. For good noise perormance, V and V must be ree o noise and ripple. All analog inputs should be reerenced directly to the single point ground. The clock inputs should be shielded rom and/or routed away rom the analog circuitry and a separate digital ground plane used. Figure 3 shows an example o an ideal ground plane design or a two sided board. O course this much ground plane will not always be possible, but users should strive to get as close to this as possible. Proto boards are not recommended.. Buering the Filter Output When driving coaxial cables and x scope probes, the ilter output should be buered. This is important especially when high Qs are used to design a speciic ilter. Inadequate buering may cause errors in noise, distortion, Q, and gain measurements. When x probes are used, buering is usually not required. A buer is recommended especially when THD tests are perormed. As shown in Figure 4, the buer should be adequately bypassed to minimize clock eedthrough. PIN DENT FOR BEST HIGH FREQENCY RESPONSE PLACE RESISTORS PARALLEL TO DOBLE SIDED COPPER CLAD BOARD AND LAY FLAT (4 RESISTORS SHOWN HERE TYPICAL) 5 7.5V CERAMIC DISK V 7 8 CLOCK CERAMIC DISK DIGITAL GROND PLANE (SINGLE POINT GROND) ANALOG GROND PLANE 4 3 NOTE: CONNECT ANALOG AND DIGITAL GROND PLANES AT A SINGLE POINT AT THE BOARD EDGE LTC64 AI Figure 3. Example Ground Plane Breadboard Technique or LTC64 8

9 APPLICATIO S I FOR ATIO W 3. Oset Nulling Lowpass ilters may have too much DC oset or some users. A servo circuit may be used to actively null the osets o the LTC64 or any LTC switched capacitor ilter. The circuit shown in Figure 5 will null osets to better than 3µV. This circuit takes seconds to settle because o the integrator pole requency. 4. Noise All the noise perormance mentioned excludes the clock eedthrough. Noise measurements will degrade i the already described grounding, bypassing, and buering techniques are not practiced. The Wideband Noise vs Q curve shown in the Typical Perormance Characteristics Section is a very good representation o the noise perormance o this device. V TRACE FOR FILTER POSITIVE SPPLY SEPARATE V POWER SPPLY TRACE FOR BFFER 7 LTC64 9 k 4 7 µf T A TO FILTER FIRST SMMING NODE k LT FROM FILTER OTPT M C NEGATIVE SPPLY µf T A C M C = C = LOW LEAKAGE FILM (I.E. POLYPROPYLENE) = = METAL FILM % LTC64 AI LTC64 AI3 Figure 4. Buering the Output o a 4th Order Bandpass Realization Figure 5. Servo Ampliier W ODES OF OPERATIO PRIMARY MODES Mode In Mode, the ratio o the external clock requency to the center requency o each nd order section is internally ixed at 5: or :. Figure 6 illustrates Mode providing nd order notch, lowpass, and bandpass outputs. Mode can be used to make high order Butterworth Iowpass ilters; it can also be used to make low Q notches and or cascading nd order bandpass unctions tuned at the same center requency with unity gain. Mode is aster than Mode 3. Note that Mode can only be implemented with 3 o the 4 LTC64 sections because section D has no externally available summing node. Section D, however, can be internally connected in Mode upon special request. AGND N S BP LP /4 LTC64 o = CLK ; n = O ; H OLP = ; H OBP = ; H ON = Q = (5) LTC64 MOO Figure 6. Mode : nd Order Filter Providing Notch, Bandpass, Lowpass Σ 9

10 W ODES OF OPERATIO Mode 3 Mode 3 is the second o the primary modes. In Mode 3, the ratio o the external clock requency to the center requency o each nd order section can be adjusted above or below 5: or :. Side D o the LTC64 can only be connected in Mode 3. Figure 7 illustrates Mode 3, the classical state variable coniguration, providing highpass, bandpass, and lowpass nd order ilter unctions. Mode 3 is slower than Mode. Mode 3 can be used to make high order all-pole bandpass, lowpass, highpass and notch ilters. When the internal clock-to-center requency ratio is set at 5:, the design equations or Q and bandpass gain are dierent rom the : case. This was done to provide speed without penalizing the noise perormance. C C HP S BP LP Σ /4 LTC64 SECONDARY MODES Mode b Mode b is derived rom Mode. In Mode b, Figure 8, two additional resistors R5 and R6, are added to alternate the amount o voltage eedback rom the lowpass output into the input o the SA (or SB or SC) switched capacitor summer. This allows the ilter clock-to-center requency ratio to be adjusted beyond 5: or :. Mode b maintains the speed advantages o Mode. Mode Mode is a combination o Mode and Mode 3, as shown in Figure 9. With Mode, the clock-to-center requency ratio, CLK / O, is always less than 5: or :. The advantage o Mode is that it provides less sensitivity to resistor tolerances than does Mode 3. As in Mode, Mode has a notch output which depends on the clock requency, and the notch requency is thereore less than the center requency, O. When the internal clock-to-center requency ratio is set at 5:, the design equations or Q and bandpass gain are dierent rom the : case. R6 R5 AGND N S BP LP MODE 3 (:): o = CLK ; Q = ; H OHP = /; H OBP = /; H OLP = / Σ MODE 3 (5:): o = CLK.5 ( /) ; Q = 5 (/) (/6); / H OLP = /; H OBP = ; H OLP = / (/6) AGND NOTE: THE 5: EQATIONS FOR MODE 3 ARE DIFFERENT FROM THE EQATIONS FOR MODE 3 OPERATION OF THE LTC59, LTC6 AND LTC6. START WITH o, CALCLATE /, SET ; FROM THE Q VALE, CALCLATE : =.5 Q 6 ; THEN CALCLATE TO SET THE DESIRED GAIN LTC64 MOO o = CLK R6 ; ; Q = (5) n = R5 R6 o ( ) H ON ( ) = H ON CLK H OBP = ; (R5//R6) < 5kΩ R6 ; R5 R6 = / ; H OLP = ; R6/(R5 R6) LTC64 MOO3 Figure 7. Mode 3: nd Order Filter Providing Highpass, Bandpass, Lowpass Figure 8. Mode b: nd Order Filter Providing Notch, Bandpass, Lowpass

11 W ODES OF OPERATIO Mode 3A This is an extension o Mode 3 where the highpass and lowpass output are summed through two external resistors and to create a notch. This is shown in Figure. Mode 3A is more versatile than Mode because the notch requency can be higher or lower than the center requency o the nd order section. The external op amp o Figure is not always required. When cascading the sections o the LTC64, the highpass and lowpass outputs can be summed directly into the inverting input o the next section. The topology o Mode 3A is useul or elliptic highpass and notch ilters with clock to cuto requency ratios higher than :. This is oten required to extend the allowed input signal requency range and to avoid premature aliasing. When the internal clock-to-center requency ratio is set at 5:, the design equations or Q and bandpass gain are dierent rom the : case. N S BP LP Σ /4 LTC64 MODE (:): MODE (5:): = o = CLK ; n = CLK 5 ; Q = / H OBP = /; H ON ( ) = (/) ; n = CLK ; Q = 5 H OBP = / / ; H (/6) ON ( ) = (/) NOTE: THE 5: EQATIONS FOR MODE ARE DIFFERENT FROM THE EQATIONS FOR MODE OPERATION OF THE LTC59, LTC6 AND LTC6. START WITH o, CALCLATE /, SET ; FROM THE Q VALE, CALCLATE :.5 Q o = CLK 5 ( ) H ON CLK = / ; H OLP = / (/) ( ) ; H ON CLK = /.5 ( /) ; H OLP = / (/) (/6) (/) ; THEN CALCLATE TO SET THE DESIRED GAIN 6 LTC64 MOO4 Figure 9. Mode : nd Order Filter Providing Notch, Bandpass, Lowpass AGND C C HP S BP LP Σ /4 LTC64 MODE 3A (:): MODE 3A (5:): R G o = CLK R H G OLP = /; H ON ( ) = ; H R ON CLK R = G L R G R H G ON ( = o ) = Q ( H OLP H R OHP ; Q = H ) ; n = CLK o = CLK ; H = / 5 5 R OHP CLK L ( ) NOTE: THE 5: EQATIONS FOR MODE 3A ARE DIFFERENT FROM THE EQATIONS FOR MODE 3A OPERATION OF THE LTC59, LTC6 AND LTC6. START WITH o, CALCLATE /, SET ; FROM THE Q VALE, CALCLATE : = NOTCH.5 Q EXTERNAL OP AMP OR INPT OP AMP OF THE LTC64, SIDE A, B, C, D ; n = CLK 6 ; H OHP = /; H OBP = / ( ) H OBP = / ; H (/6) OLP ( = ) = /.5 ( /) ; Q = (/) (/6) ; THEN CALCLATE TO SET THE DESIRED GAIN LTC64 MOO5 Figure. Mode 3A: nd Order Filter Providing Highpass, Bandpass, Lowpass, Notch

12 TYPICAL APPLICATIO S 8.5k 96k 75k 54k 75k k 76.8k 88.7k 5 8V 3k 76.8k 3k LTC CLK 8V k 54k 76.8k 54k -8V 5V LT56 V OT 9.9k 9.9k 3dB = CLK 5 CLK = 5kHz -5V LTC64 AC Figure. 8th Order Lowpass Butterworth, Passband Noise 9µV RMS (Also Reer to the LTC64-5) GAIN (db) k LTC64 8th Order Butterworth, CLK = 5kHz, 3dB = khz k FREQENCY (Hz) 5k LTC64 AC HARMONIC DISTRIBTION (%)... 5 LTC64 8th Order Butterworth, CLK = 5kHz, 3dB = khz ±8V, A. V RMS, B. 4V RMS B A k FREQENCY (Hz) LTC64 AC3 k

TYPICAL APPLICATIO S 78.7k 67k 63.4k 4.k 4 3 4.k 4.k 3 48.7k 6.4k 4 69.8k 84.5k.5V 7.5k 5V 5 6 9 LTC64 7 8 8 7.5V CLK 5V LT4 88.7k 46.4k 9 6 5 k 7k 5.3k LT6 V OT 4.k 4 k 3 95.

13 TYPICAL APPLICATIO S 78.7k 67k 63.4k 4.k k 4.k k 6.4k k 84.5k.5V 7.5k 5V LTC V CLK 5V LT4 88.7k 46.4k k 7k 5.3k LT6 V OT 4.k 4 k k 5k 3dB = CLK CLK = 5kHz LTC64 AC4 Figure. 8th Order Lowpass Single Supply Elliptic-Bessel Transitional Filter Total Supply Current = 4mA, Passband Noise 5µV RMS GAIN (db) LTC64 8th Order Lowpass, Elliptic-Bessel Traditional Filter Single 5V Supply CLK = 5kHz -3dB=5kHz k k FREQENCY (Hz) 5k LTC64 AC5.5V/DIV Transient Response µs/div INPT khz, V SQAREWAVE 3

14 TYPICAL APPLICATIO S B C ALL RESISTORS MF % A B 48.7k 46.4k 34.k 3.6k 7k 4.k 9.4k R I 39k 58k R h 63.4k 8.k C 3.6k 39.k 3.k k 7.4k D 43.k 3.6k 69.8k LTC64 5 A V CLK V V k D V LT6 V LTC64 AC6 V OT Figure 3. LTC64 8th Order Lowpass Elliptic, CTOFF = 5kHz, CLK = 5kHz, 78dB at khz, Passband Noise = µv RMS ±5V (Also Reer to the LTC64-6).... GAIN (db) k CLK = 5kHz C = 5kHz, : 78dB AT. CTOFF FREQENCY (Hz) k 5k LTC64 AC7 Figure 4. LTC64 8th Order Lowpass Elliptic, CTOFF = 5kHz 4

15 TYPICAL APPLICATIO S B V LTC CLK RL V C V ALL RESISTORS MF % A 8.5k 3.k 7.5k 44.k k 75k B 8.7k 3k 8.7k 3.9k 4k 3.k 38.3k 57.6k 8k 4k 4.k 4.3k 68.k 3.9k 3.k C R G C D R G = 8.6k C =.µf GAIN (db) CLK = 4kHz C = 4kHz : 74dB AT.5 CTOFF A D V LT6 V V OT LTC64 AC k FREQENCY (Hz) k k LTC64 AC7 Figure 6. LTC64 9th Order Lowpass Elliptic, CTOFF = 4kHz Figure 5. LTC64 9th Order Lowpass Elliptic, Fixed CTOFF = 4kHz, CLK = 4kHz, 74dB at 5kHz, Passband Noise = µv RMS ±5V PACKAGE DESCRIPTIO J Package 4-Lead CERDIP (Narrow.3 Inch, Hermetic) (Reerence LTC DWG # 5-8-).9 (3.77) MAX ( ) (.635) RAD TYP.3 BSC (7.6 BSC) (.7) MIN. (5.8) MAX.5.6 (.38.54).8.8 (.3.457) 5 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.5 (3.75) MIN (.43.65).4.6 (.36.66). (.54) BSC J4 8 OBSOLETE PACKAGE Inormation urnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed or its use. Linear Technology Corporation makes no representation that the interconnection o its circuits as described herein will not inringe on existing patent rights. 5

16 PACKAGE DESCRIPTIO N Package 4-Lead PDIP (Narrow.3 Inch) (Reerence LTC DWG # 5-8-5).65* (3.3) MAX ±.5* (6.477 ±.38) ( ).3 ±.5 (3.3 ±.7) (.43.65).8.5 (.3.38) ( ). (.58) MIN. (3.48) MIN NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.54mm). (.54) BSC.8 ±.3 (.457 ±.76).65 (.65) TYP N4 SW Package 4-Lead Plastic Small Outline (Wide.3 Inch) (Reerence LTC DWG # 5-8-6).3 ±.5 TYP N.5 BSC.45 ± ( ) NOTE N.4 MIN.35 ±.5 NOTE (.7.643) 3 N/ N/ RECOMMENDED SOLDER PAD LAYOT.5 (.7) RAD MIN.9.99 ( ) NOTE ( ) 8 TYP.93.4 (.36.64) (.94.43) (.7) (.9.33) NOTE 3 BSC ( ) (.46.7) NOTE: TYP INCHES. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE 3. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.6" (.5mm) Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA (48) 43-9 FAX: (48) (..35) S4 (WIDE) 5 LT/TP K REV A PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 99

FEATURES APPLICATIO S TYPICAL APPLICATIO. LTC Low Noise, 8th Order, Clock Sweepable Elliptic Lowpass Filter DESCRIPTIO

FEATURES APPLICATIO S TYPICAL APPLICATIO. LTC Low Noise, 8th Order, Clock Sweepable Elliptic Lowpass Filter DESCRIPTIO LTC- Low Noise, th Order, Clock Sweepable Elliptic Lowpass Filter FEATRES th Order Filter in a -Pin Package No External Components : Clock to Center Ratio µv RMS Total Wideband Noise.% THD or Better khz