DESCRIPTION FEATURES APPLICATIONS. LTC / LTC /LTC1329A-50 Micropower 8-Bit Current Output D/A Converter TYPICAL APPLICATION

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1 LTC9-/ LTC9-/LTC9A- Micropower -Bit Current Output D/A Converter FEATRES Guaranteed Precision Full-Scale DAC Output Current at C: LTC9A- µa ±% LTC9- µa ±% LTC9- µa ±% Wide Output Voltage DC Compliance: V to.v Wide Supply Range:.V.V Supply Current in Shutdown:.µA Low Supply Current: µa for LTC9-, 9µA for LTC9-/LTC9A- Available in -Pin SO Triple Mode TM Interface Modes. Standard -Wire Mode. Pulse Mode -Wire Interface: Increment-Only. Pulse Mode -Wire Interface: Increment/Decrement Can Read Back the -Bit DAC Value in -Wire Mode DAC Powers p at Midrange DAC Contents Are Retained in Shutdown APPLICATIONS LCD Contrast Control Backlight Brightness Control Battery Charger Current/Voltage Adjustment Power Supply Voltage Adjustment Trimmer Pot Elimination DESCRIPTION The LTC 9-/LTC9-/LTC9A- are micropower -bit current output D/A converters (DACs) with an output range of µa to µa for the LTC9- and µa to µa for the LTC9-/LTC9A-. The DAC current output can be biased from V to V or V to.v in.v and V systems, respectively. Supply current is only 9µA for the LTC9-/LTC9A- and µa for LTC9-. A shutdown mode drops the supply current to.µa. The LTC9 can communicate with external circuitry by using one of three interface modes: standard -wire serial mode and two pulse modes. pon power-up, the internal counter resets to B, the DAC output assumes midrange and the chip is configured in -wire or pulse mode depending on the signal level at CS. In -wire mode, the system MP can serially transfer -bit data to and from the LTC9. In pulse mode, the upper six bits of the DAC output can be programmed for increment-only (-wire interface) or increment/decrement (-wire interface) operation depending on the signal level at D IN. LTC9 is available in -pin SO packages., LTC and LT are registered trademarks of Linear Technology Corporation. Triple Mode is a trademark of Linear Technology Corporation. TYPICAL APPLICATION Digitally Controlled LCD Bias Generator V IN V µf *GOWANDA GA-K OR COILTRONICS CTX- Ω I LIM V IN SW LT FB GND SW L* µh N N.µF N k.k µf.µf k V OT V at ma I OT LTC9- GND CS MP (e.g., ) P. P. P. 9 TA

2 LTC9-/ LTC9-/LTC9A- ABSOLTE MAXIMM RATINGS W W W (Note ) Supply Voltage ( )... V Input Voltage (All Inputs)....V to (.V) Output Voltage I OT... V to (.V)....V to (.V) Short-Circuit Duration (All Outputs)... Indefinite Operating Temperature Range... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER INFORMATION I OT TOP VIEW S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = C/ W D IN (P/DN) GND CS W ORDER PART NMBER LTC9CS- LTC9CS- LTC9ACS- S PART MARKING 9 9 9A Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS =.V, T A = C, unless otherwise specified. LTC9- LTC9-/LTC9A- SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS.... V I CC Supply Current V = V DIN = V CS =, V = V, 9 µa = NC, I OT = NC Shutdown.. µa DAC Resolution Bits DAC Full-Scale Current Output Voltage at I OT =.V, T A = C µa (LTC9-, LTC9-) µa Output Voltage at I OT =.V, T A = C 9.. µa (LTC9A-) 9.. µa DAC Zero-Scale Current Output Voltage at I OT =.V na DAC Differential Monotonicity Guaranteed ±. ±.9 ±.9 LSB Nonlinearity Supply Voltage Rejection = V to.v, I OT = Full Scale, ± ± ± ± LSB Output Voltage at I OT =.V =.V to.v, Full Scale, ±. ± ±. ± LSB Output Voltage at I OT =.V Output Voltage Rejection = V, I OT = Full Scale, ±. ± ±. LSB Output Voltage at I OT = V to V = V, I OT = Full Scale, ±. ±. LSB Output Voltage at I OT = V to.v I IH, I IL Logic Input Current V V IN ± ± µa V IH High Level Input Voltage = V.. V =.V.9.9 V V IL Low Level Input Voltage = V.. V =.V.. V V OH High Level Output Voltage = V, I O = µa.. V =.V, I O = µa.. V V OL Low Level Output Voltage = V, I O = ma.. V =.V, I O = ma.. V I OZ Three-State Output Leakage V CS = ± ± µa

3 RECO E DED OPERATI G CO DITIO S WW LTC9-/ LTC9-/LTC9A- =.V, unless otherwise specified. (Notes, ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Serial Interface f Clock Frequency MHz t CKS Setup Time, Before CS ns t CSS Setup Time, CS Before ns t DV CS to Valid See Test Circuits ns t DS D IN Setup Time Before ns t DH D IN Hold Time After ns t DO to Valid See Test Circuits ns t CKHI High Time ns t CKLO Low Time ns t CSH Before CS ns t DZ CS to in Hi-Z See Test Circuits ns t CKH CS Before ns t CSLO CS Low Time f = MHz (Note ) ns V = V ns t CSHI CS High Time ns The denotes specifications which apply over the full operating temperature range. Note : Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note : Timing for all input signals is measured at.v for a High-to-Low transition and at V for a Low-to-High transition. Note : Timing specification are guaranteed but not tested. Note : This is the minimum time required for valid data transfer. TYPICAL PERFORMANCE CHARACTERISTICS W DNL (LSB) LTC9- DNL vs Code LTC9- INL vs Code LTC9- DNL vs Code T A = C =.V V(I OT ) =.V 9 9 CODE INL (LSB) T A = C =.V V(I OT ) =.V 9 9 CODE DNL (LSB) T A = C =.V V(I OT ) =.V 9 9 CODE 9 G 9 TPC 9 G

4 LTC9-/ LTC9-/LTC9A- TYPICAL PERFORMANCE CHARACTERISTICS INL (LSB) LTC9- INL vs Code T A = C =.V V(I OT ) =.V W 9 9 CODE FLL-SCALE IOT ERROR (LSB) LTC9-/LTC9- Full- Scale Current vs Temperature =.V V(I OT ) =.V LTC9- TEMPERATRE ( C) LTC9- FLL-SCALE I OT ERROR (LSB) LTC9-/LTC9- Supply Voltage Rejection T A = C V(I OT ) =.V LTC9- LTC9- SPPLY VOLTAGE (V) FLL-SCALE I OT ERROR (LSB) LTC9-/LTC9- Bias Voltage Rejection (Full-Scale Current) T A = C =.V LTC9- LTC9-9 TPC. 9 I OT BIAS VOLTAGE (V) 9 G ZERO-SCALE IOT CRRENT (na) LTC9-/LTC9- Bias Voltage Rejection (Zero-Scale Current) LTC9- LTC9-9 G 9 I OT BIAS VOLTAGE (V) 9 G MAXIMM I OT BIAS VOLTAGE (V) Maximum I OT Bias Voltage vs Supply Voltage T A = C I OT = FLL-SCALE CRRENT 9 G SPPLY VOLTAGE (V) 9 TPC9 PIN FNCTIONS I OT (Pin ): DAC Current Output. In.V or V systems, the DAC current output can be biased from V to V or V to.v respectively. (Pin ): Voltage Supply (.V.V). This supply must be kept free from noise and ripple by bypassing directly to the ground plane. (Pin ): Shutdown. A logic low puts the chip into Shutdown mode. The digital setting for the DAC is retained. (Pin ): Shift Clock. This clock synchronizes the serial data in -wire mode. This pin has a Schmitt trigger input. CS (Pin ): Chip Select Input. In -wire mode, a logic low on this CS pin enables the LTC9. pon power-up, a logic high at CS puts the chip into pulse mode. If CS ever goes low, the chip is configured in -wire mode until the next power is cycled. GND (Pin ): Ground. Ground should be tied directly to a ground plane. D IN (P/DN)(Pin ): Data Input. In -wire mode, the DAC data is shifted into D IN on the rising edge of. In pulse mode, upon power-up a logic high at D IN puts the counter into increment-only mode. If D IN ever goes low, the

5 LTC9-/ LTC9-/LTC9A- PIN FNCTIONS counter is configured in increment/decrement mode until the power is cycled. (Pin ): Data Output. In -wire mode, on every conversion serially outputs the previous -bit DAC data. In pulse mode, is three-stated. BLOCK DIAGRA W POWER-ON RESET LATCH AND LOGIC P ONLY/ P/DN VOLTAGE REFERENCE LATCH AND LOGIC -BIT CRRENT DAC I OT MODE SELECT = PLSE = -WIRE D IN (P/DN) CS CONTROL LOGIC -BIT DAC REGISTER/CONTER P/DN D IN 9-BIT SHIFT REGISTER 9 BD TEST CIRCITS Voltage Waveforms for t DO Voltage Waveforms for t DZ, t DV.V t DO CS.V.V.V.V 9 TC SET HIGH SET LOW HI-Z HI-Z t DV.V.V t DZ 9% % HI-Z HI-Z 9 TC Load Circuit for t DO.V Load Circuit for t DZ, t DV k pf k pf V t DZ WAVEFORM, t DV t DZ WAVEFORM 9 TC 9 TC

6 LTC9-/ LTC9-/LTC9A- SERIAL I/O OPERATI G SEQE CE t CSLO t CSHI CS t CKS t CKHI t CSH t CSS t DS t DH t CKLO t CKH D IN D D D D D D D D t DV t DO t DZ Hi-Z D D D D D D D D D Hi-Z 9 F Figure. -Wire Interface Timing Specification APPLICATIONS INFORMATION -BIT CRRENT OTPT DAC W The LTC9-/LTC9-/LTC9A- are -bit, current output digital-to-analog (DAC) converters. For each part, the -bit DAC output is guaranteed monotonic and is digitally adjustable in equal steps. pon power up, the internal DAC register resets to B and the DAC output assumes midrange. The current output (I OT ) can be biased from V to V or V to.v in.v and V systems, respectively. The LTC9- features a fullscale output of µa trimmed to ±% at room temperature (±% over temperature), while the LTC9- features a µa full scale and two accuracy grades; ±% at room temperature (±% over temperature) for the LTC9A- and ±% at room temperature (±% over temperature) for the LTC9-. All versions include a flexible serial digital interface which allows easy interconnection to a variety of digital systems. DIGITAL INTERFACE Automatic Mode Selection The LTC9 family includes a serial interface capable of communicating with the host system using one of three protocols; standard -wire mode, a -wire up/down pulse mode and a -wire increment-only pulse mode. The LTC9 family is designed to auto-configure itself depending on the way data is presented to it. A diagram illustrating this auto detection behavior is shown in Figure. At power-up, the interface is set to -wire pulse mode. If the CS line ever goes low (as it will at the beginning of a valid -wire serial transfer) the chip immediately reconfigures itself into -wire mode and remains in this mode until the next time the power is cycled. If CS stays high, the LTC9 family stays in pulse mode and watches the P/DN pin to determine whether to switch to -wire mode. If P/DN ever goes low (as it will the first time a down command is given) the chip switches into -wire pulse mode and remains in this mode until the next time the power is cycled. In a properly configured -wire system, CS and P/DN will stay high continuously and the LTC9-/LTC9-/LTC9A- will remain in - wire pulse mode. -wire pulse mode systems should give a single down pulse sometime before the first data pulses are sent to prevent the LTC9 family from staying in -wire mode if the first several pulses happen to be ups. CS GOES LOW -WIRE MODE POWER-P D IN (P/DN) GOES LOW INCREMENT/ DECREMENT CS STAYS HIGH PLSE MODE D IN STAYS HIGH INCREMENT- ONLY Figure. LTC9 Operating Modes 9 F

7 LTC9-/ LTC9-/LTC9A- APPLICATIONS INFORMATION W Standard -Wire Mode (Figure ) Refer to the Serial Interface Operating Sequence in Figure. When operating in -wire mode, the LTC9-/ LTC9-/LTC9A- will interface directly with most standard - or -wire serial interface systems. The clock () input synchronizes the data transfer with each input bit captured at the rising edge of and each output data bit shifted out through at the falling edge. A falling edge at CS initiates the data transfer and brings the pin out of three-state. The serial -bit data representing the new DAC setting is shifted into the D IN pin. Simultaneously, the previous DAC setting is shifted out of the pin. After the new data is shifted in, a rising edge at CS transfers the data from the input shift register into the DAC register. The DAC output assumes the new value and the pin returns to a high-impedance state. I OT = (B B B B B B B B)I FLLSCALE /.µf I OT CS D IN I OT LTC9 GND CS D IN AND CAN BE TIED TOGETHER FOR HALF DPLEX DATA TRANSFER 9 F Figure. -Wire Mode; Serial Interface (-Wire Control by CS, and D IN ) -Wire Interface (Pulse Mode, Figure ) In -wire pulse mode, each rising edge at increments the upper six bits of the DAC register by one count. When incramented beyond B, the counter rolls over and sets the DAC to the minimum value (B). In this way, a single pulse applied to increases the DAC output by a single -LSB step and pulses decrease the DAC output by one step. The last two LSBs are always zero in pulse mode. I OT = (B B B B B B )I FLLSCALE / To configure the LTC9-/LTC9-/LTC9A- in -wire pulse mode, tie both the CS and D IN pins to..µf I OT I OT LTC9 GND CS 9 F Figure. Pulse Mode: Increment Only (-Wire Control by ) -Wire Interface (Pulse Mode, Figure ) In -wire pulse mode, a logic HIGH at P/DN programs the DAC register to increment and each rising edge at increments the upper six bits of the register by one count. Similarly, a logic LOW at P/DN set the DAC register to decrement and a rising edge at decrements the upper six bits of the register by one count. Each count in -wire mode changes the DAC output by a single four LSB step. The DAC register stops incramenting at B and stops decrementing at B and will not roll over in -wire pulse mode. The last two LSBs are always zero in pulse mode. I OT = (B B B B B B )I FLLSCALE / To configure the LTC9-/LTC9-/LTC9A- in -wire pulse mode, tie CS to and bring the P/DN pin low at least once during power-up..µf I OT P/DN I OT LTC9 GND CS 9 TA Figure. Pulse Mode; Increment/Decrement (-Wire Control by and P/DN) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

8 LTC9-/ LTC9-/LTC9A- PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S Package -Lead Plastic Small Outline (Narrow.) (LTC DWG # --).9.9* (..).. (..).. (..) TYP..9 (..).. (..).. (.9.9)..** (..9) (..) *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE TYPICAL APPLICATIONS. (.) TYP Pulse Mode: Increment-Only (-Wire Control by ) with Voltage Output SO 99 V OT R FB k LT V EE V BIAS.µF I OT LTC9 GND CS V OT = ( I OT )(R FB V BIAS ) V EE < V BIAS V OT FOR =.V, V V BIAS V FOR = V, V V BIAS.V Digitally Controlled Power Supply Adjustment 9 TA V IN V µf *COILTRONICS CTX- Ω I LIM V IN SW LT FB GND SW L* µh N k k V OT V (ma) TO V (ma) µf I OT LTC9- GND CS MP (e.g., ) P. P. P. 9 TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC -Bit Micropower Serial Input V OT DAC Higher Resolution, -Pin SO LTC -Bit Multiplying Serial Input V OT DAC Higher Resolution, -Pin SO LTC -Bit Multiplying Serial Input I OT DAC Higher Resolution, -Pin SO Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - TELEX: f LT/TP 9 K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 99

DESCRIPTIO. LTC1446/LTC1446L Dual 12-Bit Rail-to-Rail Micropower DACs in SO-8

DESCRIPTIO. LTC1446/LTC1446L Dual 12-Bit Rail-to-Rail Micropower DACs in SO-8 Dual 12-Bit Rail-to-Rail Micropower DACs in SO-8 FEATRES Dual DACs with 12-Bit Resolution SO-8 Package Rail-to-Rail Output Amplifiers 3V Operation (LTC1446L): I CC = 65µA Typ 5V Operation (LTC1446): I