THE UNIVERSITY OF NEW SOUTH WALES. School of Electrical Engineering & Telecommunication FINAL EXAMINATION. Session 1, ELEC3106 Electronics

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1 THE UNIVERSITY OF NEW SOUTH WALES School of Electrical Engineering & Telecommunication FINAL EXAMINATION Session 1, 2014 ELEC3106 Electronics TIME ALLOWED: 3 hours TOTAL MARKS: 100 TOTAL NUMBER OF QUESTIONS: 4 THIS EXAM CONTRIBUTES 70% TO THE TOTAL COURSE ASSESSMENT Reading time: 10 minutes. This paper contains 8 pages. Candidates must ATTEMPT ALL questions. Answer each question in a separate answer book. All questions are of equal value. This paper MAY be retained by the candidate. Print your name, student ID and question number on the front page of each answer book. Authorised examination materials: Drawing instruments may be brought into the examination room. Candidates should use their own UNSW-approved electronic calculators. This is a closed book examination. Assumptions made in answering questions should be stated explicitly. All answers must be written in ink. Except where they are expressly required, pencils may only be used for drawing, sketching or graphical work. 1

2 LTC7543/LTC8143 Improved Industry Standard Serial 12-Bit Multiplying DACs FEATURES Improved Direct Replacement for AD7543 and DAC-8143 Low Cost DNL and INL Over Temperature: ±0.5LSB Easy, Fast and Flexible Serial Interface Daisy-Chain 3-Wire Interface for Multiple DAC Systems (LTC8143) 1LSB Maximum Gain Error Over Temperature Eliminates Adjustment Asynchronous Clear Input for Initialization Four-Quadrant Multiplication Low Power Consumption 16-Pin PDIP and SO Packages APPLICATIONS U Process Control and Industrial Automation Remote Microprocessor-Controlled Systems Digitally Controlled Filters and Power Supplies Programmable Gain Amplifiers Automatic Test Equipment DESCRIPTION U The LTC 7543/LTC8143 are serial-input 12-bit multiplying digital-to-analog converters (DACs). They are superior pin compatible replacements for the AD7543 and DAC Improvements include better accuracy, better stability over temperature and supply variations, lower sensitivity to output amplifier offset, tighter timing specifications and lower output capacitance. An easy-to-use serial interface includes an asynchronous CLEAR input for systems requiring initialization to a known state. The LTC8143 has a serial data output to allow daisychaining multiple DACs on a 3-wire interface bus. These DACs are extremely versatile. They can be used for 2-quadrant and 4-quadrant multiplying, programmable gain and single supply applications, such as noninverting voltage output and biased or offset ground mode. Parts are available in 16-pin PDIP and SO packages and are specified over the extended industrial temperature range, 40 C to 85 C., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION U V IN Multiplying DAC Has Easy 3-Wire Serial Interface 5V Integral Nonlinearity Over Temperature 1.0 CLOCK DATA LOAD V DD V REF R FB STB1 OUT 1 SRI LTC7543 LTC8143 LD1 OUT 2 DGND AGND pF + LT 1097 V OUT 7543/8143 TA01 INTEGRAL NONLINEARITY (LSB) T A = 85 C T A = 25 C T A = 40 C DIGITAL INPUT CODE 7543/8143 TA02 1

3 LTC7543/LTC8143 ABSOLUTE MAXIMUM RATINGS W W W V DD to AGND V to 7V V DD to DGND V to 7V AGND to DGND... V DD + 0.5V DGND to AGND... V DD + 0.5V Digital Inputs to DGND V to (V DD + 0.5V) V OUT1, V OUT2 to AGND V to (V DD + 0.5V) V REF to AGND, DGND... ±25V V RFB to AGND, DGND... ±25V Maximum Junction Temperature C Operating Temperature Range C to 85 C Storage Temperature Range C to 150 C Lead Temperature (Soldering, 10 sec) C U PACKAGE/ORDER INFORMATION OUT 1 1 OUT 2 2 AGND 3 STB1 4 LD1 5 NC (LTC7543) 6 SRO (LTC8143) SRI 7 STB2 8 TOP VIEW 16 R FB 15 V REF 14 V DD 13 CLR 12 DGND 11 STB4 10 STB3 9 LD2 N PACKAGE 16-LEAD PDIP SW PACKAGE 16-LEAD PLASTIC SO WIDE T JMAX = 150 C, θ JA = 100 C/ W (N) T JMAX = 150 C, θ JA = 130 C/ W (SW) U W U ORDER PART NUMBER LTC7543GKN LTC7543KN LTC7543GKSW LTC7543KSW LTC8143EN LTC8143FN LTC8143ESW LTC8143FSW Consult factory for Military grade parts. ACCURACY CHARACTERISTICS LTC7543 V DD = 5V, V REF = 10V, V OUT1 = V OUT2 = AGND = DGND =0V, T A = T MIN to T MAX, unless otherwise specified. LTC7543GK LTC7543K SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resolution Bits INL Integral Nonlinearity (Note 1) ±0.5 ±0.5 LSB (Relative Accuracy) DNL Differential Nonlinearity Guaranteed Monotonic, T MIN to T MAX ±0.5 ±0.5 LSB GE Gain Error (Note 2) T A = 25 C ±1 ±2 LSB T MIN to T MAX ±1 ±2 LSB Gain Temperature Coefficient (Note 3) ppm/ C ( Gain/ Temp) I LKG Output Leakage Current (Note 4) T A = 25 C ±1 ±1 na T MIN to T MAX ±10 ±10 na Zero-Scale Error T A = 25 C ±0.006 ±0.006 LSB T MIN to T MAX ±0.06 ±0.06 LSB PSRR Power Supply Rejection Ratio V DD = 5V ±5% ± ±0.002 ± ±0.002 %/% 2

4 ACCURACY CHARACTERISTICS LTC8143 V DD = 5V, V REF = 10V, V OUT1 = V OUT2 = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. V DD = 5V, V REF = 10V, V OUT1 = V OUT2 = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. LTC7543/LTC8143 LTC8143E LTC8143F SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resolution Bits INL Integral Nonlinearity (Note 1) ±0.5 ±1 LSB (Relative Accuracy) DNL Differential Nonlinearity Guaranteed Monotonic, T MIN to T MAX ±0.5 ±1 LSB GE Gain Error (Note 2) T A = 25 C ±1 ±2 LSB T MIN to T MAX ±2 ±2 LSB Gain Temperature Coefficient (Note 3) ppm/ C ( Gain/ Temp) I LKG Output Leakage Current (Note 4) T A = 25 C ±5 ±5 na T MIN to T MAX ±25 ±25 na Zero-Scale Error T A = 25 C ±0.03 ±0.03 LSB T MIN to T MAX ±0.15 ±0.15 LSB PSRR Power Supply Rejection Ratio V DD = 5V ±5% ± ±0.002 ± ±0.002 %/% ELECTRICAL CHARACTERISTICS LTC7543/LTC8143 LTC7543/LTC8143 ALL GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input R REF V REF Input Resistance (Note 5) kω AC Performance (Note 3) Output Current Settling Time (Notes 6, 7) µs Multiplying Feedthrough Error V REF = ±10V, 10kHz Sinewave mv P-P Digital-to-Analog Glitch Energy (Notes 6, 8) 2 20 nv-sec THD Total Harmonic Distortion (Note 9) db Output Noise Voltage Density (Note 10) 13 nv/ Hz Analog Outputs (Note 3) C OUT Output Capacitance DAC Register Loaded to All 1s C OUT pf C OUT pf DAC Register Loaded to All 0s C OUT pf C OUT pf Digital Inputs V IH Digital Input High Voltage 2.4 V V IL Digital Input Low Voltage 0.8 V I IN Digital Input Current V IN = 0V to V DD ±1 µa C IN Digital Input Capacitance (Note 3), V IN = 0V 8 pf Digital Outputs: SRO (LTC8143 Only) V OH Digital Output High I OH = 200µA 4 V V OL Digital Output Low I OL = 1.6mA 0.4 V 3

5 QUESTION 1 [25 marks] An amplifier implemented using an operational amplifier powered from a single supply is shown in Figure 1(a). To enable amplification of bipolar signals, both input and output are AC coupled; the capacitors can be regarded as infinite. The amplifier must not distort the signal. Key specifications for the operational amplifier in shown in Figure 1(b). v IN R 1 C 1 R 2 V CC R 3 v OA R 4 R 5 C 2 v OUT R L (a) Parameter Value Single supply voltage V CC 3V Input offset voltage V OS 30mV Input bias current I B 1nA Input CM voltage range V CM 0V to 3V Input noise voltage e n 100nV/ Hz Output voltage range V OA 0.2V to 2.8V Max output current I O 10mA Gain-bandwidth GBW 30 MHz (b) Figure 1: Single-supply amplifier. Circuit (a). Op-amp data (b). (A) Find an expression for the amplifier gain, A V = v OUT /v IN. The amplifier must be designed to maximise the (un-distorted) voltage swing across the load resistance, and to have a gain of A V = 30. In the following, it is assumed that A V = 2R 5 /R 4 ; further, the DC output voltage of the operational amplifier is given by: V OA = R 4 R 3 + R 4 V CC + ( V OS + (B) Find values for the resistors R 1 to R 5. ( R2 R 1 + R 2 R 4 R 3 + R 4 )V CC ) A V (C) What is the smallest load resistance, R L that the amplifier can drive? The operational amplifier offset voltage can cause a significant reduction in the maximum output voltage swing. (D) Suggest a modification to the circuit that enables the effects of offsets to be trimmed out. The dynamic range, DR of the amplifier is limited by noise and by the maximum output voltage swing. The amplifier noise is dominated by noise from the operational amplifier (resistor noise can be ignored); further, a signal-to-noise ratio of at least 1 is required. The signal voltage is assumed to be sinusoidal and limited in amplitude by (symmetrical) clipping at the output. (E) Find an expression for the amplifier DR as a function of gain A V. 5

6 QUESTION 2 [25 marks] Figure 2(a) shows a logic gate, U 1 driving a gate in a different system U 2 via a transmission line of length X 1 = 5m. The characteristic impedance of the transmission line is Z 0 = 100Ω and in it the speed of light is c = 15cm/ns. The gates are modern CMOS gates from the TinyLogic UHS family; key gate parameters are shown in Figure 2(b). Both gates operate at power supplies V CC1 = V CC2 = 3V, and it may be assumed that the supply pin voltage of the driving gate is V CCG = 3V unless otherwise noted. Ground planes are used to prevent voltage drop along ground connections. V CC1 L 1 V CCG V CC2 C 2 C 1 U i 1 1 v1 U2 R GND1 1 GND2 X 1 Z 0 (a) Parameter Value Supply voltages V CC 3V High output (I OH = 20mA) V OH 2.7V Low output (I OL = 20mA) V OL 0.3V Input capacitance C in 4pF Input current I in 0A (b) Figure 2: CMOS gate connection via transmission line (a). CMOS gate family data (b). R 1 must be chosen such that repeated reflections on the transmission line is avoided; in finding R 1, the output resistance, r OUT of the driving gate, U 1 must be taken into account. Transitions at the output of U 1 are assumed fast. (A) Find an estimate for r OUT and hence find R 1. (B) Sketch the voltage, v 1 (t) and current i 1 (t) at the input of the transmission line during a low-high transition and note relevant times, voltages and currents. In the following, it is assumed that a constant current of I 1 = 20mA flows for a period of T = 50ns during a low-high transition at the U 1 output. The L 1 parasitic inductance prevents this current flow being delivered by the main supply V CC1 ; therefore, a supply decoupling capacitor, C 1 is attached close to the U 1 gate at V CCG. C 1 must ensure V CCG < 0.1V during gate transitions. (C) Find a suitable value for C 1. The output of U 2 is desired to be distributed to many gates. The output rise time, t R is determined by the r OUT C L time constant, where r OUT is the gate output resistance and C L is the load capacitance at the gate output. In the following, it is assumed that r OUT = 20Ω, and that C L consists purely of the input capacitances of the gates U 2 is driving. It is required that t R < 2ns. (D) Find the maximum fan-out of U 2. [Hint, first find t R as a function of C L.] The transmission line has a connector at the U 1 end (not shown); as such, this leaves U 1 exposed to touch and hence to electro-static discharge (ESD) events. (E) Show how to protect U 1 against ESD. 6

7 QUESTION 3 [25 marks] A digital-to-analogue converter (DAC), LTC8143FN, is controlled by a CMOS micro-controller via a serial interface as shown in Figure 3 (the op-amp can be regarded as ideal). A partial datasheet can be found for the DAC at the beginning of this exam paper. As configured in the figure, the DAC output is a current i OUT = (B/4096) (V REF )/(R REF ), where 0 B 4095 is the digital code streamed over the interface and R REF is an internal resistance in the DAC. 3.3V 5.0V V REF V DD CMOS micro I/O controller GND??? V DD V REF STB1 OUT1 SRI LTC8143FN LD1 OUT2 DGND AGND i OUT R 1 v OUT digital analogue Figure 3: Micro-controller driving DAC using serial interface. It is required that v OUT can be set in the range 0V v OUT 2V (guaranteed); further, v OUT should have as many possible settings in this range as possible. R 1 = 10kΩ ± 1%. (A) Find a suitable value for V REF. In the following, it is assumed that V REF = 2V. Interference may cause noise, V REF on the reference voltage, compromising the the accuracy of v OUT. (B) What is the maximum noise voltage, V REF,Max that should be allowed? The circuit has both analogue and digital grounds. (C) Explain how the grounds in the system should be distributed for best circuit performance. The micro-controller has conventional 3.3 V push-pull CMOS output stages in its I/O pins with usual electrical characteristics. (D) Explain what should be in the blocks labelled? to ensure the DAC serial interface is driven in an electrically appropriate manner. To change the DAC output, a 12 bit word is streamed in over the DAC s serial interface: the data bits are presented on the SRI pin (most significant bit first) and are sampled on the rising edge of the STB1 pin. While the LD1 pin is low, the serial interface data is loaded into a DAC register, and the DAC output current is set to the corresponding value. (E) Sketch a probable timing diagram for the serial interface (STB1, SRI, and LD1). 7

8 QUESTION 4 [25 marks] Figure 4(a) shows a rechargeable LED torch. The torch uses a Li-ion battery with capacity C = 1Ah whose discharge profile is shown in figure 4(b). The battery is either connected to a charging circuit (switch S 1 conducting) or to the LED, D 1 and driving circuit, U 3 (switch S 2 conducting). The D 1 forward voltage is V F = 3.2V. The supply current draw of the LED driving circuit can be ignored, but its output voltage, V X is required to be V X 0.3V. V Pwr U 1 V Ref V Chg U 2 M 1 R 1 I Chg V B U 3 I L S 1 S 2 D 1 V X (a) V B 4.0V 3.5V 3.0V 2C C C/5 0.1h 1.0h 10.h (b) Figure 4: Rechargeable LED torch (a). Battery discharge profile (b). (A) Find the battery life, when the diode current is I L = 1.5A. For an extra bright torch setting, the diode current is set to I L = 3A; the torch packaging is restricting heat flow such that the thermal resistance from the LED junction to ambient is θ j-a = 12K/W. The torch specified operating ambient temperature is T A [0 C;40 C]. (B) Find the maximum LED junction temperature, T j,3a. In the following, it is assumed that T j,3a = 160 C. The specified maximum junction temperature for the LED is T j,spc = 150 C; at this temperature a wear-out mechanism with an activation energy of E A = 1eV gives an expected LED lifetime of t spc = 50kh. Failure rates are assumed to follow an Arrhenius law: λ e E A/(kT ), where k = ev/k. (C) Find the expected LED lifetime at the bright torch setting, t 3A. The torch is being charged from a USB plug with a voltage V Pwr = 5V ± 5%. The charging voltage is set to V Chg = 4.1V by the linear regulator U 1. The charging current is set to I Chg = 750mA. While the battery voltage, V B is less than V Chg V Ref, U 2 and M 1 ensures a constant charging current is applied to the battery, which is the desired charging setup. (D) Note down key requirements to the linear regulator U 1. (E) Choose suitable values for R 1 and V Ref. END OF EXAMINATION PAPER 8