THE UNIVERSITY OF NEW SOUTH WALES. School of Electrical Engineering & Telecommunication FINAL EXAMINATION. Session 1, ELEC3106 Electronics

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1 THE UNIVERSITY OF NEW SOUTH WALES School of Electrical Engineering & Telecommunication FINAL EXAMINATION Session, 206 ELEC306 Electronics TIME ALLOWED: 3 hours TOTAL MARKS: 00 TOTAL NUMBER OF QUESTIONS: 4 THIS EXAM CONTRIBUTES 70% TO THE TOTAL COURSE ASSESSMENT Reading time: 0 minutes. This paper contains 8 pages. Candidates must ATTEMPT ALL questions. Answer each question in a separate answer book. All questions are of equal value. This paper MAY be retained by the candidate. Print your name, student ID and question number on the front page of each answer book. Authorised examination materials: Drawing instruments may be brought into the examination room. Candidates should use their own UNSW-approved electronic calculators. This is a closed book examination. Assumptions made in answering questions should be stated explicitly. All answers must be written in ink. Except where they are expressly required, pencils may only be used for drawing, sketching or graphical work.

2 a FEATURES Single Supply Operation: +2.5 V to +6 V High Output Current: 250 ma Extremely Low Shutdown Supply Current: 00 na Low Supply Current: 750 A/Amp Wide Bandwidth: 3 MHz Slew Rate: 5 V/ s No Phase Reversal Very Low Input Bias Current High Impedance Outputs When in Shutdown Mode Unity Gain Stable APPLICATIONS Mobile Communication Handset Audio PC Audio PCMCIA/Modem Line Driving Battery Powered Instrumentation Data Acquisition ASIC Input or Output Amplifier LCD Display Reference Level Driver GENERAL DESCRIPTION The AD859, AD8592 and AD8594 are single, dual and quad rail-to-rail input and output single supply amplifiers featuring 250 ma output drive current and a power saving shutdown mode. The AD8592 includes an independent shutdown function for each amplifier. When both amplifiers are in shutdown mode the total supply current is reduced to less than µa. The AD859 and AD8594 include a single master shutdown function that reduces total supply current to less than µa. All amplifier outputs are in a high impedance state when in shutdown mode. These amplifiers have very low input bias currents, making them suitable for integrators and diode amplification. Outputs are stable with virtually any capacitive load. Supply current is less than 750 µa per amplifier in active mode. Applications for these amplifiers include audio amplification for portable computers, portable phone headsets, sound ports, sound cards and set-top boxes. The AD859x family is capable of driving heavy capacitive loads such as LCD panel reference levels. The ability to swing rail-to-rail at both the input and output enables designers to buffer CMOS DACs, ASICs and other wide output swing devices in single supply systems. The AD859, AD8592 and AD8594 are specified over the industrial ( 40 C to +85 C) temperature range. The AD859, single, is available in the tiny 6-lead SOT package. The AD8592, dual, is available in the 0-lead µsoic surface mount package. The AD8594, quad, is available in 6-lead narrow SOIC and 6-lead TSSOP packages. REV. A CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifiers with Shutdown AD859/AD8592/AD8594 PIN CONFIGURATIONS 6-Lead SOT (RT Suffix) OUT A V 2 3 OUT A IN A +IN A SDA AD V 5 SD 0-Lead SOIC (RM Suffix) V+ OUT B 3 AD8592 (Not to Scale) 8 IN B V 4 7 +IN B SDB 6-Lead Narrow SOIC (R Suffix) OUT A V AD OUT D 5 IN D 4 IN D 3 V IN B IN B OUT B TOP VIEW 2 (Not to Scale) IN C IN C 0 OUT C NC 8 9 SD NC = NO CONNECT 6-Lead TSSOP (RU Suffix) OUT A 6 OUT D IN D IN D V V AD8594 IN B +IN C IN B OUT B IN C OUT C NC 8 9 SD NC = NO CONNECT Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: 78/ World Wide Web Site: Fax: 78/ Analog Devices, Inc., 999

3 AD859/AD8592/AD8594 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V OS 25 mv 40 C < T A < +85 C 30 mv Input Bias Current I B 5 50 pa 40 C < T A < +85 C 60 pa Input Offset Current I OS 25 pa 40 C < T A < +85 C 30 pa Input Voltage Range V Common-Mode Rejection Ratio CMRR V CM = 0 V to +2.7 V db Large Signal Voltage Gain A VO R L = 2 kω, V O = +0.3 V to +2.4 V 25 V/mV Offset Voltage Drift V OS / T 20 µv/ C Bias Current Drift I B / T 50 fa/ C Offset Current Drift I OS / T 20 fa/ C OUTPUT CHARACTERISTICS Output Voltage High V OH I L = 0 ma V 40 C to +85 C +2.5 V Output Voltage Low V OL I L = 0 ma mv 40 C to +85 C 25 mv Output Current I OUT ± 250 ma Open-Loop Impedance Z OUT f = MHz, A V = 60 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V S = +2.5 V to +6 V db Supply Current/Amplifier I SY V O = 0 V ma 40 C < T A < +85 C.25 ma Supply Current Shutdown Mode I SD All Amplifiers Shut Down 0. µa 40 C < T A < +85 C µa I SD Amplifier Shut Down (AD8592).4 ma I SD2 Amplifier 2 Shut Down (AD8592).4 ma SHUTDOWN INPUTS Logic High Voltage V INH 40 C < T A < +85 C +.6 V Logic Low Voltage V INL 40 C < T A < +85 C +0.5 V Logic Input Current I IN 40 C < T A < +85 C µa DYNAMIC PERFORMANCE Slew Rate SR R L = 2 kω 3.5 V/µs Settling Time t S To 0.0%.4 µs Gain Bandwidth Product GBP 2.2 MHz Phase Margin Φo 67 Degrees Channel Separation CS f = khz, R L = 2 kω 65 db NOISE PERFORMANCE Voltage Noise Density e n f = khz 45 nv/ Hz f = 0 khz 30 nv/ Hz Current Noise Density i n f = khz 0.05 pa/ Hz Specifications subject to change without notice. (V S = +2.7 V, V CM = +.35 V, T A = +25 C unless otherwise noted) 2 REV. A

4 AD859/AD8592/AD8594 ABSOLUTE MAXIMUM RATINGS Supply Voltage V Input Voltage GND to V S Differential Input Voltage ±6 V Output Short Circuit Duration to GND Observe Derating Curves Storage Temperature Range R, RT, RM, RU Packages C to +50 C Operating Temperature Range AD859/AD8592/AD C to +85 C Junction Temperature Range R, RT, RM, RU Packages C to +50 C Lead Temperature Range (Soldering, 60 sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For supplies less than ± 5 V the differential input voltage is limited to the supplies. Package Type JA JC Units 6-Lead SOT-23 (RT) C/W 0-Lead µsoic (RM) C/W 6-Lead SOIC (R) C/W 6-Lead TSSOP (RU) C/W NOTE θ JA is specified for worst case conditions, i.e., θ JA is specified for device in socket for surface mount packages. ORDERING GUIDE Temperature Package Package Model Range Description Option AD859ART 40 C to +85 C 6-Lead SOT-23 RT-6 AD8592ARM 40 C to +85 C 0-Lead µsoic RM-0 AD8594AR 40 C to +85 C 6-Lead SOIC R-6A AD8594ARU 40 C to +85 C 6-Lead TSSOP RU-6 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD859/AD8592/AD8594 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE Typical Performance Characteristics OUTPUT VOLTAGE mv k 00 0 V S = +2.7V T A = +25 C SOURCE SINK OUTPUT VOLTAGE mv 0k k 00 0 V S = +5V T A = +25 C SOURCE SINK SUPPLY CURRENT/AMPLIFIER ma V S = +5V V S = +2.7V LOAD CURRENT ma Figure. Output Voltage to Supply Rail vs. Load Current k LOAD CURRENT ma Figure 2. Output Voltage to Supply Rail vs. Load Current k TEMPERATURE C Figure 3. Supply Current per Amplifier vs. Temperature 4 REV. A

5 QUESTION [25 marks] Figure (a) shows a bridge amplifier which amplifies the input voltage, v In and applies the result differentially across a load, Z L. This bridge-coupling is used to maximise the voltage swing across the load, v L. Some known circuit parameters are shown in figure (b). A partial datasheet for the operational amplifier (AD8592) used in the circuit can be found at the beginning of this exam paper. R R 2 v In R 3 AD R 4 i L v L Z L AD (a) Parameter Value Supply voltages.5v V EE.5V Known resistances R 0kΩ R 2 90kΩ (b) Figure : Bridge-coupled op-amp amplifier (a). Key circuit parameters (b). (A) What is the maximum voltage the circuit can apply (undistorted) to the load, v L,max? (B) Find suitable values for R 3 and R 4 such that the (undistorted) load voltage is maximised. In the following, it is assumed that v L,max = 2.5V. (C) Discuss how the load impedance, Z L should be chosen, to maximise the power delivered to the load, P L. In the following, it is assumed that R 3 = 0kΩ and R 4 = 90kΩ. It is further assumed that V In is a zero-dc sinusoidal signal of amplitude V IA. (D) Find the maximum input amplitude, V IA,max that ensures the output is not clipped (undistorted). In the following, it is assumed that the load impedance is resistive with Z L = 00Ω. It is further assumed that the minimum signal frequency is f min = 50kHz. The large operational amplifier offset voltage can cause DC power dissipation well above the maximum signal power delivered to the load. (E) Improve the circuit such that there is no DC power being wasted in the load. 5

6 QUESTION 2 [25 marks] Elements of a portable mixed analogue-digital system are shown in Figure 2(a). The system is powered by two.5 V batteries, generating supply voltages =.5V, V EE =.5V, and ground. The digital sub-system uses low-voltage CMOS logic whose static parameters are shown in Figure 2(b). The output of the amplifier is fed to the logic via an A/D converter which is modelled as a simple capacitor (C L ) in this question. A partial datasheet for the operational amplifier (AD8592) used in the system can be found at the beginning of this exam paper. v In 0kΩ R R 2 V EE 90kΩ 2 AD8592 C L 00pF LVCMOS (a) Parameter Value Output high voltage V OH.3V Output low voltage V OL 0.2V Max output current I O 0mA Input high voltage V IH 0.9V Input low voltage V IL 0.6V Max input current I I µa (b) Figure 2: Mixed analogue/digital system (a). Key gate parameters (b). A four-layer PCB is to be designed for the system. (A) Explain the key elements of a good power supply layout for the PCB. The operational amplifier (op-amp) has grounded supply decoupling capacitors on both its power supplies; these must ensure that the op-amp supply voltages change less than V = 5mV if a 00 mv step is applied at the amplifier input v In. (B) Find suitable values for the op-amps supply decoupling capacitors. The digital sub-system causes a v cc = 50mV noise voltage of low-frequency on the op-amp power supply. Due to the op-amps finite power supply rejection, this appears as an apparent input signal, v in. (C) Find v in. In the following, it is assumed that noise sources in the system cause an equivalent peak input noise voltage of v in = 0.5mV. The A/D converter in the system is assumed to have an input voltage range of [ V;V]. (D) Explain how many bits resolution, B, you would choose for the A/D converter. The op-amp has a shut-down signal (SDA) which must be controlled by the logic sub-system. (E) Design a circuit that allows the logic to control SDA appropriately. [Hint: use a transistor circuit as level translator.] 6

7 QUESTION 3 [25 marks] Figure 3(a) shows a front-end circuit used in a heart-rate monitor. The LED (D ) is flashed on/off at a constant frequency by the U gate. The LED light is subsequently reflected by a person s skin and picked up by the photo-transistor (Q ) whose output voltage v S is amplified and filtered by the following circuit yielding the output voltage v O. The power-supply voltages used in the system is =.5V and V EE =.5V. U is a CMOS-type gate and is assumed to have and equivalent output resistance in the range R O,U [0Ω;20Ω] in both high and low states. R U V EE D ck R 2 R 4 R 5 C 2 v O 50mV 0mV VEE v S Q C v I R 3 V EE U 2 v O 50mV (a) 5.ms 5.2ms t (b) Figure 3: Heart-rate monitor front-end (a). SPICE simulation plot (b). D has a forward voltage in the range V F [.8V;2.2V] and need a current in the range I D [0 ma; 20 ma] when on. (A) Find a suitable value for R. The R 2 value is chosen small (R 2 R 3 ) such that the output impedance of the photo-transistor stage (v S ) is small and can be ignored. (B) Find an expression for the filter transfer function H(s) = v O /v S. The filter section is now simulated in SPICE. Figure 3(b) shows a plot of the simulated output voltage (v O ) when a small 4 khz sinusoidal signal is applied to the filter input (v S ). The simulation result is not quite what would be expected. (C) Explain what might be the cause of the unexpected simulation result. In the cause of simulating EMI performance of the circuit, it is discovered that the SPICE model used for the operational amplifier does not include proper modelling of its power-supply rejection ratio (PSRR). A realistic power-supply rejection ratio can be modelled in SPICE by adding components around the operational amplifier. (D) Explain how you would model the PSRR in the operational amplifier. A failure-mode and effects analysis is carried out on the circuit. Simple open-circuit / shortcircuit failure modes are used for discrete components (eg. capacitors). (E) Analyse the effects of C failing. 7

8 QUESTION 4 [25 marks] Figure 4(a) shows an electronic system powered from a single AA NiMH cell whose discharge profile is shown in Figure 4(b). The system consists of a logic sub-system powered directly from the battery voltage V C and an analogue sub-system which requires a dual supply voltage, = V C and V EE = V C (the analogue sub-system does not have any current flowing in the ground node). V EE is generated by the power supply unit (PSU) whose power efficiency is η = I PSO V PSO /(I PSI V PSI ) = 80%. The analogue sub-system makes use of the AD8592 operational amplifier (op-amp) whose partial datasheet can be found at the beginning of this exam paper. V C I C I CCA I CCD V PSI I PSI logic PSU 0A VCC analogue AD8592 V L V PSO R L IL I PSO V EE (a) V C.3V.2V.V.0V 250mA 2.5A 625mA 2h 4h 6h 8h 0h (b) t Figure 4: Battery powered electronic system (a). NiMH AA cell discharge profile (b). The analogue and digital supply currents are I CCD = 00mA and I CCA = 300mA respectively. (A) Find the battery current, I C. In the following, it is assumed that the battery current is I C = 750mA. It is further assumed that the minimum allowed battery voltage is dictated by the op-amp specifications. (B) Find the system battery life time, t B and comment on the choice of supply voltages. In the analogue sub-system, two op-amps (AD8592) are used in bridge configuration to apply a voltage, V L across a resistive load, R L = 5Ω as shown in the figure. The maximum voltage applied across the load is V L,max = V. The op-amps may be assumed to have ideal class C output stages and their bias currents can be ignored. Also, it may be assumed the voltage across R L is applied symmetrical with respect to ground. (C) Find the maximum power being dissipated in each op-amp, P OA,max. In the following it is assumed that the maximum power being dissipated in each op-amp is P OA,max = 200mW. The two op-amps in the system share a µsoic package and need to operate with a maximum ambient temperature of T A = 60 C. (D) Explain if it is necessary to use a heat sink on the op-amp package. (E) Explain the operating principle of a possible implementation of the power supply unit (PSU) used in the system. END OF EXAMINATION PAPER 8