FEATURES DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO. LTC Linear Phase, 8th Order Lowpass Filter

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LTC6-7 Linear Phase, th Order Lowpass Filter FETRES Steeper Roll-Off Than th Order essel Filters f CTOFF up to khz Phase Equalized Filter in -Pin Package Phase and Group Delay Response Fully Tested

1 LTC6-7 Linear Phase, th Order Lowpass Filter FETRES Steeper Roll-Off Than th Order essel Filters f CTOFF up to khz Phase Equalized Filter in -Pin Package Phase and Group Delay Response Fully Tested Transient Response Exhibits % Overshoot and No Ringing Wide Dynamic Range 7d THD or etter Throughout a khz Passband No External Components Needed vailable in -Pin DIP and 6-Pin SO Wide Packages PPLICTIO S Data Communication Filters Time Delay Networks Phase-Matched Filters DESCRIPTIO The LTC 6-7 is a clock-tunable monolithic th order lowpass filter with linear passband phase and flat group delay. The amplitude response approximates a maximally flat passband while it exhibits steeper roll-off than an equivalent th order essel filter. For instance, at twice the cutoff frequency the filter attains d attenuation (vs d for essel), while at three times the cutoff frequency, the filter attains 6d attenuation (vs d for essel). The cutoff frequency of the LTC6-7 is tuned via an external TTL or CMOS clock. The LTC6-7 features wide dynamic range. With single V supply, the S/N + THD is 76d. Optimum 9d S/N is obtained with ±7.V supplies. The clock-to-cutoff frequency ratio of the LTC6-7 can be set to : (Pin to V + ) or : (Pin to V ). When the filter operates at clock-to-cutoff frequency ratio of :, the input is double-sampled to lower the risk of aliasing. The LTC6-7 is pin-compatible with the LTC6-X series, LTC6-7 and LTC6-7., LTC and LT are registered trademarks of Linear Technology Corporation. ll other trademarks are the property of their respective owners. TYPICL PPLICTIO khz Linear Phase Lowpass Filter Eye Diagram V IN 7.V 6 7 LTC V CLK = MHz 7.V V OT V/DIV 6-7 T NOTE: THE POWER SPPLIES SHOLD E YPSSED Y.µF CPCITOR CLOSE TO THE PCKGE ND NY PRINTED CIRCIT ORD SSEMLY SHOLD MINTIN DISTNCE OF T LEST. INCHES ETWEEN NY OTPT OR INPT PIN ND THE f CLK LINE. V S = ±7.V f CLK = MHz RTIO = : µs/div 6-7 T 67fb

2 LTC6-7 SOLTE XI RTI GS W W W Total Supply Voltage (V + to V )... 6.V Power Dissipation... mw urn-in Voltage... 6.V Voltage at ny Input... (V.V) V IN (V + +.V) Storage Temperature Range... 6 C to C (Note ) Operating Temperature Range LTC6-7C... C to C LTC6-7M OSOLETE... C to C Lead Temperature (Soldering, sec)... C PCKGE/ORDER I FOR NC V IN GND V + GND LP () INV () 6 7 TOP VIEW 9 N PCKGE -LED PLSTIC DIP T JMX = C, θ J = 6 C/W (N) J PCKGE -LED CERMIC DIP T JMX = C, θ J = 6 C/W (J) OSOLETE PCKGE R IN () NC V f CLK / V OT NC W TIO ORDER PRT NMER LTC6-7CN LTC6-7CJ LTC6-7MJ NC V IN GND V + GND NC LP () INV () 6 7 TOP VIEW 6 R IN () NC V NC f CLK / NC 9 V OT SW PCKGE 6-LED PLSTIC SO (WIDE) T JMX = C, θ J = C/W Consider the N Package as an lternate Source Order Options Tape and Reel: dd #TR Lead Free: dd #PF Lead Free Tape and Reel: dd #TRPF Lead Free Part Marking: Consult LTC Marketing for parts specified with wider operating temperature ranges. ORDER PRT NMER LTC6-7CSW ELECTRICL CHRCTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = C.V S = ±7.V, R L = k, T = C, f CTOFF = khz or khz, f CLK = MHz, TTL or CMOS level (maximum clock rise and fall time µs) and all gain measurements are referenced to passband gain, unless otherwise specified. The filter cutoff frequency is abbreviated as f CTOFF or f C. PRMETER CONDITIONS MIN TYP MX NITS Passband Gain.Hz f. f CTOFF f TEST = khz, (f CLK /f C ) = :.6..6 d Gain at. f CTOFF f TEST = khz, (f CLK /f C ) = :.9.. d f TEST = khz, (f CLK /f C ) = :... d Gain at.7 f CTOFF f TEST = khz, (f CLK /f C ) = :... d Gain at f CTOFF f TEST = khz, (f CLK /f C ) = :... d f TEST = khz, (f CLK /f C ) = :.7..7 d Gain at f CTOFF f TEST = khz, (f CLK /f C ) = : d f TEST = khz, (f CLK /f C ) = : d Gain with f CLK = khz f TEST = Hz, (f CLK /f C ) = : 6... d Gain with f CLK = khz, V S = ±.7V f TEST = khz, (f CLK /f C ) = :.9.. d f TEST = khz, (f CLK /f C ) = :... d Phase Factor (F ).Hz f f CTOFF Phase = F (f/f C ) (f CLK /f C ) = : ±. Deg (Note ) (f CLK /f C ) = : ±. Deg (f CLK /f C ) = : 7 Deg (f CLK /f C ) = : 9 Deg 67fb

3 ELECTRICL CHRCTERISTICS LTC6-7 The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = C. V S = ±7.V, R L = k, f CTOFF = khz or khz, f CLK = MHz, TTL or CMOS level (maximum clock rise and fall time µs) and all gain measurements are referenced to passband gain, unless otherwise specified. The filter cutoff frequency is abbreviated as f CTOFF or f C. PRMETER CONDITIONS MIN TYP MX NITS Phase Nonlinearity (f CLK /f C ) = : ±. % (Notes, ) (f CLK /f C ) = : ±. % (f CLK /f C ) = : ±. % (f CLK /f C ) = : ±. % Group Delay (t d ) (f CLK /f C ) = :, f f CTOFF 9.7 ±. µs t d = (F /6)(/f C ) (f CLK /f C ) = :, f f CTOFF 7. ±. µs (Note ) (f CLK /f C ) = :, f f CTOFF µs (f CLK /f C ) = :, f f CTOFF µs Group Delay Deviation (f CLK /f C ) = :, f f CTOFF ±. % (Notes, ) (f CLK /f C ) = :, f f CTOFF ±. % (f CLK /f C ) = :, f f CTOFF ±. % (f CLK /f C ) = :, f f CTOFF ±. % Input Frequency Range (Table 9) (f CLK /f C ) = : <f CLK khz (f CLK /f C ) = : <f CLK / khz Maximum f CLK V S = V (GND = V). MHz V S = ±V. MHz V S = ±7.V. MHz Clock Feedthrough (f f CLK ) : µv RMS Wideband Noise V S = ±.V 9 ± % µv RMS (Hz f f CLK ) V S = ±V ± % µv RMS V S = ±7.V ± % µv RMS Input Impedance 7 kω Output DC Voltage Swing V S = ±.7V ±. ±. V (Note ) V S = ±V ±. ±. V V S = ±7.V ±. ±. V Output DC Offset :, V S = ±V ± ± mv :, V S = ±V ± mv Output DC Offset TempCo :, V S = ±V ± µv/ C :, V S = ±V ± µv/ C Power Supply Current V S = ±.7V, T = C m m V S = ±V, T = C 6 m m V S = ±7.V, T = C 7 m m Power Supply Range ±.7 ± V 67fb

4 LTC6-7 ELECTRICL CHRCTERISTICS Note : bsolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : Input frequencies, f, are linearly phase shifted through the filter as long as f f C ; f C = cutoff frequency. Figure curve shows the typical phase response of an LTC6-7 operating at f CLK = MHz, ratio = :, f C = khz and it closely matches an ideal straight line. The phase shift is described by: phase shift = F (f/f C ); f f C. F is arbitrarily called the phase factor expressed in degrees. The phase factor allows the calculation of the phase at a given frequency. Example: The phase shift at khz of the LTC6-7 shown in Figure is: phase shift = (khz/khz) ± nonlinearity = ± % or ±.. Note : Group delay and group delay deviation are calculated from the measured phase factor and phase deviation specifications. Note : Phase deviation and group delay deviation for LTC6-7MJ is ±%. Note : The C swing is typically V P-P, 7V P-P,.V P-P, with ±7.V, ±V, ±.V Supply respectively. For more information refer to the THD + Noise vs Input graphs. 9 f CLK = MHz RTIO = : PHSE (DEG) F Figure. Phase Response in the Passband (Note ) 67fb

5 TYPICL PERFOR W CE CHRCTERISTICS LTC6-7 GIN (d) 6 7 Gain vs Frequency : 9 V S = ±V f CLK = MHz T = C. : 6-7 G PHSE FCTOR 7 6. Phase Factor vs f CLK (Typical nit) V S = ±V (f CLK /f C ) = : C 7 C C f CLK (MHz) 6-7 G PHSE FCTOR 7 6. Phase Factor vs f CLK (Typical nit) V S = ±V (f CLK /f C ) = : C 7 C C f CLK (MHz) 6-7 G Phase Factor vs f CLK (Min and Max Representative nits) V S = ±V T = C (f CLK /f C ) = : Phase Factor vs f CLK (Min and Max Representative nits) V S = V T = C PINS, T V (f CLK /f C ) = : PHSE FCTOR PHSE FCTOR f CLK (MHz)... f CLK (MHz). 6-7 G 6-7 G Passband Gain and Phase V S = ±V f CLK = MHz (f CLK /f C ) = : 6 Passband Gain and Phase V S = ±V f CLK = MHz (f CLK /f C ) = : 6 GIN (d) PHSE GIN 6 PHSE (DEG) GIN (d) PHSE GIN 6 PHSE (DEG) G6 6-7 G7 67fb

6 LTC6-7 TYPICL PERFOR W CE CHRCTERISTICS GIN (d) Passband Gain vs Frequency and f CLK V S = ±7.V T = C (f CLK /f C ) = : C. f CLK = MHz. f CLK = MHz C. f CLK = MHz D. f CLK = MHz E. f CLK = MHz E D 6-7 G GIN (d) Passband Gain vs Frequency and f CLK at T = C V S = ±7.V (f CLK /f C ) = : C. f CLK = MHz. f CLK = MHz C. f CLK = MHz D. f CLK = MHz E. f CLK = MHz E D 6-7 G9 GIN (d) Passband Gain vs Frequency and f CLK at T = C V S = ±V (f CLK /f C ) = :. f CLK =.MHz. f CLK =.MHz C. f CLK =.MHz D. f CLK =.MHz C D 6-7 G GIN (d) Passband Gain vs Frequency and f CLK V S = SINGLE V T = C (f CLK /f C ) = :. f CLK =.MHz. f CLK =.MHz C. f CLK =.MHz D. f CLK =.MHz C D 6-7 G GIN (d) Passband Gain vs Frequency and f CLK at T = C V S = SINGLE V (f CLK /f C ) = :. f CLK =.MHz. f CLK =.MHz C. f CLK =.MHz D. f CLK =.MHz C D 6-7 G DELY (µs) 7 Delay vs Frequency and f CLK C D V S = ±V T = C (f CLK /f C ) = :. f CLK =.MHz. f CLK =.MHz C. f CLK =.MHz D. f CLK =.MHz G 7 DELY (µs) Delay vs Frequency and f CLK C V S = ±V T = C (f CLK /f C ) = :. f CLK =.MHz. f CLK =.MHz C. f CLK =.MHz D. f CLK =.MHz THD + Noise vs Frequency V S = ±7.V V IN = V RMS f CLK = MHz (f CLK /f C ) = : (k RESISTOR PIN 9 TO V ) THD + Noise vs Frequency V S = ±7.V V IN = V RMS f CLK =.MHz (f CLK /f C ) = : (k RESISTOR PIN 9 TO V ) D G 6-7 G 6-7 G6 6 67fb

7 TYPICL PERFOR W CE CHRCTERISTICS LTC THD + Noise vs Frequency V S = ±V V IN = V RMS f CLK = MHz (f CLK /f C ) = : (k RESISTOR PIN 9 TO V ) THD + Noise vs Frequency V S = SINGLE V V IN =.V RMS f CLK = MHz (f CLK /f C ) = : (PINS, T V) THD + Noise vs Frequency V S = SINGLE V V IN =.V RMS f CLK = khz (f CLK /f C ) = : (PINS, T V) G7 6-7 G 6-7 G THD + Noise vs Input f IN = khz f CLK = MHz (f CLK /f C ) = : (k PIN 9 TO V ). V S = ±V. V S = ±7.V THD + Noise vs Input f IN = khz f CLK = MHz (f CLK /f C ) = :. V S = ±V. V S = ±7.V V S = SINGLE V f IN = khz f CLK = MHz (f CLK /f C ) = : THD + Noise vs Input 9. INPT (V RMS ) 9. INPT (V RMS ) 9.. PINS, T V. PINS, T.V INPT (V RMS ) 6-7 G 6-7 G 6-7 G THD + Noise vs Input V S = SINGLE V f IN = khz f CLK = khz (f CLK /f C ) = :. PINS, T V. PINS, T.V INPT (V RMS ) PHSE DIFFERENCE (DEG) Phase Matching vs Frequency PHSE DIFFERENCE ETWEEN NY TWO NITS (SMPLE OF REPRESENTTIVE NITS) V S ±V f CLK.MHz (f CLK /f C ) = : OR : T = C TO 7 C FREQENCY (f CTOFF /FREQENCY) POWER SPPLY CRRENT (m) 6 6 Power Supply Current vs Power Supply Voltage f CLK = MHz C C C 6 6 TOTL POWER SPPLY VOLTGE (V) 6-7 G 6-7 G 6-7 G 67fb 7

8 LTC6-7 TYPICL PERFOR W Table. Passband Gain and Phase V S = ±7.V, (f CLK /f C ) = :, T = C Table. Passband Gain and Phase V S = ±7.V, (f CLK /f C ) = :, T = C CE CHRCTERISTICS GIN (d) PHSE (DEG) f CLK = MHz (Typical nit) f CLK = MHz (Typical nit) f CLK = MHz (Typical nit) f CLK = MHz (Typical nit) f CLK = MHz (Typical nit) GIN (d) PHSE (DEG) f CLK = MHz (Typical nit) f CLK = MHz (Typical nit) f CLK = MHz (Typical nit) GIN (d) PHSE (DEG) f CLK = MHz (Typical nit) f CLK = MHz (Typical nit) Table. Passband Gain and Phase V S = ±V, (f CLK /f C ) = :, T = C GIN (d) PHSE (DEG) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) fb

9 TYPICL PERFOR W Table. Passband Gain and Phase V S = ±V, (f CLK /f C ) = :, T = C Table. Passband Gain and Phase V S = ±V, (f CLK /f C ) = :, T = C CE CHRCTERISTICS GIN (d) PHSE (DEG) f CLK =.MHz (Typical nit) GIN (d) PHSE (DEG) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) f CLK =.MHzMHz (Typical nit) Table. Passband Gain and Phase V S = Single V, (f CLK /f C ) = :, T = C LTC6-7 GIN (d) PHSE (DEG) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) Table 6. Passband Gain and Phase V S = Single V, (f CLK /f C ) = :, T = C GIN (d) PHSE (DEG) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) f CLK =.MHz (Typical nit) f CLK = MHz (Typical nit) fb 9

10 LTC6-7 PI F CTIO S Power Supply Pins (, ) The V + (Pin ) and the V (Pin ) should be bypassed with a.µf capacitor to an adequate analog ground. The filter s power supplies should be isolated from other digital or high voltage analog supplies. low noise linear supply is recommended. sing a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than V/µs. When V + is applied before V and V is allowed to go above ground, a signal diode should clamp V to prevent latch-up. Figures and show typical connections for dual and single supply operation. V IN V + V IN V +.µf 6 7 LTC6-7 V.µF Ω CLOCK SORCE V GND DIGITL SPPLY V OT 6-7 F Figure. Dual Supply Operation for an f CLK /f CTOFF = : k k.µf µf LTC6-7 Figure. Single Supply Operation for an f CLK /f CTOFF = : Clock Input Pin () ny TTL or CMOS clock source with a square-wave output and % duty cycle (±%) is an adequate clock source for the device. The power supply for the clock source should not be the filter s power supply. The analog ground 9 Ω V + CLOCK SORCE GND + DIGITL SPPLY V OT 6-7 F for the filter should be connected to clock s ground at a single point only. Table 7 shows the clock s low and high level threshold values for a dual or single supply operation. pulse generator can be used as a clock source provided the high level ON time is greater than.µs. Sine waves are not recommended for clock input frequencies less than khz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time µs). The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal path. Ω resistor between clock source and pin will slow down the rise and fall times of the clock to further reduce charge coupling (Figures and ). Table 7. Clock Source High and Low Threshold Levels POWER SPPLY HIGH LEVEL LOW LEVEL Dual Supply = ±7.V.V.V Dual Supply = ±V.V.V Dual Supply = ±.V.7V.V Single Supply = V 7.V 6.V Single Suppl = V.V.V nalog Ground Pins (, ) The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, Pin should be connected to the analog ground plane. For single supply operation pin should be biased at / supply and should be bypassed to the analog ground plane with at least a µf capacitor (Figure ). For single V operation at the highest f CLK of MHz, Pin should be biased at V. This minimizes passband gain and phase variations. Ratio Input Pin () The DC level at this pin determines the ratio of the clock frequency to the cutoff frequency of the filter. Pin at V + gives a : ratio and Pin at V gives a : ratio. For single supply operation the ratio is : when Pin is at V + and : when Pin is at ground. When Pin is not tied to ground, it should be bypassed to analog ground 67fb

11 LTC6-7 PI F CTIO S with a.µf capacitor. If the DC level at Pin is switched mechanically or electrically at slew rates greater than V/µs while the device is operating, a k resistor should be connected between Pin and the DC source. Filter Input Pin () The input pin is connected internally through a k resistor tied to the inverting input of an op amp. Filter Output Pins (9, 6) Pin 9 is the specified output of the filter; it can typically source m and sink m. Driving coaxial cables or resistive loads less than k will degrade the total harmonic distortion of the filter. When evaluating the device s distortion an output buffer is required. noninverting buffer, Figure, can be used provided that its input common mode range is well within the filter s output swing. Pin 6 is an intermediate filter output providing an unspecified 6th order lowpass filter. Pin 6 should not be loaded. PPLICTI O S Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter s output pin (9). The clock feedthrough is tested with the input pin () grounded and it depends on PC board layout and on the value of the power supplies. With proper layout techniques the values of the clock feedthrough are shown in Table. Table. Clock Feedthrough I FOR W TIO V S : : Single V 9µV RMS µv RMS ±V µv RMS µv RMS ±7.V µv RMS 6µV RMS Note: The clock feedthrough at single V is imbedded in the wideband noise of the filter. Clock waveform is a square wave. ny parasitic switching transients during the rise and fall edges of the incoming clock are not part of the clock feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their External Connection Pins (7, ) Pins 7 and should be connected together. In a printed circuit board the connection should be done under the IC package through a short trace surrounded by the analog ground plane. NC Pins (,,, ) Pins,, and are not connected to any internal circuit point on the device and should preferably be tied to analog ground. k + LT 6-7 F Figure. uffer for Filter Output amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. The clock feedthrough, if bothersome, can be greatly reduced by adding a simple R/C lowpass network at the output of the filter pin (9). This R/C will completely eliminate any switching transients. Wideband Noise The wideband noise of the filter is the total RMS value of the device s noise spectral density and it is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter passband and it cannot be reduced with post filtering. For instance, the LTC6-7 wideband noise at ±V supply is µv RMS, 9µV RMS of which have frequency contents from DC up to the filter s cutoff frequency. The total wideband noise (µv RMS ) is nearly independent of the value of the clock. The clock feedthrough specifications are not part of the wideband noise. 67fb

LTC6-7 PPLICTI O S I FOR W TIO Speed Limitations To avoid op amp slew rate limiting at maximum clock frequencies, the signal amplitude should be kept below a specified level as shown in Table 9.

12 LTC6-7 PPLICTI O S I FOR W TIO Speed Limitations To avoid op amp slew rate limiting at maximum clock frequencies, the signal amplitude should be kept below a specified level as shown in Table 9. Transient Response Table 9. Maximum V IN vs V S and Clock POWER SPPLY MXIMM f CLK MXIMM V IN ±7.V.MHz.V RMS (f IN > khz).mhz.v RMS (f IN > khz).mhz.7v RMS (f IN > khz).mhz.v RMS (f IN > khz) ±V.MHz.6V RMS (f IN > khz).mhz.7v RMS (f IN > khz) Single V.MHz.V RMS (f IN > khz) Table. Transient Response of LTC Lowpass Filters DELY RISE SETTLING OVER- TIME* TIME** TIME*** SHOOT LOWPSS FILTER (SEC) (SEC) (SEC) (%) LTC6- essel./f C./f C./f C. LTC6- essel./f C./f C./f C LTC6-6 essel./f C./f C./f C LTC6-7 Linear Phase./f C.6/f C./f C LTC6-7 Linear Phase./f C.9/f C./f C LTC6-7 Linear Phase./f C.9/f C./f C LTC6- utterworth./f C./f C./f C LTC6-6 Elliptic./f C./f C./f C LTC6- Elliptic.9/f C./f C./f C LTC6- Elliptic./f C./f C 6./f C * To % ±%, ** % to 9% ±%, *** To % ±.% Table. liasing (f CLK = khz) INPT FREQENCY OTPT LEVEL OTPT FREQENCY (V IN = V RMS, (Relative to Input, (liased Frequency f IN = f CLK ± f OT ) d = V RMS ) f OT = S [f CLK ± f IN ]) (khz) (d) (khz) :, f CTOFF = khz 9 (or ) (or ) (or ) (or ).. 9 (or ) (or.).. :, f CTOFF = khz 97 (or ) (or.).. 9 (or ) (or.) (or ) (or.).7. V/DIV INPT liasing V S = ±7.V, f IN = khz ± V f CLK = MHz, RTIO = : 9% % % td ts µs/div Figure..9 RISE TIME (t r ) = ±% f CTOFF. SETTLING TIME (t s ) = ±% f (TO % of OTPT) CTOFF DELY TIME (t d ) = GROP DELY (TO % OF OTPT) tr Figure 6.. f CTOFF 6-7 F OTPT 6-7 F6 liasing is an inherent phenomenon of sampled data systems and it occurs when input frequencies close to the sampling frequency are applied. For the LTC6-7 case at :, an input signal whose frequency is in the range of f CLK ±%, will be aliased back into the filter s passband. If, for instance, an LTC6-7 operating with a khz clock and khz cutoff frequency receives a 9kHz, mv input signal, a khz, µv RMS alias signal will appear at its output. When the LTC6-7 operates with a clock-tocutoff frequency of :, aliasing occurs at twice the clock frequency. Table shows details. 67fb

13 LTC6-7 PCKGE DESCRIPTIO J Package -Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # --). (.7) MIN.7 (9.99) MX 9. (.6) RD TYP.. (. 7.7). SC (7.6 SC) 6 7. (.) MX..6 (..).. (..7)..6 (..6) NOTE: LED DIMENSIONS PPLY TO SOLDER DIP/PLTE OR TIN PLTE LEDS..6 (.6.66). (.) SC. (.7) MIN J OSOLETE PCKGE 67fb

14 LTC6-7 PCKGE DESCRIPTIO N Package -Lead PDIP (Narrow. Inch) (Reference LTC DWG # --).77* (9.) MX 9. ±.* (6.77 ±.) (7.6.). ±. (. ±.7)..6 (..6).. (..) ( ). (.) MIN. (.) MIN. (.7) MIN NOTE: INCHES. DIMENSIONS RE MILLIMETERS *THESE DIMENSIONS DO NOT INCLDE MOLD FLSH OR PROTRSIONS. MOLD FLSH OR PROTRSIONS SHLL NOT EXCEED. INCH (.mm). (.) SC.6 (.6) TYP. ±. (.7 ±.76) N 67fb

15 LTC6-7 PCKGE DESCRIPTIO SW Package 6-Lead Plastic Small Outline (Wide. Inch) (Reference LTC DWG # --6). ±. TYP N. SC. ±..9. (.9.9) NOTE 6 9 N. MIN. ±. NOTE.9.9 (.7.6) N/ N/ RECOMMENDED SOLDER PD LYOT 6 7. (.7) RD MIN.9.99 ( ) NOTE..9 (..77) TYP.9. (.6.6).7. (.9.)..9. (.7) (.9.) NOTE SC (.6.) (.6.7) TYP NOTE: INCHES. DIMENSIONS IN (MILLIMETERS). DRWING NOT TO SCLE. PIN IDENT, NOTCH ON TOP ND CVITIES ON THE OTTOM OF PCKGES RE THE MNFCTRING OPTIONS. THE PRT MY E SPPLIED WITH OR WITHOT NY OF THE OPTIONS. THESE DIMENSIONS DO NOT INCLDE MOLD FLSH OR PROTRSIONS. MOLD FLSH OR PROTRSIONS SHLL NOT EXCEED.6" (.mm).. (..) S6 (WIDE) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 67fb

16 LTC6-7 TYPICL PPLICTIO khz Linear Phase Lowpass Filter Eye Diagram V IN 7.V 6 7 LTC V CLK = MHz 7.V V OT V/DIV 6-7 T NOTE: THE POWER SPPLIES SHOLD E YPSSED Y.µF CPCITOR CLOSE TO THE PCKGE ND NY PRINTED CIRCIT ORD SSEMLY SHOLD MINTIN DISTNCE OF T LEST. INCHES ETWEEN NY OTPT OR INPT PIN ND THE f CLK LINE. V S = ±7.V f CLK = MHz RTIO = : µs/div 6-7 T RELTED PRTS PRT NMER DESCRIPTION COMMENTS LTC6 niversal Filter uilding lock llows for andpass (p to khz) sing External Resistors LTC6-/// th Order Low Pass Filters, F O Max = khz Elliptic, utterworth, essel, Cauer LTC6 niversal Filter uilding lock llows for andpass (p to khz) sing External Resistors LTC6-/6/7 th Order Low Pass Filters, F O Max = khz utterworth, essel or Elliptic LTC6 niversal Filter uilding lock llows for andpass (p to khz) sing External Resistors LTC6-7 th Order Low Pass Filter, F O Max = khz Flat Group Delay, High Speed Lowpass Filter LT66-. Low Noise Differential mp and MHz Lowpass µv RMS Noise khz to MHz V Supply LT66- Low Noise Differential mp and MHz Lowpass 6µV RMS Noise khz to MHz V Supply 6 LT/LT 9 REV PRINTED IN S Linear Technology Corporation 6 McCarthy lvd., Milpitas, C 9-77 () -9 FX: () -7 LINER TECHNOLOGY CORPORTION 99 67fb

FEATURES TYPICAL APPLICATIO. LTC Low Power 8th Order Pin Selectable Butterworth or Bessel Lowpass Filter DESCRIPTIO APPLICATIO S

FEATURES TYPICAL APPLICATIO. LTC Low Power 8th Order Pin Selectable Butterworth or Bessel Lowpass Filter DESCRIPTIO APPLICATIO S FEATRES Pin Selectable Butterworth or Bessel Response ma Supply Current with ±V Supplies f CTOFF up to khz µv RMS Wideband Noise THD