DESCRIPTIO LTC1543. Software-Selectable Multiprotocol Transceiver FEATURES APPLICATIO S TYPICAL APPLICATIO

Transcription

1 LTC FETRES Software-Selectable Transceiver Supports: RS, RS, EI0, EI0-, V., V., X. TV/Detecon Inc. Certified NET and NET Compliant (Test Report No. NET/0/) TR Compliant (Test Report No. CTR/00/) Software-Selectable Cable Termination sing the LTC Complete DTE or DCE Port with LTC, LTC Operates from Single V Supply PPLICTIO S Data Networking CS and DS Data Routers Software-Selectable Multiprotocol Transceiver DESCRIPTIO The LTC is a -driver/-receiver multiprotocol transceiver that operates from a single V supply. The LTC and LTC form the core of a complete softwareselectable DTE or DCE interface port that supports the RS, RS, EI0, EI0-, V., V. or X. protocols. Cable termination may be implemented using the LTC software-selectable cable termination chip or by using existing discrete designs. The LTC runs from a single V supply using an internal charge pump that requires only five space-saving surface mounted capacitors. The part is available in a -lead SSOP surface mount package., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICL PPLICTIO DTE or DCE Multiprotocol Serial Interface with D- Connector LL CTS DSR DCD DTR RTS RXD RXC TXC SCTE TXD LTC LTC D R R D D D R D D D LTC 0 TXD () TXD SCTE () SCTE TXC () TXC RXC () RXC RXD () RXD SG () SHIELD () RTS () RTS DTR () DTR DCD () DCD DSR () DSR CTS () CTS LL () D- CONNECTOR T0 sn fas

2 LTC SOLTE XI RTI GS W W W (Note ) Supply Voltage....V Input Voltage Transmitters... 0.V to ( + 0.V) Receivers... V to V Logic Pins... 0.V to ( + 0.V) Output Voltage Transmitters... ( 0.V) to (V DD + 0.V) Receivers... 0.V to ( + 0.V) Logic Pins... 0.V to ( + 0.V)... V to 0.V V DD... 0.V to V Short-Circuit Duration Transmitter Output... Indefinite Receiver Output... Indefinite... 0 sec Operating Temperature Range LTCC... 0 C to 0 C LTCI... 0 C to C Storage Temperature Range... C to 0 C Lead Temperature (Soldering, sec) C The denotes specifications which apply over the full operating tempera- ELECTRICL CHRCTERISTICS ture range. = V (Notes, ) W PCKGE/ORDER I FOR TIO C C + V DD D D D R M TOP VIEW CHRGE PMP D D D R G PCKGE -LED PLSTIC SSOP T JMX = 0 C, θ J = 0 C/ W C + C D D D D 0 D/ D/ R R Consult LTC Marketing for parts specified with wider operating temperature ranges. ORDER PRT NMER LTCCG LTCIG SYMOL PRMETER CONDITIONS MIN TYP MX NITS Supplies I CC Supply Current (DCE Mode, RS0, RS0-, X. Modes, No Load m ll Digital Pins = or ) RS0, RS0-, X. Modes, Full Load 0 0 m V. Mode, No Load 0 m V. Mode, Full Load 0 m V. Mode, No Load 0 m V. Mode, Full Load 0 m No-Cable Mode 00 µ P D Internal Power Dissipation (DCE Mode) RS0, RS0-, X. Modes, Full Load 0 mw V. Mode, Full Load 00 mw V. Mode, Full Load 0 mw V + Positive Charge Pump Output Voltage ny Mode, No Load.0. V V. Mode, with Load.0. V V. Mode, with Load, I DD = m. V V Negative Charge Pump Output Voltage V., V. Modes, No Load. V V. Mode, Full Load.0. V V. Mode, Full Load.. V RS0, RS0-, X. Modes, Full Load.. V f OSC Charge Pump Oscillator Frequency 0 khz t r Supply Rise Time No-Cable Mode or Power-p to Turn On ms Logic Inputs and Outputs V IH Logic Input High Voltage V V IL Logic Input Low Voltage 0. V sn fas

3 LTC The denotes specifications which apply over the full operating tempera- ELECTRICL CHRCTERISTICS ture range. = V (Notes, ) SYMOL PRMETER CONDITIONS MIN TYP MX NITS I IN Logic Input Current D, D, D ± µ,, M, DCE = (LTCC) µ,, M, DCE = (LTCI) 0 0 µ,, M, DCE = ± µ V OH Output High Voltage I O = m. V V OL Output Low Voltage I O = m V I OSR Output Short-Circuit Current 0V V O 0 0 m I OZR Three-State Output Current = = M =, 0V V O ± µ V. Driver V ODO Open Circuit Differential Output Voltage R L =.k (Figure ) ± V V ODL Loaded Differential Output Voltage R L = 0Ω (Figure ) 0.V ODO 0.V ODO V R L = 0Ω (Figure ) ± V V OD Change in Magnitude of Differential R L = 0Ω (Figure ) 0. V Output Voltage V OC Common Mode Output Voltage R L = 0Ω (Figure ) V V OC Change in Magnitude of Common Mode R L = 0Ω (Figure ) 0. V Output Voltage I SS Short-Circuit Current V OT = 0 m I OZ Output Leakage Current 0.V V O 0.V, Power Off or ± ±0 µ No-Cable Mode or Driver Disabled t r, t f Rise or Fall Time (Figures, ) (LTCC) ns (Figures, ) (LTCI) ns t PLH Input to Output (Figures, ) (LTCC) 0 0 ns (Figures, ) (LTCI) 0 0 ns t PHL Input to Output (Figures, ) (LTCC) 0 0 ns (Figures, ) (LTCI) 0 0 ns t Input to Output Difference, t PLH t PHL (Figures, ) (LTCC) 0 ns (Figures, ) (LTCI) 0 ns t SKEW Output to Output Skew (Figures, ) ns V. Receiver V TH Input Threshold Voltage V V CM V V V TH Input Hysteresis V V CM V 0 mv I IN Input Current (, ) V V, V ±0. m R IN Input Impedance V V, V 0 kω t r, t f Rise or Fall Time (Figures, ) ns t PLH Input to Output (Figures, ) (LTCC) 0 0 ns (Figures, ) (LTCI) 0 0 ns t PHL Input to Output (Figures, ) (LTCC) 0 0 ns (Figures, ) (LTCI) 0 0 ns t Input to Output Difference, t PLH t PHL (Figures, ) (LTCC) 0 ns (Figures, ) (LTCI) 0 ns V. Driver V OD Differential Output Voltage Open Circuit ±.00 V With Load, V V CM V (Figure ) ±0. ±0. ±0. V I OH Transmitter Output High Current V, = 0V.0 m I OL Transmitter Output Low Current V, = 0V.0 m sn fas

4 LTC The denotes specifications which apply over the full operating tempera- ELECTRICL CHRCTERISTICS ture range. = V (Notes, ) SYMOL PRMETER CONDITIONS MIN TYP MX NITS I OZ Transmitter Output Leakage Current 0.V V, 0.V ± ±0 µ t r, t f Rise or Fall Time (Figures, ) ns t PLH Input to Output (Figures, ) (LTCC) 0 ns (Figures, ) (LTCI) 0 ns t PHL Input to Output (Figures, ) (LTCC) 0 ns (Figures, ) (LTCI) 0 ns t Input to Output Difference, t PLH t PHL (Figures, ) (LTCC) 0 ns (Figures, ) (LTCI) 0 ns t SKEW Output to Output Skew (Figures, ) ns V. Receiver V TH Differential Receiver Input Threshold Voltage V (V + V )/ V (Figure ) V V TH Receiver Input Hysteresis V (V + V )/ V (Figure ) 0 mv I IN Receiver Input Current (, ) V V, V ±0. m R IN Receiver Input Impedance V V, V 0 kω t r, t f Rise or Fall Time (Figures, ) ns t PLH Input to Output (Figures, ) (LTCC) 0 0 ns (Figures, ) (LTCI) 0 0 ns t PHL Input to Output (Figures, ) (LTCC) 0 0 ns (Figures, ) (LTCI) 0 0 ns t Input to Output Difference, t PLH t PHL (Figures, ) (LTCC) 0 ns (Figures, ) (LTCI) 0 ns V. Driver V O Output Voltage Open Circuit ± V R L = k (Figure ) ± ±. V I SS Short-Circuit Current V OT = ±0 m I OZ Output Leakage Current 0.V V O 0.V, Power Off or ± ±0 µ No-Cable Mode or Driver Disabled SR Slew Rate R L = k, C L = 00pF (Figures, ) 0 V/µs t PLH Input to Output R L = k, C L = 00pF (Figures, ).. µs t PHL Input to Output R L = k, C L = 00pF (Figures, ). µs V. Receiver V THL Input Low Threshold Voltage. 0. V V TLH Input High Threshold Voltage. V V TH Receiver Input Hysteresis V R IN Receiver Input Impedance V V V kω t r, t f Rise or Fall Time (Figures, ) ns t PLH Input to Output (Figures, ) 0 0 ns t PHL Input to Output (Figures, ) 0 ns Note : bsolute Maximum Ratings are those beyond which the safety of a device may be impaired. Note : ll currents into device pins are positive; all currents out of device are negative. ll voltages are referenced to device ground unless otherwise specified. Note : ll typicals are given for = V, C = C = C VCC =, C VDD = C VEE =.µf tantalum capacitors and T = C. sn fas

5 PI F CTIO S C (Pin ): Capacitor C Negative Terminal. Connect a capacitor between C + and C. C + (Pin ): Capacitor C Positive Terminal. Connect a capacitor between C + and C. V DD (Pin ): Generated Positive Supply Voltage for V.. Connect a capacitor to ground. (Pin ): Positive Supply Voltage Input..V.V. ypass with a capacitor to ground. D (Pin ): TTL Level Driver Input. D (Pin ): TTL Level Driver Input. D (Pin ): TTL Level Driver Input. (Pin ): CMOS Level Receiver Output. R (Pin ): CMOS Level Receiver Output. (Pin ): CMOS Level Receiver Output. (Pin ): TTL Level Mode Select Input 0 with Pull-p to. (Pin ): TTL Level Mode Select Input with Pull-p to. M (Pin ): TTL Level Mode Select Input with Pull-p to. (Pin ): TTL Level Mode Select Input with Pull- p to. LTC (Pin ): Receiver Noninverting Input with Pull-p to. (Pin ): Receiver Inverting Input. R (Pin ): Receiver Noninverting Input. R (Pin ): Receiver Inverting Input. D/ (Pin ): Receiver Noninverting Input and Driver Noninverting Output. D/ (Pin 0): Receiver Inverting Input and Driver Inverting Output. D (Pin ): Driver Noninverting Output. D (Pin ): Driver Inverting Output. D (Pin ): Driver Noninverting Output. D (Pin ): Driver Inverting Output. (Pin ): Ground. (Pin ): Negative Supply Voltage. Connect a.µf capacitor to. C (Pin ): Capacitor C Negative Terminal. Connect a capacitor between C + and C. C + (Pin ): Capacitor C Positive Terminal. Connect a capacitor between C + and C. TEST CIRCITS V OD R L 0Ω R L 0Ω V OC R L 0Ω C L 0pF C L 0pF R pf F0 F0 Figure. V. Driver Test Circuit Figure. V. Driver/Receiver C Test Circuit sn fas

6 LTC TEST CIRCITS D V OD 0Ω Ω 0Ω V CM Ω 0Ω 0Ω R pf F0 Figure. V. Driver/Receiver Test Circuit D D R C L R L pf F0 F0 Figure. V./V. Driver Test Circuit Figure. V./V. Receiver Test Circuit W ODE SELECTIO LTC MODE NME M D D D R Not sed (Default V.) V. V. Z V. V. V. RS V. V. Z V. V. V. RS V. V. Z V. V. V. X. 0 0 V. V. Z V. V. V. V V. V. Z V. V. V. RS/V. 0 0 V. V. Z V. V. V. V./RS 0 0 V. V. Z V. V. V. No Cable 0 Z Z Z Z Z Z Not sed (Default V.) V. V. V. Z V. V. RS0 0 0 V. V. V. Z V. V. RS0 0 0 V. V. V. Z V. V. X. 0 V. V. V. Z V. V. V. 0 0 V. V. V. Z V. V. RS/V. 0 V. V. V. Z V. V. V./RS 0 V. V. V. Z V. V. No Cable Z Z Z Z Z Z sn fas

7 LTC W W SWITCHI G TI E WVEFOR S V D 0V.V f = MHz : t r ns : t f ns.v t PLH t PHL V O V O 0% t r 0% % / V O V DIFF = V() V() 0% t f 0% % V O t SKEW t SKEW F0 Figure. V., V. Driver Propagation Delays V OD 0V V OD t PLH f = MHz : t r ns : t f ns INPT 0V t PHL V OH R V OL.V OTPT.V F0 Figure. V., V. Receiver Propagation Delays V D 0V V O V O.V t PHL V t f 0V V.V t PLH 0V V t r V F0 Figure. V., V. Driver Propagation Delays V IH.V V IL t PHL V OH R V OL 0.V.V t PLH.V F0 Figure. V., V. Receiver Propagation Delays sn fas

8 LTC PPLICTIO S I FOR TIO Overview W The LTC/LTC form the core of a complete software-selectable DTE or DCE interface port that supports the RS, RS, EI0, EI0-, V., V. or X. protocols. Cable termination may be implemented using the LTC software-selectable cable termination chip or by using existing discrete designs. complete DCE-to-DTE interface operating in EI0 mode is shown in Figure. The LTC of each port is used to generate the clock and data signals. The LTC is used to generate the control signals along with LL (Local Loopback).The LTC cable termination chip is used only for the clock and data signals because they must support V. cable termination. The control signals do not need any external resistors. Mode Selection The interface protocol is selected using the mode select pins, and M (see the Mode Selection table). For example, if the port is configured as a V. interface, the mode selection pins should be M =, = 0, = 0. For the control signals, the drivers and receivers will operate in V. (RS) electrical mode. For the clock and data signals, the drivers and receivers will operate in V. electrical mode. The pin will configure the port for DCE mode when high, and DTE when low. The interface protocol may be selected simply by plugging the appropriate interface cable into the connector. The mode pins are routed to the connector and are left unconnected () or wired to ground (0) in the cable as shown in Figure. The internal pull-up current sources will ensure a binary when a pin is left unconnected and that the LTC/ LTC and the LTC enter the no-cable mode when the cable is removed. In the no-cable mode the LTC/LTC supply current drops to less than 00µ and all LTC/LTC driver outputs and LTC resistive terminations are forced into a high impedance state. The mode selection may also be accomplished by using jumpers to connect the mode pins to ground or. Cable Termination Traditional implementations have included switching resistors with expensive relays, or requiring the user to change termination modules every time the interface standard has changed. Custom cables have been used with the termination in the cable head or separate terminations are built on the board and a custom cable routes the signals to the appropriate termination. Switching the terminations with FETs is difficult because the FETs must remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off. sing the LTC along with the LTC/LTC solves the cable termination switching problem. Via software control, the LTC provides termination for the V. (RS), V. (RS), V. (RS) and V. electrical protocols. V. (RS) Interface typical V. unbalanced interface is shown in Figure. V. single-ended generator output with ground C is connected to a differential receiver with inputs ' connected to, and input C' connected to the signal return ground C. sually, no cable termination is required for V. interfaces, but the receiver inputs must be compliant with the impedance curve shown in Figure. The V. receiver configuration in the LTC is shown in Figure. In V. mode switch S inside the LTC is turned off.the noninverting input is disconnected inside the LTC receiver and connected to ground. The cable termination is then the 0k input impedance to ground of the LTC V. receiver. sn fas

9 LTC PPLICTIO S I FOR TIO W DTE DCE SERIL CONTROLLER LTC LTC LTC LTC SERIL CONTROLLER TXD D TXD Ω TXD SCTE D SCTE Ω R SCTE D TXC Ω TXC D TXC RXC R Ω RXC D RXC RXD Ω RXD D RXD LTC LTC RTS D RTS RTS DTR D DTR R DTR D DCD DCD D DCD DSR R DSR D DSR CTS CTS D CTS LL D LL R LL R D F Figure. Complete Multiprotocol Interface in EI0 Mode sn fas

10 LTC PPLICTIO S I FOR TIO W LTCH LTC DCE/ DTE M (DT) (DT) CONNECTOR LTC M CLE LTC M (DT) F Figure. Single Port DCE V. Mode Selection in the Cable GENERTOR LED INTERCONNECTING CLE CLE TERMINTION ' LOD RECEIVER C C' F Figure. Typical V. Interface sn fas

11 LTC PPLICTIO S I FOR TIO W I Z.m V V V Z ' R k S R 0k R k LTC RECEIVER V V ' R 0k R k.m F C' F Figure. V. Receiver Input Impedance Figure. V. Receiver Configuration V. (RS) Interface typical V. balanced interface is shown in Figure. V. differential generator with outputs and with ground C is connected to a differential receiver with ground C', inputs ' connected to, ' connected to. The V. interface has a differential termination at the receiver end that has a minimum value of 0Ω. The termination resistor is optional in the V. specification, but for the high speed clock and data lines, the termination is required to prevent reflections from corrupting the data. The receiver inputs must also be compliant with the impedance curve shown in Figure. In V. mode, all switches are off except S inside the LTC which connects a Ω differential termination impedance to the cable as shown in Figure. ' GENERTOR.Ω S S C Ω Figure. Typical V. Interface LTC LED INTERCONNECTING CLE R k S R 0k CLE TERMINTION ' ' C' 0Ω MIN R k LOD RECEIVER LTC LTC RECEIVER F ' R.Ω R 0k R k C' F Figure. V. Receiver Configuration sn fas

12 LTC PPLICTIO S I FOR TIO V. (RS) Interface W typical V. unbalanced interface is shown in Figure. V. single-ended generator output with ground C is connected to a single-ended receiver with input ' connected to, ground C' connected via the signal return ground C. In V. mode all switches are off except S inside the LTC/LTC which connects a k (R) impedance to ground in parallel with 0k (R) plus k (R) for a combined impedance of k as shown in Figure. The noninverting input is disconnected inside the LTC/ LTC receiver and connected to a TTL level reference voltage for a.v receiver trip point. V. Interface typical V. balanced interface is shown in Figure. V. differential generator with outputs and with ground C is connected to a differential receiver with ground C', inputs ' connected to, ' connected to. The V. interface requires a T or delta network termination at the receiver end and the generator end. The receiver differential impedance measured at the connector must be 0Ω ±Ω, and the impedance between shorted terminals (' and ') and ground C' must be 0Ω ±Ω. In V. mode, both switches S and S inside the LTC are on, connecting the T network impedance as shown in Figure 0. The switch in the LTC is off. The 0k input GENERTOR LED INTERCONNECTING CLE LOD GENERTOR LED INTERCONNECTING CLE LOD CLE TERMINTION RECEIVER CLE TERMINTION RECEIVER ' ' 0Ω Ω Ω 0Ω C C' F 0Ω ' 0Ω Figure. Typical V. Interface C C' F Figure. Typical V. Interface ' ' C'.Ω S S R.Ω LTC Ω R k R 0k Figure. V. Receiver Configuration S R 0k R k R k LTC LTC RECEIVER F ' ' C'.Ω S S R.Ω LTC Ω R k S R 0k R 0k R k R k LTC RECEIVER F0 Figure 0. V. Receiver Configuration sn fas

13 LTC PPLICTIO S I FOR TIO W impedance of the receiver is placed in parallel with the T network termination, but does not affect the overall input impedance significantly. The generator differential impedance must be 0Ω to 0Ω and the impedance between shorted terminals ( and ) and ground C must be 0Ω ±Ω. For the generator termination, switches S and S are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in Figure. ny mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground, causing a high frequency common mode spike on the and terminals. The common mode spike can cause EMI problems that are reduced by capacitor C which shunts much of the common mode energy to ground rather than down the cable. No-Cable Mode The no-cable mode ( = = M = ) is intended for the case when the cable is disconnected from the connector. The charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 00µ. Charge Pump The LTC uses an internal capacitive charge pump to generate V DD and as shown in Figure. voltage doubler generates about V on V DD and a voltage inverter generates about.v for. Four surface mounted tantalum or ceramic capacitors are required for C, C, C and C. The capacitor C should be a minimum of.µf. ll capacitors are V and should be placed as close as possible to the LTC to reduce EMI. V. DRIVER LTC Ω S ON.Ω S ON Receiver Fail-Safe ll LTC/LTC receivers feature fail-safe operation in all modes. If the receiver inputs are left floating or shorted together by a termination resistor, the receiver output will always be forced to a logic high..ω C 0pF Figure. V. Driver sing the LTC C F V C C C V DD C + C LTC C + C + C C.µF F Figure. Charge Pump sn fas

14 LTC PPLICTIO S I FOR TIO W DTE vs DCE Operation The pin acts as an enable for Driver /Receiver in the LTC, and Driver /Receiver and Driver / Receiver in the LTC. The INVERT pin in the LTC allows the Driver /Receiver enable to be high or low true polarity. The LTC/LTC can be configured for either DTE or DCE operation in one of two ways: a dedicated DTE or DCE port with a connector of appropriate gender or a port with one connector that can be configured for DTE or DCE operation by rerouting the signals to the LTC/LTC using a dedicated DTE cable or dedicated DCE cable. dedicated DTE port using a D- male connector is shown in Figure. The interface mode is selected by logic outputs from the controller or from jumpers to either or on the mode select pins. dedicated DCE port using a D- female connector is shown in Figure. port with one D- connector, but can be configured for either DTE or DCE operation is shown in Figure. The configuration requires separate cables for proper signal routing in DTE or DCE operation. For example, in DTE mode, the TXD signal is routed to Pins and via Driver in the LTC. In DCE mode, Driver now routes the RXD signal to Pins and. Multiprotocol Interface with RL, LL, TM and a D- Connector If the RL, LL and TM signals are implemented, there are not enough drivers and receivers available in the LTC/ LTC. In Figure, the required control signals are handled by the LTC but the clock/data signals use the LTC. The LTC has an additional single-ended driver/receiver pair that can handle two more optional control signals such as TM and LL. Cable-Selectable Multiprotocol Interface cable-selectable multiprotocol DTE/DCE interface is shown in Figure. The select lines, and are brought out to the connector. The mode is selected by the cable by wiring (connector Pin ) and (connector Pin ) and (connector Pin ) to ground (connector Pin ) or letting them float. If, or DCE/ DTE is floating, internal pull-up current sources will pull the signals to. The select bit M is hard wired to. When the cable is pulled out, the interface will go into the no-cable mode. Compliance Testing European standard EN 00 test report is available for the LTC/LTC/LTC chipset. copy of the test report is available from LTC or TV Telecom Services Inc. (formerly Detecon Inc.) The title of the report is: Test Report No. NET/0/. The address of TV Telecom Services Inc. is: TV Telecom Services Inc. Type pproval Division Old Highway, Ste St. Paul, MN S Tel. + () -0 Fax. + () -0 sn fas

15 LTC TYPICL PPLICTIO S C 0pF C 0pF C 0pF LTC TXD SCTE C V C C CHRGE PMP LTC D D + C C.µF C C LTCH M 0 TXD () TXD SCTE () SCTE D TXC RXC RXD R M 0 TXC () TXC RXC () RXC RXD () RXD SG SHIELD C RTS DTR C V DD D D C 0 D- MLE CONNECTOR RTS () RTS DTR () DTR D DCD DSR CTS LTC R 0 DCD () DCD DSR () DSR CTS () CTS LL R LL () D INVERT M M F Figure. Controller-Selectable Multiprotocol DTE Port with D- Connector sn fas

16 LTC TYPICL PPLICTIO S C 0pF C 0pF C 0pF LTC V RXD RXC C C C CHRGE PMP LTC D D + C C.µF C C LTCH M 0 RXD () RXD RXC () RXC D TXC SCTE TXD R M 0 TXC () TXC SCTE () SCTE TXD () TXD S () SHIELD () C CTS DSR C V DD D D C D- FEMLE CONNECTOR CTS () CTS DSR () DSR D DCD DTR RTS LTC R 0 0 DCD () DCD DTR () DTR RTS () RTS LL R LL () D INVERT M M F Figure. Controller-Selectable DCE Port with D- Connector sn fas

17 LTC TYPICL PPLICTIO S C 0pF C 0pF C 0pF LTC DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC C V C C CHRGE PMP LTC D D + C C.µF C C LTCH M 0 DTE TXD TXD SCTE SCTE DCE RXD RXD RXC RXC D DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD R M S S 0 TXC TXC RXC RXC RXD RXD SG SHIELD TXC TXC SCTE SCTE TXD TXD C DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR C V DD D D C 0 D- CONNECTOR RTS RTS DTR DTR CTS CTS DSR DSR D DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS LTC R 0 DCD DCD DSR DSR CTS CTS DCD DCD DTR DTR RTS RTS DTE_LL/DCE_LL R LL LL D INVERT M M F Figure. Controller-Selectable Multiprotocol DTE/DCE Port with D- Connector sn fas

18 LTC TYPICL PPLICTIO S C 0pF C 0pF C 0pF LTC DTE_LL/DCE_TM DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD C V C C CHRGE PMP LTC D D D D R 0 + C C.µF C C LTCH M 0 DTE LL TXD TXD SCTE SCTE TXC TXC RXC RXC RXD RXD DCE TM RXD RXD RXC RXC TXC TXC SCTE SCTE TXD TXD DTE_TM/DCE_LL L 0k 0 0 CTRL LTCH INVERT SET R L DCE M EC TM SG SHIELD LL D- CONNECTOR C DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR C V DD D D C 0 RTS RTS DTR DTR CTS CTS DSR DSR D DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS LTC R 0 DCD DCD DSR DSR CTS CTS DCD DCD DTR DTR RTS RTS DTE_RL/DCE_RL R RL RL M D INVERT M F Figure. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and D- Connector sn fas

19 LTC TYPICL PPLICTIO S C 0pF C 0pF C 0pF LTC DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC C V C C CHRGE PMP LTC D D + C C.µF C C LTCH M 0 DTE TXD TXD SCTE SCTE DCE RXD RXD RXC RXC DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD D R M 0 TXC TXC RXC RXC RXD RXD SG SHIELD TXC TXC SCTE SCTE TXD TXD D- CONNECTOR C DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR C V DD D D C RTS RTS 0 DTR DTR CTS CTS DSR DSR D DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS LTC R 0 DCD DCD DSR DSR CTS CTS DCD DCD DTR DTR RTS RTS R D M INVERT CLE WIRING FOR MODE SELECTION MODE PIN PIN V. PIN PIN RS, V. PIN RS PIN CLE WIRING FOR DTE/DCE SELECTION MODE PIN DTE PIN DCE / F Figure. Cable-Selectable Multiprotocol DTE/DCE Port with D- Connector Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. sn fas

20 LTC PCKGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package -Lead Plastic SSOP (0.0) (LTC DWG # 0-0-) * (.0.) (..0) ** (.0.) (..) (0. 0.) (0. 0.) * DIMENSIONS DO NOT ILDE MOLD FLSH. MOLD FLSH SHLL NOT EXCEED 0.00" (0.mm) PER SIDE ** DIMENSIONS DO NOT ILDE INTERLED FLSH. INTERLED FLSH SHLL NOT EXCEED 0.0" (0.mm) PER SIDE 0.0 (0.) SC (0. 0.) (0.0 0.) G SSOP 0 RELTED PRTS PRT NMER DESCRIPTION COMMENTS LTC Dual RS/RS Transceiver Two RS Driver/Receiver Pairs or Two RS Driver/Receiver Pairs LTC Single V RS/RS Multiprotocol Transceiver Two RS Driver/Receiver or Four RS Driver/Receiver Pairs LTC Software-Selectable Multiprotocol Transceiver -Driver/-Receiver for Data and Clock Signals LTC Software-Selectable Cable Terminator Perfect for Terminating the LTC LTC Single Supply V. Transceiver -Driver/-Receiver for Data and Clock Signals LTC Dual Supply V. Transceiver -Driver/-Receiver for Data and Clock Signals LTC Software-Selectable Multiprotocol Transceiver -Driver/-Receiver for Control Signals Including LL LTC Software-Selectable Multiprotocol Transceiver -Driver/-Receiver for Control Signals Including LL, RL and TM LTC Software-Selectable Multiprotocol Transceiver with -Driver/-Receiver for Data and Clock Signals Termination LTC.V Multiprotocol Transceiver -Driver/-Receiver for Control Signals Including LL LTC.V Multiprotocol Transceiver -Driver/-Receiver for Control Signals Including LL, RL and TM LTC.V Multiprotocol Transceiver with Termination -Driver/-Receiver for Data and Clock Signals 0 Linear Technology Corporation 0 McCarthy lvd., Milpitas, C 0- (0) -0 FX: (0) sn fas LW/TP 0 K REV PRINTED IN S LINER TECHNOLOGY CORPORTION