1µF LTC1345 FEATURES APPLICATIO S TYPICAL APPLICATIO. Single Supply V.35 Transceiver DESCRIPTIO

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1 FERES Single Chip Provides ll V.3 Differential Clock and Data Signals Operates From Single V Supply Software Selectable DE or DCE Configuration ransmitters and Receivers Will Withstand Repeated ±kv ESD Pulses Shutdown Mode Reduces I CC to 1µ yp Maud ransmission Rate ransmitter Maintains High Impedance When Disabled, Shut Down, or with Power Off Meets CCI V.3 Specification ransmitters are Short-Circuit Protected PPLICIO S Modems elecommunications Data Routers DESCRIPIO LC4 Single Supply V.3 ransceiver he LC 4 is a single chip transceiver that provides the differential clock and data signals for a V.3 interface from a single V supply. Combined with an external resistor termination network and an L 14 RS232 transceiver for the control signals, the LC4 forms a complete low power DE or DCE V.3 interface port operating from a single V supply. he LC4 features three current output differential transmitters, three differential receivers, and a charge pump. he transceiver can be configured for DE or DCE operation or shut down using two Select pins. In the Shutdown mode, the supply current is reduced to 1µ. he transceiver operates up to Mbaud. ll transmitters feature short-circuit protection and a Receiver Output Enable pin allows the receiver outputs to be forced into a high impedance state. oth transmitter outputs and receiver inputs feature ±kv ESD protection. he charge pump features a regulated V EE output using three external 1µF capacitors., LC and L are registered trademarks of Linear echnology Corporation. YPICL PPLICIO 1µF V CC1 V µF LC4 V CC1 DE Clock and Data Signals for V.3 Interface 1µF 1µF 1µF 14 GND (2) DCE µF I I 200/0 200/0 1µF 2 1 XD (3) SCE (1) XC (4) C () D (4) V CC2 1 2 LC LC4 01 V CC2 V 1µF = Ω I ECHNOLOGIES 200/0 (SOIC) OR R0/ (DIP) 1

2 LC4 SOLE XI RI GS W W W (Note 1) Supply Voltage, V CC... V Input Voltage ransmitters V to (V CC + 0.3V) Receivers... 1V to 1V S1, S2, OE V to (V CC + 0.3V) Output Voltage ransmitters... 1V to 1V Receivers V to (V CC + 0.3V) V EE... V to 0.3V Short-Circuit Duration ransmitter Output... Indefinite Receiver Output... Indefinite V EE sec Operating emperature Range Commercial... 0 C to 0 C Industrial C to C Storage emperature Range... C to 10 C Lead emperature (Soldering, sec) C W PCKGE/ORDER I FOR IO C2 + 1 C1 + 2 V CC 3 C1 4 GND S1 S2 R3 R2 R1 OE 14 NW PCKGE 2-LED PDIP OP VIEW 2 C2 2 V EE 2 Y1 2 Z1 24 Y2 23 Z2 22 Y3 21 Z SW PCKGE 2-LED PLSIC SO HREE V.3 RNSMIERS ND HREE RECEIVERS JMX = C, θ J = C/W (NW) JMX = C, θ J = C/W (SW) ORDER PR NMER LC4CNW LC4CSW LC4INW LC4ISW Consult factory for Military grade parts. DC ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = 2 C. V CC = V ±% (Notes 2, 3), unless otherwise specified. SYMOL PRMEER CONDIIONS MIN YP MX NIS V OD ransmitter Differential Output Voltage Figure 1, 4V V OS 4V V V OC ransmitter Common-Mode Output Voltage Figure 1, V OS = V I OH ransmitter Output High Current V Y, Z =..4 m I OL ransmitter Output Low Current V Y, Z =.4. m I OZ ransmitter Output Leakage Current S1 = S2 =, V V Y, Z V ±1 ±0 µ R O ransmitter Output Impedance 2V V Y, Z 2V 0 kω V H Differential Receiver Input hreshold Voltage V (V + V )/2 V mv V H Receiver Input Hysterisis V (V + V )/2 V 0 mv I IN Receiver Input Current (, ) V V, V 0.4 m R IN Receiver Input Impedance V V, V kω V OH Receiver Output High Voltage I O = 4m, V, = 0.2V 3 4. V V OL Receiver Output Low Voltage I O = 4m, V, = 0.2V V I OSR Receiver Output Short-Circuit Current V O V CC m I OZR Receiver hree-state Output Current S1 = S2 =, V O V CC ± µ V IH Logic Input High Voltage, S1, S2, OE 2 V V IL Logic Input Low Voltage, S1, S2, OE 0. V I IN Logic Input Current, S1, S2, OE ± µ I CC V CC Supply Current Figure 1, V OS = 0, S1 = S2 = HIGH 10 m No Load, S1 = S2 = HIGH 1 30 m Shutdown, S1 = S2 = 1 0 µ V EE V EE Voltage No Load, S1 = S2 = HIGH. V 2

3 LC4 C ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = 2 C. V CC = V ±% (Notes 2, 3), unless otherwise specified. SYMOL PRMEER CONDIIONS MIN YP MX NIS t R, t F ransmitter Rise or Fall ime Figures 1 and 3, V OS = 40 ns t PLH ransmitter Input to Output Figures 1 and 3, V OS = 2 0 ns t PHL ransmitter Input to Output Figures 1 and 3, V OS = 2 0 ns t SKEW ransmitter Output to Output Figures 1 and 3, V OS = 0 ns t PLH Receiver Input to Output Figures 1 and 4, V OS = 4 0 ns t PHL Receiver Input to Output Figures 1 and 4, V OS = 2 0 ns t SKEW Differential Receiver Skew, t PLH t PHL Figures 1 and 4, V OS = 3 ns t ZL Receiver Enable to Output LOW Figures 2 and, C L = 1pF, S1 Closed 40 0 ns t ZH Receiver Enable to Output HIGH Figures 2 and, C L = 1pF, S2 Closed 3 0 ns t LZ Receiver Disable From LOW Figures 2 and, C L = 1pF, S1 Closed 30 0 ns t HZ Receiver Disable From HIGH Figures 2 and, C L = 1pF, S2 Closed 3 0 ns f OSC Charge Pump Oscillator Frequency 200 khz R MX Maximum Data Rate (Note 4) 1 Mbaud Note 1: he absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. Note 2: ll currents into device pins are termed positive; all currents out of device pins are termed negative. ll voltages are referenced to device ground unless otherwise specified. Note 3: ll typicals are given for V CC = V, C1 = C2 = C3 = 1µF ceramic capacitors and = 2 C. Note 4: Maximum data rate is specified for NRZ data encoding scheme. he maximum data rate may be different for other data encoding schemes. Data rate is guaranteed by correlation and is not tested. YPICL PERFOR CE CHRCERISICS W ransmitter Output Current vs emperature ransmitter Output Current vs Output Voltage ransmitter Output Skew vs emperature V CC = V = 2 C V CC = V 20 V CC = V OP CRREN (m) OP CRREN (m) IME (ns) EMPERRE ( C) OP VOLGE (V) EMPERRE ( C) LC4 PC01 LC4 PC02 LC4 PC03 3

4 LC4 YPICL PERFOR CE CHRCERISICS W Receiver t PLH t PHL vs emperature Supply Current vs emperature V EE Voltage vs emperature 20 V CC = V 140 V CC = V V CC = V 1 0 LODED 2.0 IME (ns) CRREN (m) 0 NO LOD 20 CRREN (m) VOLGE (V) EMPERRE ( C) EMPERRE ( C) EMPERRE ( C) LC4 PC04 LC4 PC0 LC4 PC0 ransmitter Output Waveforms Receiver Output Waveforms INP V/DIV INP 0.2/DIV OP 0.2V/DIV OP V/DIV LC4 PC0 LC4 PC0 PI F CIO S C2 + (Pin 1): Capacitor C2 Positive erminal. C1 + (Pin 2): Capacitor C1 Positive erminal. V CC (Pin 3): Positive Supply, 4. V CC.2V. C1 (Pin 4): Capacitor C1 Negative erminal. GND (Pin ): Ground. he positive terminal of C3 is connected to ground. 1 (Pin ): ransmitter 1 Input. 2 (Pin ): ransmitter 2 Input. 3 (Pin ): ransmitter 3 Input. S1 (Pin ): Select Input 1. S2 (Pin ): Select Input 2. R3 (Pin ): Receiver 3 Output. R2 (Pin ): Receiver 2 Output. R1 (Pin ): Receiver 1 Output. OE (Pin 14): Receiver Output Enable. 1 (Pin 1): Receiver 1 Inverting Input. 1 (Pin 1): Receiver 1 Noninverting Input. 2 (Pin 1): Receiver 2 Inverting Input. 2 (Pin 1): Receiver 2 Noninverting Input. 3 (Pin 1): Receiver 3 Inverting Input. 3 (Pin 20): Receiver 3 Noninverting Input. Z3 (Pin 21): ransmitter 3 Inverting Output. 4

5 LC4 PI F CIO S Y3 (Pin 22): ransmitter 3 Noninverting Output. Z2 (Pin 23): ransmitter 2 Inverting Output. Y2 (Pin 24): ransmitter 2 Noninverting Output Z1 (Pin 2): ransmitter 1 Inverting Output. Y1 (Pin 2): ransmitter 1 Noninverting Output. V EE (Pin 2): Charge Pump Output. Connected to negative terminal of capacitor C3. C2 (Pin 2): Capacitor C2 Negative erminal. F CIO LES ransmitter and Receiver Configuration S1 S2 X# # REMRKS 0 0 Shutdown 1 0 1, 2, 3 1, 2 DCE Mode, 3 Shut Down 0 1 1, 2 1, 2, 3 DE Mode, X3 Shut Down 1 1 1, 2, 3 1, 2, 3 ll ctive ransmitter INPS OPS CONFIGRION S1 S2 Y1 ND Y2 Z1 ND Z2 Y3 Z3 DE Z Z DE Z Z DCE or ll ON 1 X DCE or ll ON 1 X Shutdown 0 0 X Z Z Z Z Receiver INPS OPS CONFIGRION S1 S2 OE R1 ND R2 R3 DE or ll ON X V 1 1 DE or ll ON X V 0 0 DCE V 1 Z DCE V 0 Z Disabled X X 1 X Z Z Shutdown 0 0 X X Z Z ES CIRCIS V CC Y Y Z V OD V OS Ω Ω V OC = (V Y + V Z )/2 Z R OE 1pF LC4 F01 RECEIVER OP C L 1k S1 S2 LC4 F02 Figure 1. V.3 ransmitter/receiver est Circuit Figure 2. Receiver Output Enable/Disable iming est Load

6 LC4 W W SWICHI G I E WVEFOR S 3V t PLH f = 1MHz: t r ns: t f ns t PHL V O Y Z V O Z 0% % t r 0% V DIFF = V(Y) V(Z) 1/2 V O 0% t f 0% % Y V O t SKEW t SKEW LC4 F03 Figure 3. V.3 ransmitter Propagation Delays V ID f = 1MHz: t r ns: t f ns INP V ID t PLH t PHL V OH R OP V OL LC4 F04 Figure 4. V.3 Receiver Propagation Delays 3V OE f = 1MHz: t r ns: t f ns V R V OL t ZL OP NORMLLY LOW t LZ 0.V V OH t ZH OP NORMLLY HIGH t HZ 0.V R LC4 F0 Figure. Receiver Enable and Disable imes

7 LC4 PPLICIO S I FOR IO W Review of CCI Recommendation V.3 Electrical Specifications V.3 is a CCI recommendation for synchronous data transmission via modems. ppendix 2 of the recommendation describes the electrical specifications which are summarized below: 1. he interface cable is balanced twisted-pair with 0Ω to 0Ω impedance. 2. he transmitter s source impedance is between and he transmitter s resistance between shorted terminals and ground is 1 ±1Ω. 4. When terminated by a 0Ω resistive load, the terminalto-terminal voltage should be 0.V ±20%.. he transmitter s rise time should be less than 1% of the signal pulse or 40ns, whichever is greater.. he common-mode voltage at the transmitter output should not exceed 0.V.. he receiver impedance is 0Ω ±Ω.. he receiver impedance to ground is 1 ±1Ω.. he transmitter or receiver should not be damaged by connection to earth ground, short-circuiting, or cross connection to other lines.. No data errors should occur with ±2V common-mode change at either the transmitter or receiver, or ±4V ground potential difference between transmitter and receiver. Cable ermination Each end of the cable connected to an LC4 must be terminated by either one of two electrically equivalent external Y or resistor networks for proper operation. he Y-termination has two series connected resistors and a Ω resistor connected between ground and the center tap of the two resistors as shown in Figure. 0Ω Ω 300Ω 300Ω Figure. Y and ermination Networks LC4 F0 he alternative -termination has a 0Ω resistor across the twisted wires and two 300Ω resistors between each wire and ground as shown in Figure. Standard 1/W, % surface mount resistors can be used for the termination network. o maintain the proper differential output swing, the resistor tolerance must be % or less. termination network that combines all the resistors into an SO-14 package is available from: I echnologies (Formerly eckman Industrial) Resistor Networks 4200 onita Place Fullerton, C 23 Phone: (14) FX: (14) Part #: I echnologies 200/0 (SOIC) R0/ (DIP)

8 LC4 PPLICIO S I FOR IO heory of Operation he transmitter output consists of complementary switched-current sources as shown in Figure. W V CC V EE m m CHIP ONDRY Figure. Simplified ransmitter Schematic Y Z Ω LC4 F0 With a logic zero at the transmitter input, the inverting output Z sources m and the noninverting output Y sinks m. he differential transmitter output voltage is then set by the termination resistors. With two differential resistors at each end of the cable, the voltage is set to ( m) = 0.V. With a logic 1 at the transmitter input, output Z sinks m and Y sources m. he common-mode voltage of Y and Z is when both current sources are matched and there is no ground potential difference between the cable terminations. he transmitter current sources have a common-mode range of ±2V, which allows for a ground difference between cable terminations of ±4V. Each receiver input has a 30k resistance to ground and requires external termination to meet the V.3 input impedance specification. he receivers have an input hysteresis of 0mV to improve noise immunity. he receiver output may be forced into a high impedance state by pulling the output enable (OE) pin high. For normal operation OE should be pulled low. charge pump generates the regulated negative supply voltage (V EE ) with three 1µF capacitors. Commutating capacitors C1 and C2 form a voltage doubler and inverter while C3 acts as a reservoir capacitor. o insure proper operation, the capacitors must have an ESR less than 1Ω. Monolithic ceramic or solid tantalum capacitors are good choices. nder light loads, regulation at about.2v is provided by a pulse-skipping scheme. nder heavy loads the charge pump is on continuously. small ripple of about 00mV will be present on V EE. wo Select pins, S1 and S2, configure the chip for DE, DCE, all transmitters and receivers on, or Shutdown. In Shutdown mode, I CC drops to 1µ. he outputs of the transmitters and receivers are in high impedance states, the charge pump stops and V EE is clamped to ground. ESD Protection LC4 transmitter outputs and receiver inputs have onchip protection from multiple ±kv ESD transients. ESD testing is done using the Human ody ESD Model. ESD testing must be done with an C ground on the V CC and V EE supply pins. he low ESR supply decoupling and V EE reservoir capacitors provide this C ground during normal operation. Complete V.3 Port Figure shows the schematic of a complete surface mounted, single V DE and DCE V.3 port using only three ICs and eight capacitors per port. he LC4 is used to transmit the clock and data signals, and the L14 to transmit the control signals. If test signals 140, 141, and 142 are not used, the transmitter inputs should be tied to V CC.

9 LC4 PPLICIONS INFORMION W 1µF 1µF DE 1µF 1µF Ω DCE = V CC1 V I I 2 200/ 200/ 1µF LC4 1µF 0 0 1µF LC4 2 1 (SOIC) P XD (3) P (SOIC) S S SCE (1) W W XC (4) Y Y X C () X V V D (4) 22 1 R R µF V CC2 V 14 GND (2) 14 V CC1 CLE SHIELD V CC2 0.2µF 0.2µF 0.2µF 0.2µF µF L14 0.1µF 0.1µF L µF 2 21 H DR () H 20 1 C RS () C 1 20 E DSR () E 21 1 D CS () D 1 1 F DCD () F 1 OPIONL SIGNLS NN N L M (142) RDL (140) LL (141) NN N L ISO 23 ISO PIN DE/DCE 34-PIN DE/DCE INERFCE CONNECOR INERFCE CONNECOR LC4 0 Figure. Complete Single V V.3 Interface

10 LC4 PPLICIONS INFORMION RS422/RS4 pplications W he receivers on the LC4 are ideal for RS422 and RS4 applications. sing the test circuit in Figure, the LC4 receivers are able to successfully reconstruct the data stream with the common-mode voltage meeting RS422 and RS4 requirements (V to V). Figures and show that the LC4 receivers are very capable of reconstructing data at rates up to Mbaud. RECEIVER OP V/DIV RECEIVER INP V/DIV 0 V V V CC1 V LC4 0Ω X 0Ω V CC2 V LC4 L O Figure. V Common Mode LC4 F L IN GND + V O V COMMON-MODE VOLGE X GND LC4 F0 RECEIVER INP V/DIV 1V V V Figure RS422/RS4 Receiver Interface RECEIVER OP V/DIV 0 Figure. V Common Mode LC4 F

11 LC4 PCKGE DESCRIPION Dimensions in inches (millimeters) unless otherwise noted. NW Package 2-Lead PDIP (Wide 0.00) (LC DWG # ) 1.4* (3.) MX * ( ) ( ) 0.10 ± 0.00 (3. ± 0.) ( ) ( ) 0.01 (0.31) MIN 0.00 (1.) YP ( ) 0. (3.1) MIN *HESE DIMENSIONS DO NO INCLDE MOLD FLSH OR PRORSIONS. MOLD FLSH OR PRORSIONS SHLL NO EXCEED 0.0 INCH (0.24mm) ( ) 0.0 (2.4) SC 0.01 ± (0.4 ± 0.0) N2 Information furnished by Linear echnology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear echnology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

12 LC4 PCKGE DESCRIPION Dimensions in inches (millimeters) unless otherwise noted. SW Package 2-Lead Plastic Small Outline (Wide 0.300) (LC DWG # ) 0. 0.* ( ) NOE (.00.43) ** (.31.) ( ) ( ) ( ) 0 YP ( ) NOE ( ) 0.00 (1.20) SC ( ) YP NOE: 1. PIN 1 IDEN, NOCH ON OP ND CVIIES ON HE OOM OF PCKGES RE HE MNFCRING OPIONS. HE PR MY E SPPLIED WIH OR WIHO NY OF HE OPIONS * DIMENSION DOES NO INCLDE MOLD FLSH. MOLD FLSH SHLL NO EXCEED 0.00" (0.12mm) PER SIDE ** DIMENSION DOES NO INCLDE INERLED FLSH. INERLED FLSH SHLL NO EXCEED 0.0" (0.24mm) PER SIDE ( ) S2 (WIDE) RELED PRS PR NMER DESCRIPION COMMENS LC34 Single V RS232/RS4 Multiprotocol ransceiver wo RS4 Driver/Receiver or Four RS232 Driver/Receiver Pairs LC43 Software-Selectable Multiprotocol ransceiver 4-Driver/4-Receiver for Data and Clock Signals LC44/LC44 Software-Selectable Cable erminator Perfect for erminating the LC143 (Not Needed with LC14) LC4 Dual Supply V.3 ransceiver 3-Driver/3-Receiver for Data and Clock Signals LC RS232/RS4 Multiprotocol ransceiver One RS4 Driver/Receiver or wo RS232 Driver/Receiver Pairs LC143 Software-Selectable Multiprotocol ransceiver erminated with LC44 for Data and Clock Signals, Companion to LC144 or LC14 for Control Signals LC144 Software-Selectable Multiprotocol ransceiver Companion to LC14 or LC143 for Control Signals Including LL LC14 Software-Selectable Multiprotocol ransceiver -Driver/-Receiver Companion to LC14 or LC143 for Control Signals Including LL, M and RL LC14 Multiprotocol ransceiver with ermination Combines LC143 and LC44 Functions for Data and Clock Signals Linear echnology Corporation 130 McCarthy lvd., Milpitas, C (40)432-0 FX: (40) fa L/P K REV PRINED IN S LINER ECHNOLOGY CORPORION 1