FEATURES DESCRIPTIO TYPICAL APPLICATION. LTC1546 Software-Selectable Multiprotocol Transceiver with Termination APPLICATIO S

Transcription

1 LC Software-Selectable Multiprotocol ransceiver with ermination FERES Software-Selectable ransceiver Supports: RS, RS, EI0, EI0-, V., V., X. V elecom Services Inc. Certified NE, NE and B Compliant On-Chip Cable ermination Pin Compatible with LC Complete DE or DCE Port with LC Operates from Single V Supply Small Footprint PPLICIO S Data Networking CS and DS Data Routers DESCRIPIO he LC is a -driver/-receiver multiprotocol transceiver with on-chip cable termination. When combined with the LC, this chip set forms a complete softwareselectable DE or DCE interface port that supports the RS, RS, EI0, EI0-, V., V. and X. protocols. ll necessary cable termination is provided inside the LC. In most applications, the LC replaces both an LC and an LC without any changes to the PC board. he LC runs from a single V supply using an internal charge pump that requires only five space-saving surface mounted capacitors. he LC is available in a -lead SSOP surface mount package., LC and L are registered trademarks of Linear echnology Corporation. YPICL PPLICION Complete DE or DCE Multiprotocol Serial Interface with DB- Connector LL CS DSR DCD DR RS RXD RXC XC SCE XD LC LC D R 0 XD () XD B SCE () SCE B XC () XC B RXC () RXC B RXD () RXD B SG () SHIELD () RS () RS B DR () DR B DCD () DCD B DSR () DSR B CS () CS B LL () DB- CONNECOR 0

2 LC BSOLE XI RI GS W W W (Note ) Supply Voltage....V Input Voltage ransmitters... 0.V to ( + 0.V) Receivers... V to V Logic Pins... 0.V to ( + 0.V) Output Voltage ransmitters... (V EE 0.V) to (V DD + 0.V) Receivers... 0.V to ( + 0.V) V EE... V to 0.V V DD... 0.V to V Short-Circuit Duration ransmitter Output... Indefinite Receiver Output... Indefinite V EE... 0 sec Operating emperature Range LCC... 0 C to 0 C LCI... 0 C to C Storage emperature Range... C to 0 C Lead emperature (Soldering, sec) C W PCKGE/ORDER I FOR IO C C + V DD M M DCE/DE OP VIEW CHRGE PMP G PCKGE -LED PLSIC SSOP JMX = 0 C, θ J = 0 C/ W* *θ J SOLDERED O CIRCI BORD IS YPICLLY 0 C/W C + C V EE B B 0 / / B B B ORDER PR NMBER LCCG LCIG Consult factory for parts specified with wider operating temperature ranges. ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = C. = V (Notes, ) SYMBOL PRMEER CONDIIONS MIN YP MX NIS Supplies I CC Supply Current (DCE Mode, RS0, RS0-, X. Modes, No Load m ll Digital Pins = or ) RS0, RS0-, X. Modes, Full Load 0 0 m V. Mode 0 m V. Mode, No Load 0 m V. Mode, Full Load m No-Cable Mode 0 00 µ P D Internal Power Dissipation (DCE Mode) RS0, RS0-, X. Modes, Full Load mw V. Mode, Full Load mw V. Mode, Full Load 0 mw V + Positive Charge Pump Output Voltage V. or V. Mode, No Load.0. V V. Mode.0.0 V V. Mode, with Load.0. V V. Mode, with Load, I DD = m. V V Negative Charge Pump Output Voltage V. Mode, No Load. V V. Mode, Full Load.. V V. Mode.. V RS0, RS0-, X. Modes, Full Load..0 V

3 ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = C. = V (Notes, ) LC SYMBOL PRMEER CONDIIONS MIN YP MX NIS f OSC Charge Pump Oscillator Frequency 00 khz t r Charge Pump Rise ime No-Cable Mode/Power-Off to Normal Operation ms Logic Inputs and Outputs V IH Logic Input High Voltage V V IL Logic Input Low Voltage 0. V I IN Logic Input Current,, ± µ, M, M, DCE = 0 0 µ, M, M, DCE = ± µ V OH Output High Voltage I O = m. V V OL Output Low Voltage I O = m V I OSR Output Short-Circuit Current 0V V O 0 0 m I OZR hree-state Output Current = M = M =, 0V V O ± µ V. Driver V ODO Open Circuit Differential Output Voltage R L =.k (Figure ) ± V V ODL Loaded Differential Output Voltage R L = (Figure ) 0.V ODO 0.V ODO V R L = (Figure ) ± V V OD Change in Magnitude of Differential R L = (Figure ) 0. V Output Voltage V OC Common Mode Output Voltage R L = (Figure ) V V OC Change in Magnitude of Common Mode R L = (Figure ) 0. V Output Voltage I SS Short-Circuit Current V O = ±0 m I OZ Output Leakage Current V and V B 0.V, Power Off or ± ±0 µ No-Cable Mode or Driver Disabled t r, t f Rise or Fall ime (Figures, ) ns t PLH Input to Output Rising (Figures, ) 0 ns t PHL Input to Output Falling (Figures, ) 0 ns t Input to Output Difference, t PLH t PHL (Figures, ) 0 ns t SKEW Output to Output Skew (Figures, ) ns V. Receiver V H Input hreshold Voltage V V CM V V V H Input Hysteresis V V CM V 0 mv R IN Input Impedance V V CM V (Figure ) 0 Ω t r, t f Rise or Fall ime C L = 0pF (Figures, ) ns t PLH Input to Output Rising C L = 0pF (Figures, ) 0 0 ns t PHL Input to Output Falling C L = 0pF (Figures, ) 0 0 ns t Input to Output Difference, t PLH t PHL C L = 0pF (Figures, ) 0 ns V. Driver V OD Differential Output Voltage Open Circuit, R L =.k (Figure ) ±. V With Load, V V CM V (Figure ) ±0. ±0. ±0. V V O, V OB Single-Ended Output Voltage Open Circuit, R L =.k (Figure ) ±. V V OC ransmitter Output Offset R L = (Figure ) ±0. V

4 LC ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = C. = V (Notes, ) SYMBOL PRMEER CONDIIONS MIN YP MX NIS I OH ransmitter Output High Current V, V B = 0V.0 m I OL ransmitter Output Low Current V, V B = 0V.0 m I OZ ransmitter Output Leakage Current V and V B 0.V ± ±0 µ R OD ransmitter Differential Mode Impedance Ω R OC ransmitter Common Mode Impedance V V CM V (Figure ) 0 Ω t r, t f Rise or Fall ime (Figures, ) ns t PLH Input to Output (Figures, ) ns t PHL Input to Output (Figures, ) ns t Input to Output Difference, t PLH t PHL (Figures, ) 0 ns t SKEW Output to Output Skew (Figures, ) ns V. Receiver V H Differential Receiver Input hreshold Voltage V V CM V (Figure ) V V H Receiver Input Hysteresis V V CM V (Figure ) 0 mv R ID Receiver Differential Mode Impedance V V CM V 0 Ω R IC Receiver Common Mode Impedance V V CM V (Figure ) 0 Ω t r, t f Rise or Fall ime C L = 0pF (Figures, ) ns t PLH Input to Output C L = 0pF (Figures, ) 0 0 ns t PHL Input to Output C L = 0pF (Figures, ) 0 0 ns t Input to Output Difference, t PLH t PHL C L = 0pF (Figures, ) 0 ns V. Driver V O Output Voltage Open Circuit ± V R L = k (Figure ) ± ±. V I SS Short-Circuit Current V O = ±0 m R OZ Power-Off Resistance V < V O < V, Power Off 00 Ω or No-Cable Mode SR Slew Rate R L = k, C L = 0 (Figures, ) 0 V/µs t PLH Input to Output R L = k, C L = 00pF (Figures, ).. µs t PHL Input to Output R L = k, C L = 00pF (Figures, ).. µs V. Receiver V HL Input Low hreshold Voltage (Figure ). 0. V V LH Input High hreshold Voltage (Figure ). V V H Receiver Input Hysteresis (Figure ) V R IN Receiver Input Impedance V V V kω t r, t f Rise or Fall ime C L = 0pF (Figures, ) ns t PLH Input to Output C L = 0pF (Figures, ) 0 00 ns t PHL Input to Output C L = 0pF (Figures, ) 0 00 ns Note : bsolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note : ll currents into device pins are positive; all currents out of device are negative. ll voltages are referenced to device ground unless otherwise specified. Note : ll typicals are given for = V, C = C = C VCC = C VDD =, C VEE =.µf and = C.

5 YPICL PERFOR CE CHRCERISICS SPPLY CRREN (m) V. Mode Supply Current vs Data Rate W SPPLY CRREN (m) 0 0 V. Mode Supply Current vs Data Rate SPPLY CRREN (m) LC V. Mode Supply Current vs Data Rate D RE (kbd) D RE (kbd) D RE (kbd) G0 G0 G0 V. Mode I CC vs emperature 0 V. Mode I CC vs emperature 0 V. Mode I CC vs emperature ICC (m) 0 I CC (m) 0 I CC (m) EMPERRE ( C) EMPERRE ( C) EMPERRE ( C) G0 G0 G0 PI F CIO S C (Pin ): Capacitor C Negative erminal. Connect a capacitor between C + and C. C + (Pin ): Capacitor C Positive erminal. Connect a capacitor between C + and C. V DD (Pin ): Generated Positive Supply Voltage for V.. Connect a capacitor to ground. (Pin ): Positive Supply Voltage Input..V.V. Bypass with a capacitor to ground. (Pin ): L Level Driver Input. (Pin ): L Level Driver Input. (Pin ): L Level Driver Input. (Pin ): CMOS Level Receiver Output. (Pin ): CMOS Level Receiver Output. (Pin ): CMOS Level Receiver Output. (Pin ): L Level Mode Select Input 0 with Pull-p to. See able. M (Pin ): L Level Mode Select Input with Pull-p to. See able. M (Pin ): L Level Mode Select Input with Pull-p to. See able. DCE/DE (Pin ): L Level Mode Select Input with Pull- p to. See able.

6 LC PI F CIO S B (Pin ): Receiver Noninverting Input. (Pin ): Receiver Inverting Input. B (Pin ): Receiver Noninverting Input. (Pin ): Receiver Inverting Input. / B (Pin ): Receiver Noninverting Input and Driver Noninverting Output. / (Pin 0): Receiver Inverting Input and Driver Inverting Output. B (Pin ): Driver Noninverting Output. (Pin ): Driver Inverting Output. B (Pin ): Driver Noninverting Output. (Pin ): Driver Inverting Output. (Pin ): Ground. V EE (Pin ): Negative Supply Voltage. Connect a.µf capacitor to. C (Pin ): Capacitor C Negative erminal. Connect a capacitor between C + and C. C + (Pin ): Capacitor C Positive erminal. Connect a capacitor between C + and C. BLOCK DIGR W C C + CHRGE PMP C C + C + C C + C V DD V DD V EE V EE S S Ω B S S Ω B 0k k k.ω 0 / DCE/DE S S Ω S k 0k.Ω / B 0k k k S S Ω.Ω k.ω 0k 0k k B k S S Ω.Ω k.ω 0k B BD

7 LC ES CIRCIS D B V OD R L R L V OC D B R L 0Ω C L 0pF C L 0pF F0 F0 Figure. V. Driver DC est Circuit Figure. V. Driver C est Circuit I B B I R B R V CM = ±V + (V B V ) R IN = I B I F0 C L F0 Figure. Input Impedance est Circuit Figure. V., V. Receiver C est Circuit V OB V OB Ω V OD R L Ω Ω Ω R L V OC V CM + V CM = ±V F0 F0 F0 V O V O Figure. V. Driver Open-Circuit est Figure. V. Driver est Circuit Figure. V. Driver Common Mode Impedance est Circuit Ω Ω V H + R V CM = ±V +.Ω Ω.Ω F0 V CM + F0 F Figure. V. Driver C est Circuit Figure. V. Receiver DC est Circuit Figure. Receiver Common Mode Impedance est Circuit D R C L R L V C L F F Figure. V. Driver est Circuit Figure. V. Receiver est Circuit

8 LC W ODE SELECIO able LC MODE NME M M DCE/DE Not sed (Default V.) V. V. Z V. V. V. RS V. V. Z V. V. V. RS V. V. Z V. V. V. X. 0 0 V. V. Z V. V. V. V V. V. Z V. V. V. RS/V. 0 0 V. V. Z V. V. V. V./RS 0 0 V. V. Z V. V. V. No Cable 0 Z Z Z Z Z Z Not sed (Default V.) V. V. V. Z V. V. RS0 0 0 V. V. V. Z V. V. RS0 0 0 V. V. V. Z V. V. X. 0 V. V. V. Z V. V. V. 0 0 V. V. V. Z V. V. RS/V. 0 V. V. V. Z V. V. V./RS 0 V. V. V. Z V. V. No Cable Z Z Z Z Z Z W W SWICHI G I E WVEFOR S V D 0V.V f = MHz : t r ns : t f ns.v t PLH t PHL V O B V O 0% t r 0% % / V O 0% t f 0% % B V O t SKEW t SKEW F Figure. V., V. Driver Propagation Delays V O B 0V V O t PLH f = MHz : t r ns : t f ns INP 0V t PHL V OH R V OL.V OP.V F Figure. V., V. Receiver Propagation Delays

9 LC W W SWICHI G I E WVEFOR S V D 0V V O V O.V t PHL V t f 0V SR = V t V f.v t PLH 0V V t r V SR = V t r F Figure. V. Driver Propagation Delays V IH.V V IL t PHL V OH R V OL 0.V.V t PLH.V F Figure. V. Receiver Propagation Delays PPLICIO S I FOR IO W Overview he LC and LC form a complete softwareselectable DE or DCE interface port that supports the RS, RS, EI0, EI0-, V., V. and X. protocols. Cable termination is provided on-chip, eliminating the need for discrete termination designs. complete DCE-to-DE interface operating in EI0 mode is shown in Figure. he LC half of each port is used to generate and appropriately terminate the clock and data signals. he LC is used to generate the control signals along with LL (Local Loopback). Mode Selection he interface protocol is selected using the mode select pins, M and M (see able ). For example, if the port is configured as a V. interface, the mode selection pins should be M =, M = 0, = 0. For the control signals, the drivers and receivers will operate in V. (RS) electrical mode. For the clock and data signals, the drivers and receivers will operate in V. electrical mode. he DCE/DE pin will configure the port for DCE mode when high, and DE when low. he interface protocol may be selected simply by plugging the appropriate interface cable into the connector. he mode pins are routed to the connector and are left unconnected () or wired to ground (0) in the cable as shown in Figure. he internal pull-up current sources will ensure a binary when a pin is left unconnected. he mode selection may also be accomplished by using jumpers to connect the mode pins to ground or. When the cable is removed, leaving all mode pins unconnected, the LC/LC will enter no-cable mode. In this mode the LC/LC supply current drops to less than 00µ and the LC/LC driver outputs are forced into a high impedance state. t the same time, the and receivers of the LC are differentially terminated with Ω and the other receivers on the LC and LC are terminated with 0kΩ to ground.

10 LC PPLICIO S I FOR IO W DE DCE SERIL CONROLLER LC LC SERIL CONROLLER XD XD Ω XD SCE SCE Ω SCE XC Ω XC XC RXC Ω RXC RXC RXD Ω RXD RXD LC LC RS RS RS DR DR DR DCD DCD DCD DSR DSR DSR CS CS CS LL D LL R LL R D F Figure. Complete Multiprotocol Interface in EI0 Mode Cable ermination raditional implementations used expensive relays to switch resistors or required the user to change termination modules every time a new interface standard was selected. Switching the terminations with FEs is difficult because the FEs must remain off when the signal voltage is beyond the supply voltage. lternatively, custom cables may contain termination in the cable head or route signals to various terminations on the board. he LC/LC chipset solves the cable termination switching problem by automatically providing the appropriate termination and switching on-chip for the V. (RS), V. (RS), V. (RS) and V. electrical protocols.

11 LC PPLICIO S I FOR IO W (D) LC M M DCE/DE CONNECOR DCE/DE M LC M CBLE (D) F Figure : Single Port DCE V. Mode Selection in the Cable V. (RS) Interface ll V. drivers and receivers necessary for the RS, EI0, EI0-, V. and X. protocols are implemented on the LC. typical V. unbalanced interface is shown in Figure. V. single-ended generator with output and ground C is connected to a differential receiver with input ' connected to, and ground C' connected via the signal return to ground C. sually, no cable termination is required for V. interfaces, but the receiver inputs must be compliant with the impedance curve shown in Figure 0. he V. receiver configuration in the LC is shown in Figure. In V. mode, switch S inside the LC is turned off. he noninverting input is disconnected inside the LC receiver and connected to ground. he cable termination is then the 0k input impedance to ground of the LC V. receiver. V. (RS) Interface typical V. balanced interface is shown in Figure. V. differential generator with outputs and B and ground C is connected to a differential receiver with input ' connected to, input B' connected to B, and ground C' connected via the signal return to ground C. he V..m GENEROR V C BLED INERCONNECING CBLE CBLE ERMINION Figure. ypical V. Interface V I Z Figure 0. V. Receiver Input Impedance ' C' V LOD RECEIVER V F.m V Z F0

12 LC PPLICIO S I FOR IO W ' R k S R 0k R k LC RECEIVER '.Ω S S Ω R k S R 0k R k LC RECEIVER B' B R 0k R k B'.Ω R 0k R k C' F C' F interface has a differential termination at the receiver end that has a minimum value of 0Ω. he termination resistor is optional in the V. specification, but for the high speed clock and data lines, the termination is essential to prevent reflections from corrupting the data. he receiver inputs must also be compliant with the impedance curve shown in Figure 0. In V. mode, all switches are off except S of the LC s receivers which connects a Ω differential termination impedance to the cable as shown in Figure. he LC only handles control signals, so no termination other than its V. receivers 0k input impedance is necessary. V. (RS) Interface typical V. unbalanced interface is shown in Figure. V. single-ended generator with output and ground C is connected to a single-ended receiver with input ' GENEROR Figure. V. Receiver Configuration B C BLED INERCONNECING CBLE CBLE ERMINION Figure. ypical V. Interface ' B' C' 0Ω MIN LOD RECEIVER F ctually, there is no switch S in receivers and. However, for simplicity, all termination networks on the LC can be treated identically if it is assumed that an S switch exists and is always closed on the and receivers. Figure. V. Receiver Configuration connected to and ground C' connected via the signal return to ground C. In V. mode, S is closed inside the LC/LC which connects a k (R) impedance to ground in parallel with 0k (R) plus k (R) for a combined impedance of k as shown in Figure. Proper termination is only provided when the B input of the receivers is floating, since S of the LC s and receivers remains on in V. mode. he noninverting input is disconnected inside the LC/LC receiver and connected to a L level reference voltage to give a.v receiver trip point. GENEROR ' B' C' C BLED INERCONNECING CBLE CBLE ERMINION Figure. ypical V. Interface.Ω S S.Ω Ω R k S R 0k R 0k Figure. V. Receiver Configuration ' C' R k R k LOD LC RECEIVER RECEIVER F F

13 LC PPLICIO S I FOR IO W V. Interface typical V. balanced interface is shown in Figure. V. differential generator with outputs and B and ground C is connected to a differential receiver with input ' connected to, input B' connected to B, and ground C' connected via the signal return to ground C. he V. interface requires a or delta network termination at the receiver end and the generator end. he receiver differential impedance measured at the connector must be 0Ω ±Ω, and the impedance between shorted terminals (' and B') and ground (C') must be ±Ω. In V. mode, both switches S and S inside the LC are on, connecting a network impedance as shown in Figure. he 0k input impedance of the receiver is placed in parallel with the network termination, but does not affect the overall input impedance significantly. he generator differential impedance must be to and the impedance between shorted terminals ( and B) and ground (C) must be ±Ω. No-Cable Mode he no-cable mode ( = M = M = ) is intended for the case when the cable is disconnected from the connector. he charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 00µ. Note that the LC s and receivers continue to be terminated by a Ω differential impedance. Charge Pump he LC uses an internal capacitive charge pump to generate V DD and V EE as shown in Figure. voltage doubler generates about V on V DD and a voltage inverter generates about.v on V EE. Four surface mounted tantalum or ceramic capacitors are required for C, C, C and C. he V EE capacitor C should be a minimum of.µf. ll capacitors are V and should be placed as close as possible to the LC to reduce EMI. GENEROR Ω B BLED INERCONNECING CBLE ' B' LOD CBLE ERMINION Ω RECEIVER V C C C V DD C + C LC C + C V EE + C C.µF F C C' F Figure. Charge Pump ' B' C'.Ω S Figure. ypical V. Interface S.Ω Ω R k S R 0k R 0k R k R k LC RECEIVER Figure. V. Receiver Configuration F Receiver Fail-Safe ll LC/LC receivers feature fail-safe operation in all modes. If the receiver inputs are left floating or are shorted together by a termination resistor, the receiver output will always be forced to a logic high. DE vs DCE Operation he DCE/DE pin acts as an enable for Driver /Receiver in the LC, and Driver /Receiver and Driver / Receiver in the LC. he INVER pin in the LC allows the Driver /Receiver enable to be high or low true polarity.

14 LC PPLICIO S I FOR IO W he LC/LC can be configured for either DE or DCE operation in one of two ways: a dedicated DE or DCE port with a connector of appropriate gender or a port with one connector that can be configured for DE or DCE operation by rerouting the signals to the LC/LC using a dedicated DE cable or dedicated DCE cable. dedicated DE port using a DB- male connector is shown in Figure. he interface mode is selected by logic outputs from the controller or from jumpers to either or on the mode select pins. dedicated DCE port using a DB- female connector is shown in Figure 0. port with one DB- connector, that can be configured for either DE or DCE operation is shown in Figure. he configuration requires separate cables for proper signal routing in DE or DCE operation. For example, in DE mode, the XD signal is routed to Pins and via the LC s Driver. In DCE mode, Driver now routes the RXD signal to Pins and. Multiprotocol Interface with RL, LL, M and a DB- Connector If the RL, LL and M signals are implemented, there are not enough drivers and receivers available in the LC/ LC. In Figure, the required control signals are handled by the LC. he LC has an additional single-ended driver/receiver pair that can handle two more optional control signals such as M and RL. Cable-Selectable Multiprotocol Interface cable-selectable multiprotocol DE/DCE interface is shown in Figure. he select lines, M and DCE/DE are brought out to the connector. he mode is selected by the cable by wiring (connector Pin ) and M (connector Pin ) and DCE/DE (connector Pin ) to ground (connector Pin ) or letting them float. If, M or DCE/ DE is floating, internal pull-up current sources will pull the signals to. he select bit M is hard wired to. When the cable is pulled out, the interface will go into the no-cable mode. Compliance esting he LC/LC chipset has been tested by V elecom Services Inc. and passed the NE, NE and B requirements. Copies of the test reports are available from LC or V elecom Services. he titles of the reports are: NE and NE: est Report No. NE/00/. B: est Report No. C/00/. he address of V elecom Services Inc. is: V elecom Services Inc. ype pproval Division Old Highway, Ste St. Paul, MN S EL: + () -0 FX: + () -0

15 LC YPICL PPLICIO S XD SCE XC RXC RXD C V C C CHRGE PMP LC M M DCE/DE 0 + C C.µF XD () XD B SCE () SCE B XC () XC B RXC () RXC B RXD () RXD B SG SHIELD C RS DR C V DD V EE C 0 DB- MLE CONNECOR RS () RS B DR () DR B DCD DSR CS LC 0 DCD () DCD B DSR () DSR B CS () CS B LL R LL () M M D INVER M M DCE/DE F Figure. Controller-Selectable Multiprotocol DE Port with DB- Connector

16 LC YPICL PPLICIO S RXD RXC XC SCE XD C V C C CHRGE PMP LC M M DCE/DE 0 + C C.µF RXD () RXD B RXC () RXC B XC () XC B SCE () SCE B XD () XD B S () SHIELD () C CS DSR C V DD V EE C DB- FEMLE CONNECOR CS () CS B DSR () DSR B DCD DR RS LC 0 0 DCD () DCD B DR () DR B RS () RS B LL R LL () M M D INVER M M DCE/DE F0 Figure 0. Controller-Selectable DCE Port with DB- Connector

17 LC YPICL PPLICIO S DE_XD/DCE_RXD DE_SCE/DCE_RXC DE_XC/DCE_XC DE_RXC/DCE_SCE DE_RXD/DCE_XD C V C C CHRGE PMP LC M M DCE/DE 0 + C C.µF DE XD XD B SCE SCE B XC XC B RXC RXC B RXD RXD B SG SHIELD DCE RXD RXD B RXC RXC B XC XC B SCE SCE B XD XD B C DE_RS/DCE_CS DE_DR/DCE_DSR C V DD V EE C 0 DB- CONNECOR RS RS B DR DR B CS CS B DSR DSR B DE_DCD/DCE_DCD DE_DSR/DCE_DR DE_CS/DCE_RS LC 0 DCD DCD B DSR DSR B CS CS B DCD DCD B DR DR B RS RS B DE_LL/DCE_LL R LL LL M M DCE/DE D INVER M M DCE/DE F Figure. Controller-Selectable Multiprotocol DE/DCE Port with DB- Connector

18 LC YPICL PPLICIO S DE_XD/DCE_RXD DE_SCE/DCE_RXC C V C C CHRGE PMP LC + C C.µF DE XD XD B SCE SCE B DCE RXD RXD B RXC RXC B DE_XC/DCE_XC DE_RXC/DCE_SCE DE_RXD/DCE_XD M M DCE/DE 0 XC XC B RXC RXC B RXD RXD B SG SHIELD XC XC B SCE SCE B XD XD B C DE_RS/DCE_CS DE_DR/DCE_DSR V C,,0 V DD V EE C 0 DB- CONNECOR RS RS B DR DR B CS CS B DSR DSR B M M DCE/DE DE_DCD/DCE_DCD DE_DSR/DCE_DR DE_CS/DCE_RS DE_LL/DCE_RI DE_RI/DCE_LL DE_M/DCE_RL DE_RL/DCE_M LC 0 D R R D DENB M M REN DCE/DE DCD DCD B DSR DSR B CS CS B LL * RI M RL *OPIONL DCD DCD B DR DR B RS RS B RI LL RL M F Figure. Controller-Selectable Multiprotocol DE/DCE Port with RL, LL, M and DB- Connector

19 LC YPICL PPLICIO S DE_XD/DCE_RXD DE_SCE/DCE_RXC C V C C CHRGE PMP LC + C C.µF DE XD XD B SCE SCE B DCE RXD RXD B RXC RXC B DE_XC/DCE_XC DE_RXC/DCE_SCE DE_RXD/DCE_XD M M DCE/DE 0 XC XC B RXC RXC B RXD RXD B SG SHIELD XC XC B SCE SCE B XD XD B DB- CONNECOR C DE_RS/DCE_CS DE_DR/DCE_DSR C V DD V EE C DCE/DE M RS RS B 0 DR DR B CS CS B DSR DSR B DE_DCD/DCE_DCD DE_DSR/DCE_DR DE_CS/DCE_RS LC 0 R D M M DCE/DE INVER CBLE WIRING FOR MODE SELECION MODE V. RS, V. RS PIN PIN PIN CBLE WIRING FOR DE/DCE SELECION MODE PIN DE PIN DCE PIN PIN PIN DCD DCD B DSR DSR B CS CS B DCD DCD B DR DR B RS RS B F Figure. Cable-Selectable Multiprotocol DE/DCE Port with DB- Connector Information furnished by Linear echnology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear echnology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

20 LC PCKGE DESCRIPIO Dimensions in inches (millimeters) unless otherwise noted. G Package -Lead Plastic SSOP (0.0) (LC DWG # 0-0-0).0.* (0. 0.0) 0..0 (0.0 0.).0.** (0.0 0.).. ( ) ( ) ( ) NOE: DIMENSIONS RE IN MILLIMEERS * DIMENSIONS DO NO ILDE MOLD FLSH. MOLD FLSH SHLL NO EXCEED 0.mm (0.00") PER SIDE ** DIMENSIONS DO NO ILDE INERLED FLSH. INERLED FLSH SHLL NO EXCEED 0.mm (0.0") PER SIDE 0. (0.0) BSC ( ) ( ) G SSOP RELED PRS PR NMBER DESCRIPION COMMENS LC Dual RS/RS ransceiver wo RS Driver/Receiver Pairs or wo RS Driver/Receiver Pairs LC Single V RS/RS Multiprotocol ransceiver wo RS Driver/Receiver or Four RS Driver/Receiver Pairs LC Software-Selectable Multiprotocol ransceiver -Driver/-Receiver for Data and Clock Signals LC Software-Selectable Cable erminator Perfect for erminating the LC (Not Needed with LC) LC Single Supply V. ransceiver -Driver/-Receiver for Data and Clock Signals LC Dual Supply V. ransceiver -Driver/-Receiver for Data and Clock Signals LC Software-Selectable Multiprotocol ransceiver erminated with LC for Data and Clock Signals, Companion to LC or LC for Control Signals LC Software-Selectable Multiprotocol ransceiver Companion to LC or LC for Control Signals Including LL LC Software-Selectable Multiprotocol ransceiver -Driver/-Receiver Companion to LC or LC for Control Signals Including LL, M and RL 0 Linear echnology Corporation 0 McCarthy Blvd., Milpitas, C 0- (0) -00 FX: (0) sn fs L/LCG 00 K PRINED IN S LINER ECHNOLOGY CORPORION