+5V Multiprotocol, Software-Selectable Control Transceivers

Transcription

1 -; Rev ; / +V Multiprotocol, Software-Selectable General Description The MXL/MX are four-driver/four-receiver multiprotocol transceivers that operate from a single +V supply in conjunction with the MXL. The MXL/MX, along with the MXL and MXL, form a complete software-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that supports the V. (RS-), V./V. (RS-/V., EI-, EI-, X., RS-), and V. protocols. The MXL/ MX transceivers carry serial interface control signaling, while the MXL carries the high-speed clock and data signals. Typically, the MXL is terminated using the MXL. The MX is identical to the MXL except for the addition of a µs (typ) glitch rejection circuit at the receiver inputs. The MXL/ MX are available in -pin SSOP packages. Data Networking CSU and DSU Data Routers Switches PCI Cards Telecommunication Equipment pplications Features MXL/MX, MXL, MXL Chipset Is Pin Compatible with LTC, LTC, LTC Chipset Chipset Operates from a Single +V Supply Software-Selectable Supports V. (RS-), V./V. (RS-/V., EI-, EI-, X., RS-) Protocols Flow-Through Pin Configuration True Fail-Safe Operation Low.µ Shutdown Current (No-Cable Mode) µs Receiver Input Deglitching (MX Only) TUV-Certified NET/NET and TBR/TBR Compliant Ordering Information PRT TEMP. RNGE PIN-PCKGE MXLCI C to + C SSOP MXCI C to + C SSOP Pin Configuration appears at end of data sheet. MXL/MX Typical Operating Circuit LL CTS DSR DCD DTR RTS RXD RXC TXC SCTE TXD D R R R R MXL MX D D D R R R MXL D D D MXL LL () CTS () CTS B DSR () DSR B DCD () DCD B DTR () DTR B RTS () RTS B SHIELD () SG () RXD () RXD B DB- CONNECTOR RXC () RXC B TXC () TXC B SCTE () SCTE B TXD () TXD B Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at ---, or visit Maxim s website at

2 +V Multiprotocol, Software-Selectable MXL/MX BSOLUTE MXIMUM RTINGS ll Voltages to GND Unless Otherwise Noted Supply Voltages...-.V to +V V DD...-.V to +.V V EE...+.V to -V V DD to V EE (Note )...V Logic Input Voltage M,, M,, INVERT, T_IN...-.V to +V Logic Output Voltage R_OUT...-.V to ( +.V) Transmitter Outputs T_OUT_, T_OUT_/R_IN...-V to +V Short-Circuit Duration...Continuous Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICL CHRCTERISTICS Receiver Inputs R_IN_, T_OUT_/R_IN_...-V to +V Continuous Power Dissipation (T = + C) -Pin SSOP (derate.mw/ C above + C)...mW Operating Temperature Range... C to + C Junction Temperature...+ C Storage Temperature Range...- C to + C Lead Temperature (soldering, s)...+ C Note : V DD and V EE - can have maximum magnitude of.v and V, respectively, but their difference cannot exceed V. ( = +V, V DD = +.V, V EE = -.V, T = T MIN to T MX, unless otherwise noted. Typical values are at T = + C.) (Note ) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS POWER SUPPLIES V C C S up p l y C ur r ent ( D C E M od e) ( D i g i tal Inp uts = G N D or V C C ) ( Tr ansm i tter s O utp uts S tati c) V EE Supply Current (DCE Mode) (Digital Inputs = GND or ) (Transmitters Outputs Static) V D D S up p l y C ur r ent ( D C E M od e) ( D i g i tal Inp uts = G N D or V C C ) ( Tr ansm i tter s O utp uts S tati c) Internal Power Dissipation (DCE Mode) I CC I EE I DD RS-, RS-, X., no load. RS-, RS-, X., full load V., no load V., full load No-cable mode, Invert = V C C. µ RS-, RS-, X., no load. RS-, X., full load RS-, full load V., no load V., full load No-cable mode. µ RS-, RS-, X., no load. RS-, RS-, X., full load V., no load V., full load No-cable mode. µ RS-, RS-, X., full load P D V., full load LOGIC INPUTS (M,, M,, INVERT, TIN, TIN, TIN, TIN) Input High Voltage V IH. V Input Low Voltage V IL. V TIN, TIN, TIN, TIN ± M,, M,, INVERT = Logic Input Current I IN GND µ M,, M,, INVERT = ± m m m mw

3 +V Multiprotocol, Software-Selectable ELECTRICL CHRCTERISTICS (continued) ( = +V, V DD = +.V, V EE = -.V, T = T MIN to T MX, unless otherwise noted. Typical values are at T = + C.) (Note ) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS LOGIC OUTPUTS (ROUT, ROUT, ROUT, ROUT) Output High Voltage V OH I SOURCE = m. V Output Low Voltage V OL I SINK = m.. V Output Short-Circuit Current I SC V OUT - m Output Pullup Current I L V OUT =, no-cable mode µ RECEIVER INPUTS Receiver Glitch Rejection MX only µs V. TRNSMITTER Open-Circuit Differential Output Voltage Loaded Differential Output Voltage V ODO Op en ci r cui t, R =.kω ( Fi g ur e ) ± V V ODL R = Ω (Figure ), T = + C. V ODO R = Ω (Figure ) ±. V ODO V MXL/MX Change in Magnitude of Output Differential Voltage V OD R = Ω (Figure ). V Common-Mode Output Voltage V OC R = Ω (Figure ) V Change in Magnitude of Output Common-Mode Voltage V OC R = Ω (Figure ). V Short-Circuit Current I SC V OUT = GND m Output Leakage Current I Z -.V < V OUT < +.V, power-off or nocable mode ± ± µ Rise or Fall Time t r, t f R = Ω (Figures, ) ns Transmitter Input to Output Data Skew t PHL, t PLH R = Ω (Figures, ) ns t PHL - t PLH (Figures, ) ns Output-to-Output Skew (Figures, ) ns V. RECEIVER Differential Input Voltage V TH -V V CM V - mv Input Hysteresis V TH -V V CM V mv Receiver Input Current I IN -V V,B V ±. m Receiver Input Resistance R IN -V V,B V kω Rise or Fall Time t r, t f (Figures, ) ns Receiver Input to Output Data Skew t PHL, t PLH (Figures, ) t PHL - t PLH (Figures, ) MXL ns MX µs MXL ns MX µs

4 +V Multiprotocol, Software-Selectable MXL/MX ELECTRICL CHRCTERISTICS (continued) ( = +V, V DD = +.V, V EE = -.V, T = T MIN to T MX, unless otherwise noted. Typical values are at T = + C.) (Note ) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS V. TRNSMITTER Open-Circuit Output Voltage Swing V O R L =.kω (Figure ) ± ± V R L = Ω (Figure ) ±. Output Voltage Swing V T. x V R L = Ω (Figure ), T = + C V O Short-Circuit Current I SC V O = GND, T = + C ± m Output Leakage Current I Z -.V < V OUT < +.V, power-off or no-cable mode ± ± µ Rise or Fall Time t r, t f R L = Ω, C L = pf (Figures, ) µs Transmitter Input to Output V. RECEIVER t PHL, t PLH R L = Ω, C L = pf (Figures, ) µs Differential Threshold Voltage V TH - mv Input Hysteresis V TH mv Receiver Input Current I IN -V V V ±. m Receiver Input Impedance R IN -V V V kω Rise or Fall Time t r, t f (Figures, ) ns Receiver Input to Output Data Skew V. TRNSMITTER MXL ns t PLH MX µs ( Fi g ur es, ) MXL ns t PHL MX µs t PHL - t PLH ( Fi g ur es, ) MXL ns MX µs Open circuit (Figure ) ± V Output Voltage Swing V O R L = kω (Figure ) ± ± V Short-Circuit Current I SC V O = GND ± m Output Leakage Current I Z -.V V OUT +.V, power-off or no-cable mode ± ± µ Output Slew Rate SR R L = kω, C L = pf (Figures, ) V/µs Transmitter Input to Output V. RECEIVER t PHL.. R L = kω, C L = pf (Figures, ) t PLH. Input Low Voltage V IL.. V Input High Voltage V IH.. V Input Hysteresis V HYS.. V Input Resistance R IN -V < V IN < +V kω Rise or Fall Time t r, t f (Figures, ) ns µs

5 +V Multiprotocol, Software-Selectable ELECTRICL CHRCTERISTICS (continued) ( = +V, V DD = +.V, V EE = -.V, T = T MIN to T MX, unless otherwise noted. Typical values are at T = + C.) (Note ) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS Receiver Input to Output (T = + C, unless otherwise noted.) ICC (m) V. MODE SUPPLY CURRENT (I CC ) vs. DT RTE FULL LOD, R = Ω DCE MODE INVERT = MXL ns t PLH MX µs (Figures, ) MXL ns t PHL MX µs Note : MXL/MX are designed to operate with V DD and V EE supplied by the MXL charge pump. NO LOD, R =.kω., DT RTE (kbps) MXL/MX toc Typical Operating Characteristics IDD (m) V. MODE SUPPLY CURRENT (I DD ) vs. DT RTE DCE MODE INVERT = FULL, R = Ω NO LOD, R =.kω., DT RTE (kbps) MXL/MX toc MXL/MX IEE (m) V. MODE SUPPLY CURRENT (I EE ) vs. DT RTE DCE MODE INVERT = FULL, R = Ω NO LOD, R =.kω MXL/MX toc ICC (m) V. MODE SUPPLY CURRENT (I CC ) vs. DT RTE DCE MODE INVERT = FULL LOD (R L = kω, C L = ) ND NO LOD MXL/MX toc., DT RTE (kbps). DT RTE (kbps)

6 +V Multiprotocol, Software-Selectable MXL/MX (T = + C, unless otherwise noted.) IDD (m) V. MODE SUPPLY CURRENT (I DD ) vs. DT RTE DCE MODE INVERT = FULL LOD, R L = kω, C L = pf NO LOD DT RTE (kbps) Typical Operating Characteristics (continued) MXL/MX toc IEE (m) V. MODE SUPPLY CURRENT (I EE ) vs. DT RTE DCE MODE INVERT = FULL LOD, R L = kω, C L = pf NO LOD DT RTE (kbps) MXL/MX toc V. LODED DIFFERENTIL OUTPUT VOLTGE vs. TEMPERTURE V. LODED OUTPUT VOLTGE vs. TEMPERTURE DIFFERENTIL OUTPUT VOLTGE (V) DCE MODE INVERT = R L = Ω V OUT+ V OUT- MXL/MX toc OUTPUT VOLTGE (V) DCE MODE R L = Ω V OUT+ V OUT- MXL/MX toc TEMPERTURE ( C) - TEMPERTURE ( C) V. LODED OUTPUT VOLTGE vs. TEMPERTURE V. RECEIVER INPUT CURRENT vs. INPUT VOLTGE OUTPUT VOLTGE (V) DCE MODE R L = kω V OUT- V OUT+ MXL/MX toc INPUT CURRENT (µ) - - MXL/MX toc - TEMPERTURE ( C) INPUT VOLTGE (V)

7 +V Multiprotocol, Software-Selectable (T = + C, unless otherwise noted.) INPUT CURRENT (m) V. RECEIVER INPUT CURRENT vs. INPUT VOLTGE INPUT VOLTGE (V) Typical Operating Characteristics (continued) MXL/MX toc SLEW RTE (V/µs) V. SLEW RTE vs. LOD CPCITNCE SLEW- SLEW+ CPCITNCE (pf) MXL/MX toc MXL/MX RISE/FLL TIME (µs) V. TRNSMITTER RISE ND FLL TIME vs. LOD CPCITNCE RISE FLL MXL/MX toc T IN T OUT / R IN MXL LOOPBCK SCOPE PHOTO V. MODE (UNLODED) MXL/MX toc V/div V/div. R OUT V/div CPCITNCE (pf) µs/div MXL LOOPBCK SCOPE PHOTO V. MODE (LODED) MXL/MX toc MXL LOOPBCK SCOPE PHOTO V. MODE (LODED) MXL/MX toc T IN V/div T IN V/div T OUT / R IN V/div T OUT / R IN V/div R OUT V/div R OUT V/div µs/div µs/div

8 +V Multiprotocol, Software-Selectable MXL/MX Pin Description PIN NME FUNCTION +V Supply Voltage (±%). Bypass with a capacitor to ground. V DD Positive Supply Generated by MXL. Bypass with a capacitor to ground. TIN Transmitter TTL-Compatible Input TIN Transmitter TTL-Compatible Input TIN Transmitter TTL-Compatible Input ROUT Receiver CMOS Output ROUT Receiver CMOS Output ROUT Receiver CMOS Output TIN Transmitter TTL-Compatible Input ROUT Receiver CMOS Output M TTL-Compatible Mode Select Pin with Internal Pullup to TTL-Compatible Mode Select Pin with Internal Pullup to M TTL-Compatible Mode Select Pin with Internal Pullup to TTL-Compatible Input with Internal Pullup to. Logic level high selects DCE interface. INVERT TTL Inp ut w i th Inter nal P ul l up to V C C. IN V E RT = H IGH r ever ses acti on of D C E /DTE for C hannel. TOUT/RIN Transmitter Output/Inverting Receiver Input RINB Noninverting Receiver Input RIN Inverting Receiver Input RINB Noninverting Receiver Input RIN Inverting Receiver Input TOUTB/RINB Noninverting Transmitter Output/Noninverting Receiver Input TOUT/RIN Inverting Transmitter Output/Inverting Receiver Input TOUTB Noninverting Transmitter Output TOUT Inverting Transmitter Output TOUTB Noninverting Transmitter Output TOUT Inverting Transmitter Output GND Ground V EE Negative Supply Generated by MXL. Bypass with a capacitor to ground.

9 +V Multiprotocol, Software-Selectable V OD Figure. V. DC Test Circuit R R V OC D V O C L Figure. V./V. Driver Test Circuit Test Circuits R L MXL/MX pf D B Ω B R pf D R pf pf Figure. V. C Test Circuit Detailed Description The MXL/MX are four-driver/four-receiver multiprotocol transceivers that operate from a single +V supply and the charge pump from the MXL. The MXL/MX, along with the MXL and MXL, form a complete software-selectable DTE or DCE interface port that supports the V. (RS-), V./V. (RS-, V., EI-, EI-, X., RS- ), and V. protocols. The MXL or MX usually carries the control signals. The MXL carries the high-speed clock and data signals, and the MXL provides termination for the clock and data signals. The MXL/MX feature a.µ no-cable mode, true fail-safe operation, and thermal shutdown circuitry. Thermal shutdown protects the drivers against Figure. V./V. Receiver Test Circuit excessive power dissipation. When activated, the thermal shutdown circuitry places the driver outputs into a high-impedance state. The MX deglitching feature reduces errors in unterminated equipment. The state of the mode-select pins M,, and M determines which serial-interface protocol is selected (Table ). The state of the input determines whether the transceivers will be configured as a DTE serial port or a DCE serial port. When the input is logic HIGH, driver T is activated and receiver R is disabled. When the input is logic LOW, driver T is disabled and receiver R is activated. The INVERT pin state changes the functionality regarding T and R only. M,, M, INVERT, and are internally pulled up to to ensure logic HIGH if left unconnected.

10 +V Multiprotocol, Software-Selectable MXL/MX V D V B- -V B V.V t PLH % Figure. V., V. Driver Propagation Delays V D B- -V D t PLH t r % % t SKEW f = MHz: t r ns: t f ns V DIFF = V(B) - V() / V f = MHz: t r ns: t f ns Switching Time Waveforms.V t PHL % % % t f t SKEW INPUT t PHL V H R V L.V OUTPUT.V Figure. V., V. Receiver Propagation Delays V D.V t PHL t PLH V -V V t f -V -V t r V Figure. V., V. Driver Propagation Delays V IH V IL.V t PHL.V t PLH V H R V L.V.V Figure. V., V. Receiver Propagation Delays

11 +V Multiprotocol, Software-Selectable The MXL/MXs mode can be selected through software control of the M,, M, INVERT, and inputs. lternatively, the mode can be selected by shorting the appropriate combination of mode control inputs to GND (the inputs left floating will be internally pulled up to - logic HIGH). If the M,, and M mode inputs are all unconnected, the MXL/MX will enter no-cable mode. Fail-Safe The MXL/MX guarantee a logic HIGH receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. The V. receiver threshold is set between -mv and mv to guarantee fail-safe operation. If the differential receiver input voltage (B - ) is mv, ROUT is logic HIGH. In the case of a terminated bus with all transmitters disabled, the receiver s differential input voltage is pulled to by the termination. With the receiver thresholds of the MXL/MX, this results in ROUT logic HIGH. The V. receiver threshold is set between -mv and mv. If the V. receiver input voltage is less than or equal to -mv, ROUT is logic HIGH. The V. receiver threshold is set between.v and.v. If the receiver input voltage is less than or equal to.v, ROUT is logic HIGH. In the case of a terminated bus with transmitters disabled, the receiver s input voltage is pulled to by the termination. pplications Information Cable-Selectable Mode cable-selectable, multiprotocol DTE/DCE interface is shown in Figure. The mode control lines M,, and are wired to the DB- connector. To select the serial interface mode, the appropriate combination of M,, M, and are grounded within the cable wiring. The control lines that are not grounded are pulled high by the internal pullups on the MXL. The serial interface protocol of the MXL/MX is now selected based on the cable that is connected to the DB- interface. V. (RS-) Interface The V. interface (Figure ) is an unbalanced singleended interface capable of driving a Ω load. The V. driver generates a minimum V O voltage of ±V across and C when unloaded and a minimum voltage of. V O when loaded with Ω. The V. receiver has a single-ended input and does not reject common-mode differences between C and C. The V. receiver input trip threshold is defined between +mv and -mv with input impedance characteristic shown in Figure. The MXL/MX V. mode receiver has a differential threshold between -mv and +mv. To ensure that the receiver has proper fail-safe operation see the Fail-Safe section. To aid in rejecting system noise, the MXL/MX V. receiver has a typical hysteresis of mv. Switch S in Figure is open in V. mode to disable the V. kω termination at the receiver input. Switch S is closed and switch S is open to internally ground the receiver B input. V. (RS-) Interface s shown in Figure, the V. protocol is a fully balanced differential interface. The V. driver generates a minimum of ±V between nodes and B when Ω minimum resistance is presented at the load. The V. receiver is sensitive to differential signals of ±mv at receiver inputs and B. The V. receiver input must comply with the impedance curve of Figure and reject common-mode signals developed across the cable (referenced from C to C in Figure ) of up to ±V. The MXL/MX V. mode receiver has a differential threshold between -mv and +mv. To ensure that the receiver has proper fail-safe operation; see the Fail-Safe section. To aid in rejecting system noise, the MXL/MX V. receiver has a typical hysteresis of mv. Switch S in Figure is open in V. mode to disable the V. kω termination at the inverting receiver input. Because the control signals are slow (kbps), Ω termination resistance is generally not required for the MXL/MX. The receiver inputs must also be compliant with the impedance curve shown in Figure. V. (RS-) Interface The V. interface is an unbalanced single-ended interface (Figure ). The V. generator provides a minimum of ±V across the kω load impedance between and C. The V. receiver has single-ended input. The MXL/MX V. mode receiver has a threshold between +.V and +.V. To aid in rejecting system noise, the MXL/MX V. receiver has a typical hysteresis of mv. Switch S in Figure is closed in V. mode to enable the kω V. termination at the receiver inputs. No-Cable Mode The MXL/MX will enter no-cable mode when the mode-select pins are left unconnected or connected HIGH (M = = M = ). In this mode, the multiprotocol drivers and receivers are disabled and the MXL/MX

12 +V Multiprotocol, Software-Selectable MXL/MX DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD C.µF V C C NC CHRGE PUMP D D D R R R M MXL M C C.µF C V EE C C pf C pf pf C MXL M LTCH M DTE TXD TXD B SCTE SCTE B TXC TXC B RXC RXC B RXD RXD B SG SHIELD DCE RXD RXD B RXC RXC B TXC TXC B SCTE SCTE B TXD TXD B C DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS C NC V DD D D D R R R R D V EE GND M MXL MX M INVERT C CBLE WIRING FOR MODE SELECTION MODE V. PIN PIN PIN PIN RS-. V. N.C. PIN RS- PIN N.C. CBLE WIRING FOR DTE/DCE SELECTION MODE PIN DTE PIN DCE N.C. M RTS CTS RTS B CTS B DTR DSR DTR B DSR B DB- CONNECTOR DCD DCD B DSR DSR B CTS CTS B DCD DCD B DTR DTR B RTS RTS B Figure. Cable-Selectable Multiprotocol Port with DB- Connector

13 +V Multiprotocol, Software-Selectable GENERTOR Figure. Typical V./V. Interface I Z C UNBLNCED INTERCONNECTING CBLE.m C CBLE TERMINTION GENERTOR LOD BLNCED INTERCONNECTING CBLE RECEIVER CBLE TERMINTION LOD RECEIVER MXL/MX -V -.m -V +V V Z +V B C Ω MIN B C Figure. Receiver Input Impedance Curve Figure. Typical V. Interface B C B R kω S GND R kω R kω S R kω R kω S MXL MX RECEIVER supply current is less than µ. The receiver outputs enter a high-impedance state in no-cable mode, which allows these output lines to be shared with other receiver outputs (the receiver outputs have an internal pullup resistor to pull the outputs HIGH if not driven). lso, in no-cable mode, the transmitter outputs enter a highimpedance state, so these output lines can be shared with other devices. Receiver Glitch Rejection To improve operation in an unterminated or otherwise noisy system, the MX features µs of receiver input glitch rejection. The glitch-rejection circuitry blocks the reception of high-frequency noise (t B < µs) while receiving a low-frequency signal (t B >µs) allowing glitch-free operation in unterminated systems at up to kbps. The MXL does not have this feature and can be operated at frequencies greater than kbps if properly terminated. Figure. V. Internal Resistance Network

14 +V Multiprotocol, Software-Selectable MXL/MX B C B GND R kω S R kω R kω R kω R kω MXL MX RECEIVER B C B GND R kω S R kω R kω R kω R kω MXL MX RECEIVER Figure. V. Internal Resistance Networks Figure. V. Termination and Internal Resistance Network DTE vs. DCE Operation Figure shows a port with one DB- connector that can be configured for either DTE or DCE operation. The configuration requires separate cables for proper signal routing in DTE or DCE operation. Figure illustrates a DCE or DTE controller-selectable interface. The and INVERT inputs switch the port s mode of operation (Table ). The MXL and MXL/MX can be connected for either DTE or DCE operation in one of two ways: a dedicated DTE or DCE port with an appropriate gender connector or a port with a connector that can be configured for DTE or DCE operation by rerouting the signals to the MXL and MXL/MX using a dedicated DTE cable or dedicated DCE cable. The interface mode is selected by logic outputs from the controller or from jumpers to either or GND on the mode select pins. dedicated DCE port using a DB- female connector is shown in Figure. Figure illustrates a dedicated DTE port using a DB- male connector.

15 +V Multiprotocol, Software-Selectable Table. Mode Select Table PROTOCOL M M Not Used (Default V.) DCE/ DTE INVERT T T T R R R T R V. V. Z V. V. V. Z V. RS- V. V. Z V. V. V. Z V. RS- V. V. Z V. V. V. Z V. X. V. V. Z V. V. V. Z V. V. V. V. Z V. V. V. Z V. RS-/V. V. V. Z V. V. V. Z V. V./RS- V. V. Z V. V. V. Z V. No Cable Z Z Z Z Z Z Z Z Not Used (Default V.) V. V. Z V. V. V. V. Z RS- V. V. Z V. V. V. V. Z RS- V. V. Z V. V. V. V. Z X. V. V. Z V. V. V. V. Z V. V. V. Z V. V. V. V. Z RS-/V. V. V. Z V. V. V. V. Z V./RS- V. V. Z V. V. V. V. Z No Cable Z Z Z Z Z Z Z Z Not Used (Default V.) V. V. V. Z V. V. V. Z RS- V. V. V. Z V. V. V. Z RS- V. V. V. Z V. V. V. Z X. V. V. V. Z V. V. V. Z V. V. V. V. Z V. V. V. Z RS-/V. V. V. V. Z V. V. V. Z V./RS- V. V. V. Z V. V. V. Z No Cable Z Z Z Z Z Z Z Z Not Used (Default V.) V. V. V. Z V. V. Z V. RS- V. V. V. Z V. V. Z V. RS- V. V. V. Z V. V. Z V. X. V. V. V. Z V. V. Z V. V. V. V. V. Z V. V. Z V. RS-/V. V. V. V. Z V. V. Z V. V./RS- V. V. V. Z V. V. Z V. No Cable Z Z Z Z Z Z Z Z MXL/MX

16 +V Multiprotocol, Software-Selectable MXL/MX DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD C.µF V C C CHRGE PUMP D D D R R R M MXL M C C.µF C V EE C C pf C pf pf C MXL M LTCH M DTE TXD TXD B SCTE SCTE B TXC TXC B RXC RXC B RXD RXD B SG SHIELD DCE RXD RXD B RXC RXC B TXC TXC B SCTE SCTE B TXD TXD B C C V DD V EE GND C DB- CONNECTOR DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS DTE_LL/DCE_LL D D D R R R R D RTS RTS B DTR DTR B DCD DCD B DSR DSR B CTS CTS B LL CTS CTS B DSR DSR B DCD DCD B DTR DTR B RTS RTS B LL INVERT M M MXL M MX M INVERT Figure. Controller-Selectable Multiprotocol Port with DB- Connector

17 +V Multiprotocol, Software-Selectable RXD RXC TXC SCTE TXD C.µF V C C CHRGE PUMP D D D R R R M MXL M NC C C.µF C V EE C C pf C pf pf C MXL M LTCH M RXD () RXD B RXC () RXC B TXC () TXC B SCTE () SCTE B TXD () TXD B SGND () SHIELD () MXL/MX C C V DD V EE GND C DB- FEMLE CONNECTOR CTS DSR DCD DTR RTS LL D D D R R R R D CTS () CTS B DSR () DSR B DCD () DCD B DTR () DTR B RTS () RTS B LL () INVERT M M MXL M MX INVERT M NC Figure. Controller-Selectable DCE Port with DB- Connector

18 +V Multiprotocol, Software-Selectable MXL/MX TXD SCTE TXC RXC RXD C.µF V C C CHRGE PUMP D D D R R R M MXL M C C.µF C V EE C C pf C pf pf C MXL M LTCH M TXD () TXD B SCTE () SCTE B TXC () TXC B RXC () RXC B RXD () RXD B SG SHIELD C C V DD V EE GND C DB- MLE CONNECTOR RTS DTR DCD DSR CTS LL D D D R R R R D RTS () RTS B DTR () DTR B DCD () DCD B DSR () DSR B CTS () CTS B LL () INVERT M M MXL M MX INVERT M Figure. Controller-Selectable Multiprotocol DTE Port with DB- Connector

19 +V Multiprotocol, Software-Selectable Chip Information TRNSISTOR COUNT: PROCESS: BiCMOS TOP VIEW V DD TIN TIN TIN ROUT ROUT ROUT TIN ROUT M MXL MX Pin Configuration V EE GND TOUT TOUTB TOUT TOUTB TOUT/RIN TOUTB/RINB RIN RINB RIN MXL/MX RINB M TOUT/RIN INVERT SSOP

20 +V Multiprotocol, Software-Selectable MXL/MX Package Information SSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, San Gabriel Drive, Sunnyvale, C -- Maxim Integrated Products Printed US is a registered trademark of Maxim Integrated Products.