TOP VIEW. Maxim Integrated Products 1

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1 ; Rev 0; 10/02 EALUATION KIT AAILABLE 1:5 ifferential (L)PECL/(L)ECL/ General escription The is a low-skew, 1-to-5 differential driver designed for clock and data distribution. This device allows selection between two inputs: one differential and one single ended. The selected input is reproduced at five differential outputs. The differential input can be adapted to accept a single-ended input by connecting the on-chip BB supply to one input as a reference voltage. The features low output-to-output skew (20ps), making it ideal for clock and data distribution across a backplane or board. For interfacing to differential HSTL and (L)PECL signals, this device operates over a 3.0 to 5.5 supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3 or 5.0 supply. For differential (L)ECL operation, this device operates with a -3.0 to -5.5 supply. The is offered in a 20-pin wide SO package. Applications Precision Clock istribution Low-Jitter ata Repeaters ata and Clock rivers and Buffers Central-Office Backplane Clock istribution SLAM Backplane Base Stations ATE Features Guaranteed 400m ifferential Output at 1.5GHz Selectable Single-Ended or ifferential Input 130ps (max) Part-to-Part Skew at +25 C 20ps Output-to-Output Skew 365ps Propagation elay Synchronous Output Enable/isable On-Chip Reference for Single-Ended Inputs Input Biased to Low when Open Pin Compatible with MC100EL14 Ordering Information PART TEMP RANGE PIN-PACKAGE EWP -40 C to +85 C 20 Wide SO Pin Configuration Typical Application Circuit TOP IEW QO 1 20 Q0 2 Q 19 EN Q Z O = 50Ω RECEIER Q1 Q2 Q N.C. S Z O = 50Ω Q3 Q BB Q SEL 50Ω 50Ω Q TT = 2.0 WIE SO Functional iagram appears at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/allas irect! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Single-Ended Inputs (S, SEL, EN,, ) For to For >... - to to...±3.0 Continuous Output Current...50mA Surge Output Current...100mA BB Sink/Source Current...±0.65mA Continuous Power issipation (T A = +70 C) Single-Layer PC Board 20-Pin Wide SO (derate 10mW/ C above +70 C)...800mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin Wide SO C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC Board 20-Pin Wide SO C/W Junction-to-Case Thermal Resistance 20-Pin Wide SO C/W Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +150 C ES Protection Human Body Model (Inputs and Outputs)...2k Lead Temperature (soldering, 10s) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. C ELECTRICAL CHARACTERISTICS ( = 3.0 to 5.5, outputs loaded with 50Ω ±1% to 2, SEL = high or low, EN = low, unless otherwise noted. Typical values are at = 5.0, IH = 1, IL = 1.5.) (Notes 1, 2, 3) PARAMETER SYMBOL CONITIONS SINGLE-ENE INPUTS (S, SEL, EN) Input High oltage IH Input Low oltage IL ( ) > ( ) -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Input Current I IN IL(MIN), IH(MAX) µa IFFERENTIAL INPUTS (, ) Single-Ended Input High oltage Single-Ended Input Low oltage High oltage of ifferential Input Low oltage of ifferential Input IH IL connected to BB, Figure 1 connected to BB, Figure 1 ( ) connected to BB, Figure 1 ( ) > IH IL

3 C ELECTRICAL CHARACTERISTICS (continued) ( = 3.0 to 5.5, outputs loaded with 50Ω ±1% to 2, SEL = high or low, EN = low, unless otherwise noted. Typical values are at = 5.0, IH = 1, IL = 1.5.) (Notes 1, 2, 3) PARAMETER SYMBOL CONITIONS ifferential Input oltage -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS IH - IL Input Current I IN IH, IL, IH, IL µa OUTPUTS (, ) Single-Ended Output High oltage OH Figure Single-Ended Output Low oltage OL Figure ifferential Output oltage REFERENCE ( BB ) Reference oltage Output (Note 4) POWER SUPPLY Supply Current (Note 5) OH - OL Figure m BB I BB = ±0.5mA I EE ma 3

4 AC ELECTRICAL CHARACTERISTICS ( = 3.0 to 5.5, outputs are loaded with 50Ω ±1% to 2, input frequency 1.5GHz, input transition time = 125ps (20% to 80%), SEL = high or low, EN = low, IH = to, IL = to 0.15, IH - IL = 0.15 to 3, unless otherwise noted. Typical values are at = 5.0.) (Notes 1, 6) PARAMETER SYMBOL CONITIONS to elay (ifferential) S to elay -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS t PLH1, t PHL1 Figure ps t PLH3, t PHL3 IL = 1.55, IH = 1.09, Figure ps Output-to-Output Skew (Note 7) Part-to-Part Skew (Note 8) Added Random Jitter (Note 9) t SKOO ps t SKPP ps t RJ f IN = 1.5GHz clock p s ( RM S ) Added eterministic Jitter (Note 9) t J 1.5Gbps 2E 23-1 PRBS pattern Ps P-P Switching Frequency Output Rise/Fall Time (20% to 80%) ( OH - OL ) f MAX 400m, Figure GHz t R, t F Figure ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: C parameters are production tested at T A = +25 C and guaranteed by design over the full operating temperature range. Note 4: Use BB only for inputs that are on the same device as the BB reference. Note 5: All pins are open except and. Note 6: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 9: evice jitter added to a jitter-free input signal. 4

5 Typical Operating Characteristics ( = 5.0, IH = 1, IL = 1.15, input transition time = 125ps (20% to 80%), f IN = 1.5GHz, outputs loaded with 50Ω to ( 2), T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs.temperature ALL PINS ARE OPEN EXCEPT AN toc01 IFFERENTIAL OUTPUT OLTAGE (m) IFFERENTIAL OUTPUT OLTAGE ( OH - OL ) vs. FREQUENCY toc TEMPERATURE ( C) FREQUENCY (GHz) TRANSITION TIME (ps) TRANSITION TIME vs. TEMPERATURE t R t F toc03 PROPAGATION ELAY (ps) PROPAGATION ELAY vs. TEMPERATURE S MEASUREMENT AT IH = 2.12, = IFFERENTIAL toc TEMPERATURE ( C) TEMPERATURE ( C) 5

6 PIN NAME FUNCTION 1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to ( 2). 2 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to ( 2). 3 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to ( 2). 4 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to ( 2). 5 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to ( 2). 6 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to ( 2). 7 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to ( 2). 8 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to ( 2). 9 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to ( 2). 10 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to ( 2). 11 Negative Supply oltage etailed escription The is a low-skew, 1-to-5 differential driver designed for clock or data distribution. A 2-to-1 MUX selects one of the two clock inputs,, and S. The and inputs are differential while the S is single ended. The MUX is switched by the single-ended SEL input. A logic low selects the input and a logic high selects the S input. The SEL logic threshold is set by the internal voltage reference BB. SEL input can be driven by and or by a singleended (L)PECL/(L)ECL signal. The selected input is reproduced at five differential outputs, Q0 to Q4. Pin escription 12 SEL Clock Select Input (Single Ended). rive low to select the, input. rive high to select the S input. The SEL threshold is equal to BB. Internal pulldown to and pullup to. 13 BB reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to ; Reference Output oltage. Connect to the inverting or noninverting clock input to provide a otherwise, leave it unconnected. 14 Inverting ifferential Clock Input. Internal 45kΩ pullup to and 45kΩ pulldown to. 15 Noninverting ifferential Clock Input. Internal pulldown to and 45kΩ pullup to. 16 S Single-Ended Clock Input. Internal pulldown to and 45kΩ pullup to. 17 N.C. Not Internally Connected. Solder to PC board for package thermal dissipation. Positive Supply oltage. Bypass to with 0.1µF and 0.01µF ceramic capacitors. Place the 18, 20 capacitors as close to the device as possible with the smaller value capacitor closest to the device. Output Enable Input. Outputs are synchronously enabled on the falling edge of the clock input 19 EN when EN is low. Outputs are synchronously set to low on the falling edge of the clock input when EN is high. Internal pulldown to and pullup to. Synchronous Enable The is synchronously enabled and disabled with outputs in the low state to eliminate shortened clock pulses. EN is connected to the input of an edgetriggered flip-flop. After power-up, drive EN low and toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are disabled to a low state on the falling edge of the selected clock input after EN goes high. The threshold for EN is equal to BB. Power Supply For interfacing to differential HSTL and (L)PECL signals, the range is from 3.0 to 5.5 (with 6

7 grounded), allowing high-performance clock or data distribution in systems with a nominal 5.0 supply. For interfacing to differential (L)ECL, the range is -3.0 to -5.5 (with grounded). Output levels are referenced to and are considered (L)PECL or (L)ECL, depending on the level of the supply. With connected to a positive supply and connected to ground, the outputs are (L)PECL. The outputs are (L)ECL when is connected to ground and is connected to a negative supply. Input Bias Resistors When the and inputs are open, the internal bias resistors set the inputs to differential low state. The inverting input () is biased with a 45kΩ pullup to and a 45kΩ pulldown to. The noninverting input () and S are biased with a 45kΩ pullup to and a pulldown to. The single-ended inputs (SEL, EN) are each biased with a pulldown to and a pullup to. ifferential Clock Input Limits The maximum magnitude of the differential signal applied to the differential clock input is 3.0. This limit also applies to the difference between any reference voltage input and a single-ended input. Specifications for the high and low voltages of a differential input ( IH and IL ) and the differential input voltage ( IH - IL ) apply simultaneously. Single-Ended Clock Input and BB The differential clock input can be configured to accept a single-ended input. This is accomplished by connecting the on-chip reference voltage, BB, to the inverting or noninverting input of the differential input as a reference. For example, the differential, input is converted to a noninverting, single-ended input by connecting BB to and connecting the single-ended input signal to. Similarly, an inverting configuration is obtained by connecting BB to and connecting the single-ended input to. With a differential input configured as single ended (using BB ), the singleended input can be driven to and or with a single-ended (L)PECL/(L)ECL signal. Note that the single-ended input must be least BB ±95m or a differential input of at least 95m to switch the outputs to the OH and OL levels specified in the C Electrical Characteristics table. When using the BB reference output, bypass it with a 0.01µF ceramic capacitor to. If the BB reference is not used, leave it open. The BB reference can source or sink 0.5mA. Use BB only for an input that is on the same device as the BB reference. Applications Information Supply Bypassing Bypass to with high-frequency, surface-mount, ceramic, 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the BB reference output, bypass it with a 0.01µF ceramic capacitor to (if the BB reference is not used, it can be left open). Controlled-Impedance Traces Input and output trace characteristics affect the performance of the. Connect input and output signals with 50Ω characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate outputs with 50Ω to 2 or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0. TRANSISTOR COUNT: 616 PROCESS: Bipolar Chip Information 7

8 ( IS CONNECTE TO BB ) IH BB IL OH OH - OL OL Figure 1. Switching Characteristics with Single-Ended Input IH IH - IL IL t PLH1 tphl1 OH OH - OL OL 80% 80% 0 (IFFERENTIAL) 0 (IFFERENTIAL) - 20% 20% t R t F Figure 2. Timing iagram 8

9 S t PLH3 t PHL3 IH IL OH OH - OL OL 80% 0 (IFFERENTIAL) 80% 0 (IFFERENTIAL) - 20% 20% t R t F Figure 3. Timing iagram for S EN S OR t S t H t S OUTPUTS ARE LOW t PLH OUTPUTS STAY LOW Figure 4. EN Timing iagram 9

10 Functional iagram Q0 45kΩ 45kΩ Q0 Q1 45kΩ Q1 0 Q2 Q2 1 Q3 S 45kΩ Q3 Q4 Q4 SEL EN Q BB 10

11 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to N E H INCHES MILLIMETERS IM MIN MAX MIN MAX A A B C e E H L SOICW.EPS 1 TOP IEW ARIATIONS: IM INCHES MILLIMETERS MIN MAX MIN MAX N MS AA AB AC A AE A C e B A1 0-8 FRONT IEW L SIE IEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE,.300" SOIC APPROAL OCUMENT CONTROL NO. RE B 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel rive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.