IEEE 802.3af PD Interface Controller For Power-Over-Ethernet

Transcription

1 9-99; Rev ; /0 EVALUATION KIT AVAILABLE IEEE 0.af PD Interface Controller General Description The provide complete interface function for a powered device (PD) to comply with the IEEE 0.af standard in a power-over-ethernet system. MAX5940A// MAX5940C/ provide the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also feature power-mode undervoltage lockout () with wide hysteresis and powergood outputs. The MAX5940A/ are available with an absolute maximum rating of 0V and the MAX5940C/ are rated for an absolute maximum rating of 90V. An integrated MOSFET provides PD isolation during detection and classification. All devices guarantee a leakage current offset of less than 0µA during the detection phase. A programmable current limit prevents high inrush current during power-on. The device features powermode with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. The MAX5940A/MAX5940C provide an active-high () open-drain output and a fixed threshold. The / provide both active-high () and active-low () outputs and have an adjustable threshold with the default value compliant to the 0.af standard. All devices are designed to work with or without an external diode bridge. The are available in -pin SO packages and are rated over the extended temperature range of -40 C to +5 C. IP Phones Wireless Access Nodes Computer Telephony Applications Security Cameras IEEE 0.af Power Devices D* Features Fully Integrated IEEE 0.af-Compliant PD Interface PD Detection and Programmable Classification Signatures Less than 0µA Leakage Current Offset During Detection Integrated MOSFET For Isolation and Inrush Current Limiting 90V Absolute Maximum Rating (MAX5940C/) Gate Output Allows External Control of the Internal Isolation MOSFET Programmable Inrush Current Control Programmable Undervoltage Lockout (/ Only) Wide Hysteresis Accommodates Twisted- Pair Cable Voltage Drop / Outputs to Enable Downstream DC-DC Converters -40 C to +5 C Operating Temperature Range DC-DC CONVERTER Ordering Information PART TEMP RANGE PIN- PACKAGE MAX5940AESA -40 C to +5 C SO Fixed Pin Configurations appear at end of data sheet. ESA -40 C to +5 C SO Adjustable MAX5940CESA -40 C to +5 C SO Fixed ESA -40 C to +5 C SO Adjustable Typical Operating Circuits 0V nf RDISC 5.5kΩ RCL MAX5940A MAX5940C COUT V+ MAX504 SS_SHDN VREG LOAD -4V D* 4 5 VEE OUT *OPTIONAL. Typical Operating Circuits continued at end of data sheet. C Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (All voltages are referenced to V EE, unless otherwise noted.) (MAX5940A/)...-0.V to +0V (MAX5940C/)...-0.V to +90V OUT,...-0.V to ( + 0.V),...-0.V to +V...-0.V to +V to OUT...-0.V to ( + 0.V) Maximum Input/Output Current (continuous) OUT to V EE...500mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS, to V EE...0mA,, to V EE...0mA to V EE...0mA Continuous Power Dissipation (T A = +0 C) -Pin SO (derate 5.9mW/ C above +0 C)...40mW Operating Temperature Range C to +5 C Storage Temperature Range...-5 C to +50 C Junction Temperature C Lead Temperature (soldering, 0s) C (V IN = ( - V EE ) = 4V, = = = OUT = OPEN, = V EE, T A = -40 C to +5 C, unless otherwise noted. Typical values are at T A = +5 C. All voltages are referenced to V EE, unless otherwise noted.) (Note ) DETECTION MODE PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Offset Current (Note ) I OFFSET V IN =.4V to 0.V 0 µa Effective Differential Input Resistance (Note ) CLASSIFICATION MODE Classification Current Turn-Off Threshold (Note 4) Classification Current (Notes 5, ) I CLASS 0V, R DISC = V IN =.V to 5.5kΩ POWER MODE dr V IN =.4V up to 0.V with V step, OUT = = 550 kω V TH,CLSS V IN rising V Class 0, R CL = 0kΩ 0 Class, R CL = Ω 9.. Class, R CL = 9Ω.9 9. Class, R CL = 55Ω Class 4, R CL = Ω. 4.4 Operating Supply Voltage V IN V IN = ( - V EE ) V Operating Supply Current I IN Measure at, not including R DISC 0.4 ma MAX5940A/MAX5940C Default Power Turn-On Voltage V, ON V IN increasing /, = V EE Default Power Turn-Off Voltage V, OFF V IN decreasing, = V EE for / Default Power Turn-On/Off Hysteresis External Programming Range V HYST, MAX5940A/MAX5940C 4. /, = V EE.4 V IN,EX Set externally (/ only) (Note ) ma 0 V V External Reference Voltage V REF, V External Reference Voltage Hysteresis HYST Ratio to V REF, % Bias Current I =.40V µa V V

3 ELECTRICAL CHARACTERISTICS (continued) (V IN = ( - V EE ) = 4V, = = = OUT = OPEN, = V EE, T A = -40 C to +5 C, unless otherwise noted. Typical values are at T A = +5 C. All voltages are referenced to V EE, unless otherwise noted.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Ground Sense Threshold (Note ) Input Ground Sense Glitch Rejection Power Turn-Off Voltage, Undervoltage Lockout Deglitch Time (Note 9) Isolation Switch N-Channel MOSFET On-Resistance Isolation Switch N-Channel MOSFET Off-Threshold Voltage V TH,G, mv = V EE µs t OFF_DLY V IN, V falling 0. ms Output current = 00mA, V = V, R ON measured between V GSTH T A = +5 C (Note 0) 0.. OUT and V EE T A = +5 C 0..5 OUT =, V - V EE, output current < µa Pulldown Switch Resistance R G Power-off mode, V IN = V, = V EE for 0.5 V Note : All min/max limits are production tested at +5 C. Limits at +5 C and -40 C are guaranteed by design. Note : The input offset current is illustrated in Figure. Note : Effective differential input resistance is defined as the differential resistance between and V EE without any external resistance. See Figure. Note 4: Classification current is turned off whenever the IC is in power mode. Note 5: See Table in the PD Classification Mode section. R DISC and R CL must be ±%, 00ppm or better. I CLASS includes the IC bias current and the current drawn by R DISC. Note : See the Thermal Dissipation section for details. Note : When is connected to the midpoint of an external resistor-divider with a series resistance of 5.5kΩ (±%), the turnon threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the pin does not exceed its maximum rating of V when V IN is at the maximum voltage ( only). Note : When the input voltage is below V TH,G,, the sets the threshold internally. Note 9: An input voltage or V glitch below their respective thresholds shorter than or equal to t OFF_DLY does not cause the to exit power-on mode (as long as the input voltage remains above an operable voltage level of V). Note 0: Guaranteed by design. Note : references to OUT while references to V EE. Ω 0 Ω Charging Current I G V = V µa High Voltage V I = µa V, Assertion V OUT Threshold, Assertion V Threshold, Output Low Voltage (Note ) V OUT - V EE, V OUT - V EE decreasing,... V V OUTEN V = 5.5V Hysteresis 0 mv ( - V EE ) increasing, OUT = V EE V V GSEN Hysteresis 0 mv V OLDCDC I SINK = ma; for, OUT ( - 5V) 0.4 V Leakage Current (Note ) = high, - V OUT = V µa Leakage Current (Note ) = V EE, - V EE = V µa

4 DETECTION CURRENT (ma) INPUT OFFSET CURRENT (μa) I INi + I OFFSET DETECTION CURRENT vs. INPUT VOLTAGE 0.5 R DISC = 5.5kΩ I IN + I RDISC INPUT VOLTAGE (V) INPUT OFFSET CURRENT vs. INPUT VOLTAGE INPUT VOLTAGE (V) I INi I IN dr i (V INi + - V INi ) V = (I INi + - I INi ) (I INi + - I INi ) I OFFSET I INi - V INi dr i dr i V INi V V INi + Figure. Effective Differential Input Resistance/Offset Current MAX5940A/B toc0 MAX5940A/B toc04 CLASSIFICATION CURRENT (ma) NORMALIZED CLASSIFICATION CURRENT vs. INPUT VOLTAGE CLASS 4 CLASS CLASS CLASS CLASS INPUT VOLTAGE (V) NORMALIZED vs. TEMPERATURE.00 = V EE TEMPERATURE ( C) MAX5940A/B toc0 MAX5940A/B toc05 EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (MΩ) V IN Typical Operating Characteristics (V IN = ( - V EE ) = 4V, = = = OUT = OPEN, = V EE (), T A = -40 C to +5 C. Typical values are at T A = +5 C. All voltages are referenced to V EE, unless otherwise noted.) V (mv) EFFECTIVE DIFFERENTIAL INPUT RESISTANCE vs. INPUT VOLTAGE INPUT VOLTAGE (V) OUTPUT LOW VOLTAGE vs. CURRENT I SINK (ma) MAX5940A/B toc0 MAX5940A/B toc0 4

5 V (mv) OUTPUT LOW VOLTAGE vs. CURRENT I SINK (ma) MAX5940A/B toc0 OUT LEAKAGE CURRENT (na) INRUSH CURRENT CONTROL (V IN = 4V) MAX5940A/B toc0 ms/div Typical Operating Characteristics (continued) (V IN = ( - V EE ) = 4V, = = = OUT = OPEN, = V EE (), T A = -40 C to +5 C. Typical values are at T A = +5 C. All voltages are referenced to V EE, unless otherwise noted.) 0 4 V OUT = V OUT LEAKAGE CURRENT vs. TEMPERATURE TEMPERATURE ( C) V 5V/div I INRUSH 00mA/div V OUT TO V EE 50V/div 50V/div MAX5940A/B toc0 INRUSH CURRENT CONTROL (V IN = V) MAX5940A/B toc09 ms/div INRUSH CURRENT CONTROL (V IN = V) MAX5940A/B toc ms/div V 5V/div I INRUSH 00mA/div V OUT TO V EE 50V/div 50V/div V 5V/div I INRUSH 00mA/div V OUT TO V EE 0V/div 0V/div 5

6 MAX5940A/ MAX5940C PIN / NAME, N.C. No Connection. Not internally connected. FUNCTION Pin Description Undervoltage Lockout Programming Input for Power Mode. When is above its threshold, the device enters power mode. Connect to V EE to use the default undervoltage lockout threshold. Connect to an external resistor-divider to define a threshold externally. The series resistance value of the external resistors must add to 5.5kΩ (±%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull to between V TH,G, and V REF,. Classification Setting. Add a resistor from to V EE to set a PD class (see Tables and ). Gate of Internal N-Channel Power MOSFET. sources 0µA when the device enters power mode. Connect an external 00V ceramic capacitor (C ) from to OUT to program the inrush current. Pull to V EE to turn off the internal MOSFET. The detection and classification functions operate normally when is pulled to V EE. Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect 4 4 V EE V EE to -4V. 5 5 OUT Output Voltage. Drain of the integrated isolation N-channel power MOSFET. Power-Good Indicator Output, Active-High, Open-Drain. is referenced to OUT. goes high impedance when V OUT is within.v of V EE and when is 5V above V EE. Otherwise, is pulled to OUT (given that V OUT is at least 5V below ). Connect to the ON pin of a downstream DC-DC converter. Power-Good Indicator Output, Active-Low, Open-Drain. is referenced to V EE. is pulled to V EE when V OUT is within.v of V EE and when is 5V above V EE. Otherwise, goes high impedance. Connect to the ON pin of a downstream DC-DC converter. Ground. is the positive input terminal. Detailed Description Operating Modes The PD front-end section of the MAX5940_ operates in different modes, PD detection signature, PD classification, and PD power, depending on its input voltage (V IN = - V EE ). All voltage thresholds are designed to operate with or without the optional diode bridge while still complying with the IEEE 0.af standard (see Figure 4). Detection Mode (.4V V IN 0.V) In detection mode, the power source equipment (PSE) applies two voltages on V IN in the range of.4v to 0.V (V step minimum), and then records the current measurements at the two points. The PSE then computes ΔV/ΔI to ensure the presence of the 5.5kΩ signature resistor. In this mode, most of the MAX5940_ internal circuitry is off and the offset current is less than 0µA. If the voltage applied to the PD is reversed, install protection diodes on the input terminal to prevent internal damage to the MAX5940_ (see the Typical Application Circuits). Since the PSE uses a slope technique (ΔV/ΔI) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process.

7 Table. PD Power Classification/R CL Selection CLASS USAGE R CL (Ω) MAXIMUM POWER USED BY PD (W) 0 Default 0k 0.44 to.95 Optional 0.44 to.4 Optional 9.4 to.49 Optional to.95 4 Not Allowed Reserved* *Class 4 reserved for future use. Table. Setting Classification Current IEEE 0.af PD CLASSIFICATION CLASS CURRENT SEEN AT V IN (ma) CLASS R CL (Ω) V IN * (V) CURRENT SPECIFICATION (ma) MIN MAX MIN MAX 0 0k. to to to to to *VIN is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop. Classification Mode (.V V IN 0V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. The IEEE 0.af standard defines five different classes as shown in Table. An external resistor (R CL ) connected from to V EE sets the classification current. The PSE determines the class of a PD by applying a voltage at the PD input and measures the current sourced out of the PSE. When the PSE applies a voltage between.v and 0V, the MAX5940_ exhibit a current characteristic with values indicated in Table. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by the 5.5kΩ detection signature resistor and the supply current of the MAX5940_ so the total current drawn by the PD is within the IEEE 0.af standard figures. The classification current is turned off whenever the device is in power mode. Power Mode During power mode, when V IN rises above the undervoltage lockout threshold (V,ON ), the MAX5940_ gradually turn on the internal N-channel MOSFET Q (see Figure ). The MAX5940_ charge the gate of Q with a constant current source (0µA, typ). The drainto-gate capacitance of Q limits the voltage rise rate at the drain of the MOSFET, thereby limiting the inrush current. To reduce the inrush current, add external drain-to-gate capacitance (see the Inrush Current Limit section). When the drain of Q is within.v of its source voltage and its gate-to-source voltage is above 5V, the MAX5940_ asserts the / outputs. The MAX5940_ have a wide hysteresis and turn-off deglitch time to compensate for the high impedance of the twisted-pair cable. Undervoltage Lockout The MAX5940_ operate up to a V supply voltage with a default turn-on (V,ON ) set at 5V (MAX5940A/MAX5940C) or 9V (/) and a turn-off (V,OFF ) set at 0V. The / have an adjustable threshold using a resistor-divider connected to (see Figure ). When the input voltage is above the threshold, the IC is in power mode and the MOSFET is on. When the input voltage goes below the threshold for more than t OFF_DLY, the MOSFET turns off.

8 () ( ). Figure. Block Diagram R R R 00mV.4V To adjust the threshold (/ only), connect an external resistor-divider from to and from to V EE. Use the following equations to calculate R and R for a desired threshold: R k x V REF, = 5. 5 Ω VIN, EX R = 5.5kΩ - R where V IN,EX is the desired threshold. Since the resistor-divider replaces the 5.5kΩ PD detection resistor, ensure that the sum of R and R equals 5.5kΩ ±%. When using the external resistor-divider, the / has an external reference voltage hysteresis of 0% (typ). When is programmed externally, the turn-off threshold is 0% (typ) of the new threshold. REF V EE V 0% EN Q EN CLASSIFICATION.V, REF 5V, REF V IN = V TO V R R Q.V V EE Q4 Q () OUT Figure. Setting Undervoltage Lockout with an External Resistor-Divider

9 Inrush Current Limit The MAX5940_ charge the gate of the internal MOSFET with a constant current source (0µA, typ). The drainto-gate capacitance of the MOSFET limits the voltage rise rate at the drain, thereby limiting the inrush current. Add an external capacitor from to OUT to further reduce the inrush current. Use the following equation to calculate the inrush current: I I x C INRUSH = G C OUT / Outputs (MAX5940A/MAX5940C only) is an open-drain, active-high logic output. goes high impedance when V OUT is within.v of V EE and when is 5V above V EE. Otherwise, is pulled to V OUT (given that V OUT is at least 5V below ). Connect to the ON pin of a downstream DC-DC converter. Connect a 00kΩ pullup resistor from to if needed. (/ only) is an open-drain, active-low logic output. is pulled to V EE when V OUT is within.v of V EE and when is 5V above V EE. Otherwise, goes high impedance. Connect to the ON pin of a downstream DC-DC converter. Connect a 00kΩ pullup resistor from to if needed. Thermal Dissipation During classification mode, if the PSE applies the maximum DC voltage, the maximum voltage drop from to V will be V. If the maximum classification current of 4mA flows through the MAX5940_, then the maximum DC power dissipation will be 54mW, which is slightly higher than the maximum DC power dissipation of the IC at maximum operating temperature. However, according to the IEEE 0.af standard, the duration of the classification mode is limited to 5ms (max). The MAX5940_ handle the maximum classification power dissipation for the maximum duration time without sustaining any internal damage. If the PSE violates the IEEE 0.af standard by exceeding the 5ms maximum classification duration, it may cause internal damage to the IC. 9

10 0V RJ-45 POWER-OVER SPAIR PAIRS R DISC 5.5kΩ nf 4 5 R* POWER-OVER SIGNAL PAIRS R* R CL RX TX Typical Application Circuits C OUT MAX504 SS_SHDN Application Circuit V REG PHY V DC-DC CONVERTER V+ V REG LOAD -4V 4 V EE OUT 5 C *R AND R ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 5.5kΩ AND REPLACE THE 5.5kΩ RESISTOR. Figure 4. PD with Power-Over-Ethernet (Power is Provided by Either the Signal Pairs or the Spare Pairs) 0

11 Application Circuit Diode D prevents the power-over-ethernet to back drive the wall adapter. Whenever the wall adapter power is greater than (V D + approximately V), the -4V 0V WALL ADAPTER SUPPLY R DISC 5.5kΩ nf V EE D R CL D PS0A-.0kΩ 4 V EE OUT 5 V EE 00kΩ CMPT904 Typical Application Circuits (continued) CMPT904 is pulled low to pinch off the power-over-ethernet. The wall adapter power pollutes the discovery signature, preventing PSE from detecting this PD. C C OUT DC-DC CONVERTER V+ MAX504 SS_SHDN Figure 5. Adding Wall Adapter Input Supply (Wall Adapter Supply Takes Precedence Over Power-Over-Ethernet) VREG LOAD

12 Application Circuit D prevents the wall adapter power from polluting the discovery and classification signatures. The optional -4V 0V WALL ADAPTER SUPPLY R DISC 5.5kΩ nf R CL D 4 V EE OUT 5 Typical Application Circuits (continued) R4 provides the 0mA minimum power maintenance signature to keep the power-over-ethernet from disconnecting. C D R4 4kΩ W DC-DC CONVERTER C OUT V+ MAX504 SS_SHDN Figure. Adding Wall Adapter Input Supply (Wall Adapter Supply And Power-Over-Ethernet Co-Exist, the One with Higher Voltage Provides Power To The Load) VREG LOAD

13 -4V 0V WALL ADAPTER SUPPLY R DISC 5.5kΩ nf R CL D 4 V EE OUT 5 Typical Application Circuits (continued) Application Circuit 4 If the wall adapter supply comes up first, it provides power to the load and pollute the discovery and classification signatures. If the power-over-ethernet comes up first, it powers the load until taken over by a wall adapter with higher output voltage. C DC-DC CONVERTER Figure. Adding Wall Adapter Input Supply (the One with Higher Voltage Provides Power to the Load) C OUT V+ MAX504 SS_SHDN VREG LOAD

14 -4V TOP VIEW D* 0V D* N.C. V EE 4 R DISC 5.5kΩ nf MAX5940A MAX5940C SO R** R** Pin Configurations 5 R CL N.C. OUT 4 5 V EE OUT *OPTIONAL. **R AND R ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 5.5kΩ AND REPLACE THE 5.5kΩ RESISTOR. Typical Operating Circuits (continued) C C OUT DC-DC CONVERTER V+ MAX504 SS_SHDN V REG LOAD Chip Information TRANSISTOR COUNT:,4 PROCESS: BiCMOS V EE 4 5 OUT SO 4

15 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to N TOP VIEW D e B A FRONT VIEW E A H C L SIDE VIEW 0 - INCHES MILLIMETERS DIM MIN MAX MIN MAX A A B C e BSC. BSC E H L VARIATIONS: DIM D D D INCHES MIN MAX MIN MAX N MS AA AB AC PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE,.50" SOIC APPROVAL MILLIMETERS DOCUMENT CONTROL NO. REV B SOICN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 0 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.