3V 10-Tap Silicon Delay Line DS1110L

Transcription

1 XX-XXXX; Rev 1; 11/3 3V 1-Tap Silicon Delay Line General Description The 1-tap delay line is a 3V version of the DS111. It has 1 equally spaced taps providing delays from 1ns to ns. The series delay lines provide a nominal accuracy of ±% or ±2ns, whichever is greater, at 3.3V and +2 C. The is characterized to operate from 2.7V to 3.6V. The produces both leading- and trailing-edge delays with equal precision. The device is offered in a standard 14-pin TSSOP. Communications Equipment Medical Devices Automated Test Equipment PC Peripheral Devices Applications Features All-Silicon Delay Line 3V Version of the DS111 1 Taps Equally Spaced Delays Are Stable and Precise Leading- and Trailing-Edge Accuracy Delay Tolerance ±% or ±2ns, Whichever Is Greater, at 3.3V and +2 C Economical Low-Profile 14-Pin TSSOP Low-Power CMOS TTL/CMOS Compatible Vapor Phase and IR Solderable Fast-Turn Prototypes Delays Specified Over Commercial and Industrial Temperature Ranges Custom Delays Available Pin Configuration Ordering Information TOP VIEW IN N.C. TAP2 TAP4 TAP6 TAP8 GND TSSOP (173mil) V CC TAP1 TAP3 TAP TAP7 TAP9 TAP1 PART TEM P RANGE PIN- PACKAGE TOTAL DELAY ( ns) * E-1-4 C to +8 C 14 TSSOP (173mil) 1 E-12-4 C to +8 C 14 TSSOP (173mil) 12 E-1-4 C to +8 C 14 TSSOP (173mil) 1 E-17-4 C to +8 C 14 TSSOP (173mil) 17 E-2-4 C to +8 C 14 TSSOP (173mil) 2 E-2-4 C to +8 C 14 TSSOP (173mil) 2 E-3-4 C to +8 C 14 TSSOP (173mil) 3 E-3-4 C to +8 C 14 TSSOP (173mil) 3 E-4-4 C to +8 C 14 TSSOP (173mil) 4 E-4-4 C to +8 C 14 TSSOP (173mil) 4 E- -4 C to +8 C 14 TSSOP (173mil) *Custom delays are available. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground...-.V to +6.V Operating Temperature Range...-4 C to +8 C Storage Temperature Range...- C to +12 C Soldering Temperature...See IPC/JEDEC J-STD-2A Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (-4 C to +8 C, VCC = 2.7V to 3.6V.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) V High-Level Input Voltage V IH (Note 1) 2.2 Low-Level Input Voltage V IL (Note 1) V Input Leakage Current I I V V I V CC µa Active Current I CC V CC = max, period = min (Note 2) 4 1 ma High-Level Output Current I OH V CC = min, V OH = 2.3V -1. ma Low-Level Output Current I OL V CC = min, V OL =.V 12 ma V CC +.3 V AC ELECTRICAL CHARACTERISTICS (-4 C to +8 C, VCC = 2.7V to 3.6V.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Pulse Width t WI (Note 6) Input to Tap Delay (Delays 4ns) 1% of tap 1 +2 C, 3.3V (Notes 3,, 6, 7, 9) -2 Table 1 +2 C to +7 C (Notes 4 7) -3 Table 1 +3 t PHL -4 C to +8 C (Notes 4 7) -4 Table 1 +4 ns ns Input to Tap Delay (Delays > 4ns) +2 C, 3.3V (Notes 3,, 6, 7, 9) - Table 1 + C to +7 C (Notes 4 7) -8 Table 1 +8 t PHL -4 C to +8 C (Notes 4 7) -13 Table % Power-Up Time t PU 1 ms Input Period Period (Note 8) 2 (t WI ) ns 2

3 CAPACITANCE (TA = +2 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Capacitance C IN 1 pf Note 1: All voltages are referenced to ground. Note 2: Measured with outputs open. Note 3: Initial tolerances are ± with respect to the nominal value at +2 C and V CC = 3.3V for both leading and trailing edges. Note 4: Temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7V to 3.6V range. Note : Intermediate delay values are available on a custom basis. Note 6: See Test Conditions section. Note 7: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other taps also slow down; tap 3 can never be faster than tap 2. Note 8: Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.). Note 9: For Tap 1 delays greater than 2ns, the tolerance is ±3ns or ±%, whichever is greater. (V CC = 3.3V, T A = +2 C, unless otherwise noted.) Typical Operating Characteristics DELAY CHANGE (%) vs. V CC - RAISING EDGE toc DELAY CHANGE (%) vs. V CC -2 RAISING EDGE toc V CC (V) V CC (V) 6 4 vs. TEMPERATURE - toc3 4 3 vs. TEMPERATURE -2 toc RISING EDGE RISING EDGE TEMPERATURE ( C) TEMPERATURE ( C) 3

4 (V CC = 3.3V, T A = +2 C, unless otherwise noted.) OUTPUT CURRENT HIGH (A).E+ -2.E-3-4.E-3-6.E-3-8.E-3-1.E-2-1.2E-2-1.4E-2-1.6E-2 OUTPUT CURRENT HIGH vs. OUTPUT VOLTAGE HIGH Typical Operating Characteristics (continued) V CC = 2.7V toc OUTPUT CURRENT LOW (A) 1.8E-2 1.6E-2 1.4E-2 1.2E-2 1.E-2 8.E-3 6.E-3 4.E-3 2.E-3 OUTPUT CURRENT LOW vs. OUTPUT VOLTAGE LOW V CC = 2.7V toc6-1.8e OUTPUT VOLTAGE HIGH (V).E OUTPUT VOLTAGE LOW (V) 4 4 ACTIVE CURRENT vs. INPUT FREQUENCY -2 toc7 2 2 ACTIVE CURRENT vs. INPUT FREQUENCY - toc8 3 CURRENT (ma) CURRENT (ma) V CC = 3.6V 1pF LOAD ON EACH TAP FREQUENCY (MHz) V CC = 3.6V 1pF LOAD ON EACH TAP FREQUENCY (MHz) Pin Description PIN NAME FUNCTION 1 IN Input 2 N.C. No Connection 7 GND Ground 13, 3, 12, 4, 11,, 1, 6, 9, 8 Tap 1 Tap 1 Tap Output Number 14 VCC 2.7V to 3.6V 4

5 Detailed Description The 1-tap delay line is a 3V version of the DS111. It has 1 equally spaced taps providing delays from 1ns to ns. The device is offered in a standard 14-pin TSSOP. The series delay lines provide a nominal accuracy of ±% or ±2ns, whichever is greater, at 3.3V and +2 C. The is characterized to operate from 2.7V to 3.6V. The reproduces the input-logic state at the tap 1 output after a fixed delay as specified by the dash-number suffix of the part number (Table 1). The produces both leading- and trailing-edge delays with equal precision. Each tap is capable of driving up to 1 74LS-type loads. Dallas Semiconductor can customize standard products to meet specific needs. Figure 1 is the DS111_L logic diagram and Figure 2 shows the timing diagram for the silicon delay line. Table 1. Part Number by Delay (tphl, tplh) PART T O T A L D EL A Y ( n s ) DELAY/TAP (ns) E E E E E E E E E E E- TAP1 TAP2 TAP9 TAP1 IN 1% 1% 1% 1% Figure 1. Logic Diagram PERIOD t RISE t FALL V IH 2.4V 2.4V IN V IL.6V 1.V 1.V.6V 1.V t WI t WI 1.V 1.V OUT Figure 2. Timing Diagram: Silicon Delay Line

6 Terminology Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t WI (Pulse Width): The elapsed time on the pulse between the 1.V point on the leading edge and the 1.V point on the trailing edge, or the 1.V point on the trailing edge and the 1.V point on the leading edge. t RISE (Input Rise Time): The elapsed time between the 2% and the 8% point on the leading edge of the input pulse. t FALL (Input Fall Time): The elapsed time between the 8% and the 2% point on the trailing edge of the input pulse. (Time Delay Rising): The elapsed time between the 1.V point on the leading edge of the input pulse and the 1.V point on the leading edge of any tap output pulse. t PHL (Time Delay, Falling): The elapsed time between the 1.V point on the trailing edge of the input pulse and the 1.V point on the trailing edge of any tap output pulse. Test Setup Description Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the. A precision pulse generator under software control produces the input waveform. Time delays are measured by a time interval counter (2ps resolution) connected PULSE GENERATOR START Z = Ω TIME INTERVAL COUNTER STOP VHF SWITCH CONTROL UNIT Figure 3. Test Circuit DEVICE UNDER TEST 6

7 between the input and each tap. Each tap is selected and connected to the counter by a VHF switch-control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE-488 bus. Output Each output is loaded with the equivalent of one 4Ω resistor in parallel with a 1pF capacitor. Delay is measured at the 1.V level on the rising and falling edge. Table 2. Test Conditions TRANSISTOR COUNT: 6813 Chip Information Package Information For the latest package outline information, go to com/packages. INPUT Ambient Temperature Supply Voltage (V CC ) Input Pulse Source Impedance Rise and Fall Time Pulse Width Period +2 C ±3 C 3.3V ±.1V CONDITION High = 3.V ±.1V Low =.V ±.1V Ω max 2ns max ns (1µs for - ns) 1µs (2µs for - ns) Note: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.