20MHz to 134MHz Spread-Spectrum Clock Modulator for LCD Panels DS1181L
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1 Rev 1; /0 0MHz to 13MHz Spread-Spectrum General Description The is a spread-spectrum clock modulator IC that reduces EMI in high clock-frequency-based, digital electronic equipment. Using an integrated phase-locked loop (PLL), the accepts an input clock signal in the range of 0MHz to 13MHz and delivers a spread-spectrum modulated output clock signal. The PLL modulates, or dithers, the output clock about the center input frequency at a pin-selectable magnitude, allowing direct EMI control and optimization. In addition, through an enable pin the dithering can be enabled or disabled for easy comparison of system performance during EMI testing. This same input pin also allows the output to be three-stated. By dithering the system clock, all the address, data, and timing signals generated from this signal are also dithered so that the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This is accomplished without changing clock rise/fall times or adding the space, weight, design time, and cost associated with mechanical shielding. The is provided in an -pin TSSOP package and operates over a full automotive temperature range of -0 C to +15 C. Applications LCD Panels for TVs, Desktop Monitors, and Notebook and Tablet PCs Automotive Telematics and Infotainment Printers Typical Operating Circuit appears at end of data sheet. Block Diagram Features Modulates a 0MHz to 13MHz Clock with Center Spread-Spectrum Dithering Selectable Spread-Spectrum Modulation Magnitudes of: ±0.5% ±1.0% ±1.5% ±.0% Low 75ps Cycle-to-Cycle Jitter Spread-Spectrum Disable Mode Pin Compatible with Alliance/PulseCore Semiconductor P00 Series Devices Clock Output Disable Low Cost Low Power Consumption 3.3V Single Voltage Supply -0 C to +15 C Temperature Range Small -Pin TSSOP Package Ordering Information PART TEMP RANGE PIN-PACKAGE E+ -0 C to +15 C TSSOP E+T -0 C to +15 C TSSOP +Denotes a lead(pb)-free/rohs-compliant package. T = Tape and reel. Pin Configuration CLKIN f IN = 0MHz TO 13MHz PLL WITH CENTER- DITHERED SPREAD- SPECTRUM SSO f SSO = 0MHz to 13MHz (DITHERED) TOP VIEW CLKIN CRSEL ENABLE LOGIC SSEN 3 SSO CRSEL CONFIGURATION DECODE AND CONTROL GND GND TSSOP 5 SSEN Maxim Integrated Products 1 For information on other Maxim products, visit Maxim s website at
2 ABSOLUTE MAXIMUM RATINGS Voltage Range on Relative to GND V to +.3V Voltage Range on Any Lead Relative to GND V to ( + 0.5V), not to exceed +.3V Operating Temperature Range...-0 C to +15 C Storage Temperature Range C to +15 C Soldering Temperature...See J-STD-00 Specification Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -0 C to +15 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage (Note 1) V 0. x + Input Logic 1 V IH x Input Logic 0 V IL -0.3 V Input Logic Float (SSEN, CRSEL) I FLOAT 0V < V IN < ±1 μa SSO < 0MHz 15 SSO Load C L 0MHz SSO < 13MHz 7 CLKIN Frequency f IN 0 13 MHz CLKIN Duty Cycle f INDC 0 0 % V pf DC ELECTRICAL CHARACTERISTICS ( = +3.0V to +3.V, T A = -0 C to +15 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current I CC C L = 7pF, f IN = 13MHz 1 ma //CLKIN Input Leakage I IL:1 0V < V IN < μa CRSEL/SSEN Input Leakage I IL: 0V < V IN < μa Output Leakage (SSO) I OZ SSEN = float μa Low-Level Output Voltage (SSO) V OL I OL = ma 0. V High-Level Output Voltage (SSO) V OH I OH = -ma. V AC ELECTRICAL CHARACTERISTICS ( = +3.0V to +3.V, T A = -0 C to +15 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SSO Duty Cycle f SSODC Measured at / 0 0 % SSO Rise Time t R C L = 7pF 1 ns SSO Fall Time t F C L = 7pF 1 ns Peak Cycle-to-Cycle Jitter t J T A = -0 C to +5 C,,000 cycles 75 ps Power-Up Time t POR (Note ) 50 ms Note 1: All voltages referenced to ground. Currents into the IC are positive and out of the IC are negative. Note : Time between power applied to device and stable output.
3 (T A = +5 C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 1 ICC (ma) CLKIN = 13MHz CLKIN = MHz CLKIN = 0MHz toc01 ICC (ma) 1 SUPPLY CURRENT vs. TEMPERATURE CLKIN = 13MHz CLKIN = MHz CLKIN = 0MHz Typical Operating Characteristics toc0 ICC (ma) SUPPLY CURRENT vs. FREQUENCY 1 = 3.V = 3.0V toc03 C L = 7pF (V) 0-0 C L = 7pF 0 1 TEMPERATURE ( C) C L = 7pF FREQUENCY (MHz) DUTY CYCLE (%) DUTY CYCLE vs. SUPPLY VOLTAGE CLKIN = 7MHz toc0 DUTY CYCLE (%) DUTY CYCLE vs. TEMPERATURE CLKIN = 7MHz toc05 ATTENUATION (db) SPECTRUM ATTENUATION vs. FREQUENCY AT DIFFERENT DITHER AMPLITUDES f OUT = 7MHz 0.5% ±1.5% ±1% db 13dB 15dB 17dB ±% toc (V) TEMPERATURE ( C) 1 RBW = 10KHz CENTER DITHER FREQUENCY (MHz) 3
4 PIN NAME FUNCTION 1 CLKIN Clock Input. 0MHz to 13MHz clock input (f IN ). 3 GND Ground Pin Description Spread-Spectrum Magnitude Select Inputs. These digital inputs select the desired spread-spectrum magnitude as shown in the table below. MAGNITUDE SELECTED (%) 0 0 ± ± ± ±0.5 5 SSEN SSO Spread-Spectrum Enable. Three-level input to enable/disable spread-spectrum and to three-state the output. 0 = Power-up/spread-spectrum enabled. Float = SSO three-stated. 1 = Power-up/spread-spectrum disabled (not a bypass mode). Spread-Spectrum Clock Output. Outputs a center-dithered spread-spectrum version of the clock input at CLKIN. 7 CRSEL Supply Voltage Clock Range and Dither Rate Select. Three-level input that determines the dither rate. See the Detailed Description section for details. CRSEL CLKIN RANGE (MHz) DITHER RATE 0 to 13 Float 33 to to 3 f IN /3 Detailed Description The modulates an input clock to generate a center-dithered spread-spectrum output. A 0MHz to 13MHz clock is applied to the CLKIN pin. An internal PLL dithers the output clock about its center frequency at a user-selectable magnitude. Spread-Spectrum Dither Magnitude The can generate dither magnitudes up to ±%. The desired magnitude is selected using input pins and as shown in Table 1. Table 1. Dither Magnitude Spread-Spectrum Dither Rate The output spread-spectrum dither rate is fixed at f IN /3. Table. Dither Rate CRSEL CLKIN RANGE (MHz) 0 to 13 Float 33 to to 3 DITHER RATE f IN /3 MAGNITUDE SELECTED (%) 0 0 ± ± ± ±0.5
5 Spread-Spectrum Enable On power-up, the output clock (SSO) remains three-stated until the internal PLL reaches a stable frequency. The SSEN input can be used to disable the spread-spectrum modulation and to three-state the SSO output. If the SSEN pin is pulled high, the spread-spectrum modulation is turned off, but the device still uses the internal PLL to generate the clock signal at SSO. If the SSEN pin is floated, the output is three-stated. Applications Information Power-Supply Decoupling To achieve best results, it is highly recommended that a decoupling capacitor is used on the IC power-supply pins. Typical values of decoupling capacitors are 0.01µF and 0.1µF. Use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the and GND pins of the IC to minimize lead inductance. IF SSEN = 1 f IN + (0.5%, 1.0%, 1.5%, OR.0% OF f IN ) f IN f IN - (0.5%, 1.0%, 1.5%, OR.0% OF f IN ) DITHER AMOUNT (±0.5%, ±1.0%, ±1.5%, OR ±.0%) f SSO 1 DITHER CYCLE RATE CLKIN RANGE (MHz) DITHER RATE 0 TO 13 f IN /3 TIME Figure 1. Spread-Spectrum Frequency Modulation Typical Operating Circuit f IN = 0MHz TO 13MHz CLKIN CRSEL DECOUPLING CAPACITOR GND SSO SSEN f SSO DITHERED NOTE: IN THE ABOVE CONFIGURATION WITH,, AND SSEN CONNECTED TO GND AS WELL AS CRSEL CONNECTED TO, THE DEVICE IS CONFIGURED WITH A SPREAD-SPECTRUM MAGNITUDE OF ±.0%, AND ALLOWS A CLKIN BETWEEN 0MHz and 3MHz. Package Information For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. TSSOP H
6 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 0 11/07 Initial release. 1 /0 Increased the absolute maximum ratings range from +3.3V to +.3V. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 10 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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19-5903; Rev 0; 6/11 General Description The family of supervisory circuits monitors voltages from +1.1V to +5V using a factory-set reset threshold. The MAX16084/MAX16085/MAX16086 offer a manual reset
TOP VIEW. Maxim Integrated Products 1
19-2213; Rev 0; 10/01 Low-Jitter, Low-Noise LVDS General Description The is a low-voltage differential signaling (LVDS) repeater, which accepts a single LVDS input and duplicates the signal at a single
TOP VIEW. HD Recorders TSSOP
9-446; Rev ; /8 EVALUATION KIT AVAILABLE Low-Cost, -Channel, HD/PS/SD/BP General Description The / integrated -channel video filters for high-definition (HD), progressive-scan (PS), standard-definition
10Ω, Quad, SPST, +3V Logic-Compatible Analog Switches
19-218; Rev 1; 9/8 1Ω, Quad, SPST, +3V Logic-Compatible General Description Maxim s analog switches feature low on-resistance (1Ω max) and 1.5Ω onresistance matching between channels. These switches are
Low-Charge Injection, 16-Channel, High-Voltage Analog Switches MAX14800 MAX14803
19-4484; Rev 1; 9/09 Low-Charge Injection, 16-Channel, General Description The provide high-voltage switching on 16 channels for ultrasonic imaging and printer applications. The devices utilize HVCMOS
High-Voltage Switch for Wireless Power
General Description The MAX20304 is a DPST switch intended for wirelesspower-circuit applications. The new application for the portable device is the magnetic card reader. There has been a method to use
MAX4751/MAX4752/MAX Ω, Low-Voltage, Single-Supply Quad SPST Analog Switches
// General Description The // are low on-resistance, low-voltage, quad, single-pole/single-throw (SPST) analog switches that operate from a single +1.V to +3.V supply. These devices have fast switching
ICS NETWORKING AND PCI CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET Description The is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental
Receiver for Optical Distance Measurement
19-47; Rev ; 7/9 EVALUATION KIT AVAILABLE Receiver for Optical Distance Measurement General Description The is a high-gain linear preamplifier for distance measurement applications using a laser beam.
LOCO PLL CLOCK MULTIPLIER. Features
DATASHEET ICS501A Description The ICS501A LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
PI6C557-03B. PCIe 3.0 Clock Generator with 2 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TSSOP) Block Diagram
Features ÎÎPCIe 3.0 compliant à à PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V
ICS7151A-50 SPREAD SPECTRUM CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS7151A-50 Description The ICS7151A-50 is a clock generator for EMI (Electromagnetic Interference) reduction. Spectral peaks are attenuated by modulating the system clock frequency. Down or
IDT5V60014 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET IDT5V60014 Description The IDT5V60014 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques.
MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers
General Description The are single receivers designed for RS-48 and RS-4 communication. These devices guarantee data rates up to Mbps, even with a 3V power supply. Excellent propagation delay (1ns max)
Description. This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz
PT7C4512 Features Description Zero ppm multiplication error This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz generate a high quality, high frequency clock outputs
TOP VIEW COUT1 COM2. Maxim Integrated Products 1
19-77; Rev ; 7/4.75Ω, Dual SPDT Audio Switch with General Description The dual, single-pole/double-throw (SPDT) switch operates from a single +2V to +5.5V supply and features rail-to-rail signal handling.
MAX15070A/MAX15070B 7A Sink, 3A Source, 12ns, SOT23 MOSFET Drivers
General Description The /MAX15070B are high-speed MOSFET drivers capable of sinking 7A and sourcing 3A peak currents. The ICs, which are an enhancement over MAX5048 devices, have inverting and noninverting
Pin Configurations/Functional Diagrams/Truth Table COM COM GND MAX4644 OFF OFF. Maxim Integrated Products 1
9-7; Rev ; 3/ High-Speed, Low-Voltage, 4Ω, General Description The is a single-pole/double-throw (SPDT) switch that operates from a single supply ranging from +.8V to +.V. It provides low 4Ω on-resistance
ICS QUAD PLL CLOCK SYNTHESIZER. Description. Features. Block Diagram PRELIMINARY DATASHEET
PRELIMINARY DATASHEET ICS348-22 Description The ICS348-22 synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock
5- to 10-Cell Li+ Protector with Cell Balancing
Rev 0; 4/08 5- to 10-Cell Li+ Protector with Cell Balancing General Description The provides full charge and discharge protection for 5- to 10-cell lithium-ion (Li+) battery packs. The protection circuit
I O 7-BIT POT REGISTER ADDRESS COUNT 7-BIT POT. CODE 64 (40h) DS3503
Rev 1; 3/9 NV, I2C, Stepper Potentiometer General Description The features two synchronized stepping digital potentiometers: one 7-bit potentiometer with RW as its output, and another potentiometer with
Single/Dual LVDS Line Receivers with In-Path Fail-Safe
9-2578; Rev 2; 6/07 Single/Dual LVDS Line Receivers with General Description The single/dual low-voltage differential signaling (LVDS) receivers are designed for high-speed applications requiring minimum
ICS650-40A ETHERNET SWITCH CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DTSHEET ICS650-40 Description The ICS650-40 is a clock chip designed for use as a core clock in Ethernet Switch applications. Using IDT s patented Phase-Locked Loop (PLL) techniques, the device takes a
PCI-EXPRESS CLOCK SOURCE. Features
DATASHEET ICS557-01 Description The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.
EVALUATION KIT AVAILABLE 3.5GHz Downconverter Mixers with Selectable LO Doubler. PART MAX2683EUE MAX2684EUE *Exposed pad TOP VIEW IFOUT+ IFOUT-
-; Rev ; / EVALUATION KIT AVAILABLE.GHz Downconverter Mixers General Description The MAX/MAX are super-high-performance, low-cost downconverter mixers intended for wireless local loop (WLL) and digital
6500V/µs, Wideband, High-Output-Current, Single- Ended-to-Differential Line Drivers with Enable
99 Rev ; /99 EVALUATION KIT AVAILABLE 65V/µs, Wideband, High-Output-Current, Single- General Description The // single-ended-todifferential line drivers are designed for high-speed communications. Using
27pF TO ADC C FILTER (OPTIONAL) Maxim Integrated Products 1
19-215; Rev 6; 9/6 EVALUATION KIT AVAILABLE RF Power Detectors in UCSP General Description The wideband (8MHz to 2GHz) power detectors are ideal for GSM/EDGE (MAX226), TDMA (MAX227), and CDMA (MAX225/MAX228)