670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters

Transcription

1 9-2827; Rev ; 4/04 670MHz LVDS-to-LVDS and Anything-to-LVDS General Description The are 670MHz, low-jitter, lowskew :2 splitters ideal for protection switching, loopback, and clock and signal distribution. The devices feature ultra-low.0ps(rms) random jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing errors. The MAX974 has a fail-safe LVDS input and LVDS outputs. The MAX975 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX974 features a fail-safe circuit that drives the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX975 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -V and overshoot of V CC + V. The are available in 0-pin µmax and 0-lead thin QFN with exposed pad packages, and operate from a single +3.3V supply over the -40 C to +85 C temperature range. Protection Switching Loopback Clock Distribution Applications Functional Diagram and Pin Configurations appear at end of data sheet. Features.0ps (RMS) Jitter (max) at 670MHz 80ps (P-P) Jitter (max) at 800Mbps Data Rate +3.3V Supply LVDS Fail-Safe Inputs (MAX974) Anything Input (MAX975) Accepts Differential CML/LVDS/LVPECL Power-Down Inputs Tolerate -.0V and V CC +.0V Low-Power CMOS Design 0-Lead µmax and Thin QFN Packages -40 C to +85 C Operating Temperature Range Conform to ANSI TIA/EIA-644 LVDS Standard IEC Level 4 ESD Rating Ordering Information PART TEMP RANGE PPACKAGE MAX974EUB -40 C to +85 C 0 µmax MAX974ETB* -40 C to +85 C 0 Thin QFN-EP** MAX975EUB -40 C to +85 C 0 µmax MAX975ETB* -40 C to +85 C 0 Thin QFN-EP** *Future product contact factory for availability. **EP = Exposed paddle. Typical Application Circuit CLOCK DISTRIBUTION MAX974 MAX976 ASIC CLK CLK IN MAX974 MAX976 ASIC CLK2 CLK IN Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS V CC to GND V to +4.0V, to GND V to +4.0V OUT_+, OUT_- to GND V to +4.0V PD0, PD to GND...-.4V to (V CC +.4V) Single-Ended and Differential Output Short-Circuit Duration (OUT_+, OUT_-)...Continuous Continuous Power Dissipation (T A = +70 C) 0-Pin µmax (derate 5.6mW/ C above +70 C)...444mW 0-Lead QFN (derate 24.4mW/ C above +70 C)...95mW Maximum Junction Temperature C Storage Temperature Range C to +50 C ESD Protection Human Body Model (R D =.5kΩ, C S = 00pF),, OUT_+, OUT_-... ±2kV Other Pins (V CC, PD0, PD)...2kV IEC Level 4 (R D = 330Ω, C S = 50pF) Contact Discharge,, OUT_+, OUT_-...±8kV Air-Gap Discharge,, OUT_+, OUT_-...±5kV Lead Temperature (soldering, 0s) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V CC = +3.0V to +3.6V, R L = 00Ω ±%, PD_ = high, differential input voltage V ID = 0.05V to.2v, MAX974 input common-mode voltage V CM = V ID /2 to (2.4V - V ID /2 ), MAX975 input common-mode voltage V CM = V ID /2 to (V CC - V ID /2 ), T A = -40 C to +85 C, unless otherwise noted. Typical values are at V CC = +3.3V, V ID = 0.2V, V CM = +.25V, T A = +25 C.) (Notes, 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIFFERENTIAL INPUT (, ) Differential Input High Threshold VTH +50 mv Differential Input Low Threshold VTL -50 mv Input Current I, I Figure µa Power-Off Input Current MAX974 V CC = 0V or open, Figure I, V = 3.6V or 0V, V = 3.6V I MAX975 or 0V, V CC = 0V or open, Figure µa Fail-Safe Input Resistors R IN V CC = 3.6V, 0V or open, Figure (MAX974) R IN Input Resistors (MAX975) RIN3 V CC = 3.6V, 0V or open, Figure kω Input Capacitance C IN or to GND (Note 4) 4.5 pf LVTTL/LVCMOS INPUTS (PD0, PD) Input High Voltage V IH 2.0 Input Low Voltage V IL V V CC + -.0V PD_ 0V -.5 ma Input Current I IN 0V PD_ V CC µa V CC PD_ V CC +.0V +.5 ma kω V LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Voltage V OD Figure mv Change in Differential Output Voltage Between Logic States V OD Figure mv Offset Voltage V OS Figure V 2

3 DC ELECTRICAL CHARACTERISTICS (continued) (V CC = +3.0V to +3.6V, R L = 00Ω ±%, PD_ = high, differential input voltage V ID = 0.05V to.2v, MAX974 input common-mode voltage V CM = V ID /2 to (2.4V - V ID /2 ), MAX975 input common-mode voltage V CM = V ID /2 to (V CC - V ID /2 ), T A = -40 C to +85 C, unless otherwise noted. Typical values are at V CC = +3.3V, V ID = 0.2V, V CM = +.25V, T A = +25 C.) (Notes, 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Change in Offset Voltage Between Logic States Fail-Safe Differential Output Voltage (MAX974) V OS Figure mv V OD Figure mv Differential Output Resistance R DIFF V CC = 3.6V or 0V Ω Power-Down Single-Ended Output Current Power-Off Single-Ended Output Current I PD I OFF PD_ = low PD0, PD = low, V CC = 0V or open V OUT_+ = open, V OUT_- = 3.6V or 0V V OUT_- = open, V OUT_+ = 3.6V or 0V V OUT_+ = open, V OUT_- = 3.6V or 0V V OUT_- = open, V OUT_+ = 3.6V or 0V -.0 ± µa -.0 ± µa V ID = +50mV or -50mV, V OUT_+ = 0V or Output Short-Circuit Current IOS V CC V ID = +50mV or -50mV, V OUT_- = 0V or V CC ma Differential Output Short-Circuit Current Magnitude I OSD V ID = +50mV or -50mV, V OD = 0V (Note 4) 5 ma Supply Current I CC PD0 = V CC, PD = 0V or PD0 = 0V, PD = V CC 7 26 PD0 = Vcc, PD = Vcc ma Power-Down Supply Current I CCPD PD, PD0 = 0V µa Output Capacitance C O OUT_+ or OUT_- to GND (Note 4) 5.2 pf 3

4 AC ELECTRICAL CHARACTERISTICS (V CC = +3.0V to +3.6V, R L = 00Ω±%, C L = 5pF, differential input voltage V ID = 0.5V to.2v, MAX974 input common-mode voltage, V CM = V ID /2 to (2.4V - V ID /2 ), MAX975 input common-mode voltage V CM = V ID /2 to (V CC - V ID /2 ), PD_ = high, T A = -40 C to +85 C, unless otherwise noted. Typical values are at V CC = +3.3V, V ID = 0.2V, V CM = +.25V, T A = +25 C.) (Notes 5, 6, 7) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High-to-Low Propagation Delay t PHL Figures 4, ns Low-to-High Propagation Delay t PLH Figures 4, ns Added Deterministic Jitter t DJ Figures 4, 5 (Note 8) 80 ps (P-P) Added Random Jitter t RJ Figures 4, 5.0 ps (RMS) Pulse Skew t PLH - t PHL t SKP Figures 4, ps Output-to-Output Skew t SKOO Figure ps Part-to-Part Skew t SKPP Figures 4, 5 (Note 9) t SKPP2 Figures 4, 5 (Note 0).9 Rise Time t R Figures 4, ps Fall Time t F Figures 4, ps Power-Down Time t PD Figures 7, ns PD0, PD = L H, Figures 7, µs Power-Up Time t PU PD0 = H, PD = L H, Figures 7, PD = H, PD0 L H, Figures 7, ns ns Maximum Data Rate D RMAX Figures 4, 5, V OD 250mV (Note ) 800 Mbps Maximum Switching Frequency f MAX Figures 4, 5, V OD 250mV (Note ) 670 MHz f IN = 670MHz Switching Supply Current I CCSW PRBS Supply Current I CCPR D R = 800Mbps, PRBS input ma ma Note : Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except V TH, V TL, V ID, V OD, and V OD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 00% tested at T A = +25 C. Note 3: Tolerance on all external resistors (including figures) is ±%. Note 4: Guaranteed by design. Note 5: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. Note 6: C L includes scope probe and test jig capacitance. Note 7: Pulse-generator output for differential inputs, (unless otherwise noted): f = 670MHz, 50% duty cycle, R O = 50Ω, t R = 700ps, and t F = 700ps (0% to 00%). Pulse-generator output for single-ended inputs PD0, PD: t R = t F =.5ns (0.2V CC to 0.8V CC ), 50% duty cycle, V OH = V CC +.0V settling to V CC, V OL = -.0V settling to zero, f = 0kHz. Note 8: Pulse-generator output for t DJ : V OD = 0.5V, V OS =.25V, data rate 800Mbps, PRBS, R O = 50Ω, t R = 700ps, and t F = 700ps (0% to 00%). Note 9: t SKPP is the magnitude of the difference of any differential propagation delays between devices operating under identical conditions. Note 0: t SKPP2 is the magnitude of the difference of any differential propagation delays between devices operating over rated conditions. Note : Meets all AC specifications. 4

5 Typical Operating Characteristics ((MAX974) V CC = +3.3V, V ID = 0.5V, V CM =.25V, T A = +25 C, R L = 00Ω ±%, C L = 5pf, PD_ = V CC, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) MAX974 toc0 DIFFERENTIAL OUTPUT VOLTAGE (mv) DIFFERENTIAL OUTPUT VOLTAGE vs. FREQUENCY FREQUENCY (MHz) MAX974 toc02 RISE/FALL TIME (ps) OUTPUT RISE/FALL TIME vs. TEMPERATURE t R TEMPERATURE ( C) t F MAX974 toc03 DIFFERENTIAL PROPAGATION DELAY (ns) DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE t PHL t PLH MAX974 toc04 OUTPUT-TO-OUTPUT SKEW (ps) OUTPUT-TO-OUTPUT SKEW vs. TEMPERATURE MAX974 toc05 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. FREQUENCY MAX974 toc TEMPERATURE ( C) TEMPERATURE ( C) FREQUENCY (MHz) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. DATA RATE PRBS MAX974 toc07 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX974 toc08 RISE/FALL TIME (ps) OUTPUT RISE/FALL TIME vs. SUPPLY VOLTAGE t F t R MAX974 toc DATA RATE (Mbps) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 5

6 Typical Operating Characteristics (continued) ((MAX974) V CC = +3.3V, V ID = 0.5V, V CM =.25V, T A = +25 C, R L = 00Ω ±%, C L = 5pf, PD_ = V CC, unless otherwise noted.) DIFFERENTIAL PROPAGATION DELAY (ns) DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE t PHL t PLH SUPPLY VOLTAGE (V) MAX974 toc0 OUTPUT-TO-OUTPUT SKEW (ps) OUTPUT-TO-OUTPUT SKEW vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) MAX974 toc DIFFERENTIAL OUTPUT VOLTAGE (mv) DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE LOAD RESISTANCE (Ω) MAX974 toc2 PROPAGATION DELAY (ns) PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE t PLH t PHL MAX INPUT COMMON-MODE VOLTAGE (V) MAX974 toc3a PROPAGATION DELAY (ns) PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE t PHL t PLH INPUT COMMON-MODE VOLTAGE (V) MAX974 toc3b OUTPUT-TO-OUTPUT SKEW (ps) OUTPUT-TO-OUTPUT SKEW vs. INPUT COMMON-MODE VOLTAGE MAX974 MAX974 toc4a OUTPUT-TO-OUTPUT SKEW (ps) OUTPUT-TO-OUTPUT SKEW vs. INPUT COMMON-MODE VOLTAGE MAX975 MAX974 toc4b INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) 6

7 µmax PIN QFN NAME Noninverting Differential Input 2 2 Inverting Differential Input 3 3 GND Ground 4 4 PD 5 5 PD0 6 6 OUT0- Inverting LVDS Output OUT0+ Noninverting LVDS Output V CC Power Supply 9 9 OUT- Inverting LVDS Output 0 0 OUT+ Noninverting LVDS Output EP Exposed Pad FUNCTION Pin Description LVTTL/LVCMOS Input. OUT+, OUT- are high impedance to ground when PD is low. Internal pulldown resistor to GND. LVTTL/LVCMOS Input. OUT0+, OUT0- are high impedance to ground when PD0 is low. Internal pulldown resistor to GND. Exposed Pad. Solder to ground. Detailed Description The are 670MHz, low-jitter, lowskew :2 splitters ideal for protection switching, loopback, and clock and signal distribution. The devices feature ultra-low 80ps P-P deterministic jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing error. The MAX974 has a fail-safe LVDS input and LVDS outputs. The MAX975 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX974 features a fail-safe circuit that drives the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX975 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -V and overshoot of VCC + V. The are available in 0-pin µmax and 0-lead thin QFN packages, and operate from a single +3.3V supply over the -40 C to +85 C temperature range. Current-Mode LVDS Outputs The LVDS outputs use a current-steering configuration. This approach results in less ground bounce and less output ringing, enhancing noise margin and system speed performance. A differential output voltage is produced by steering current through the parallel combination of the integrated differential output resistor and transmission line impedance/termination resistor. When driving a 00Ω termination resistor, a differential voltage of 250mV to 475mV is produced. For loads greater than 00Ω, the output voltage is larger, and for loads less than 00Ω, the output voltage is smaller. See the Differential Output Voltage vs. Load Resistance curve in Typical Operating Characteristics for more information. The outputs are short-circuit current limited for single-ended and differential shorts. MAX974 Input Fail-Safe The fail-safe feature of the MAX974 sets the outputs high when the differential input is: Open Undriven and shorted Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the outputs and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver output is in high impedance. A shorted input can occur because of a cable failure. 7

8 When the input is driven with a differential signal of V ID = 50mV to.2v within a voltage range of 0 to 2.4V, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and terminated, an internal resistor in the fail-safe circuit pulls the input above VCC - 0.3V, activating the fail-safe circuit and forcing the outputs high (Figure ). Overshoot and Undershoot Voltage Protection The are designed to protect the power-down inputs (PD0 and PD) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above VCC or below GND by up to V, an internal circuit limits input current to.5ma. Applications Information Power-Supply Bypassing Bypass the V CC pin with high-frequency surface-mount ceramic 0.µF and 0.00µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to V CC. Differential Traces Input and output trace characteristics affect the performance of the. Use controlledimpedance differential traces (00Ω typ). To reduce radiated noise and ensure that noise couples as common mode, route the differential input and output signals within a pair close together. Reduce skew by matching the electrical length of the two signal paths that make up the differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. Cables and Connectors Interconnect for LVDS typically has a controlled differential impedance of 00Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Termination The require external input and output termination resistors. For LVDS, connect an input Table. Input Function Table INPUT () - () +50mV -50mV -50mV < VID < +50mV MAX975 MAX974 Open Open, undriven short, or undriven parallel termination OUTPUTS (OUT_+) - (OUT_-) termination resistor across the differential input and at the far end of the interconnect driven by the LVDS outputs. Place the input termination resistor as close to the receiver input as possible. Termination resistors should match the differential impedance of the transmission line. Use % surface-mount resistors. H L Indeterminate Table 2. Power-Down Function Table H H Both outputs enabled L or open L or open L or open High High L or open R IN R IN V CC R IN2 COMPARATOR V CC - 0.3V MAX974 INTERNAL FAIL-SAFE CIRCUIT Figure. Input Structure Shutdown to minimum power, outputs high impedance to ground H OUT0 enabled, OUT high impedance to ground OUT enabled, OUT0 high impedance to ground DIFFERENTIAL RCVR TO OUTPUT PD PD0 OUT_+, OUT_- V CC R IN3 R IN3 MAX975 INPUT 8

9 .25V.20V.25V.20V Figure 2. V OD Test Circuit OUT_+ V OD OUT_ - R L 5kΩ 5kΩ V TEST = 0 TO V CC.25V.20V.25V.20V Figure 3. V OS Test Circuit OUT+ 5kΩ OUT_+ R L /2 R L /2 OUT_ - VOS R L OUT- C L C L 5kΩ V TEST = 0 TO V CC OUT0+ 5kΩ PULSE GENERATOR OUT0- R L 50Ω 50Ω C L C L 5kΩ Figure 4. Transition Time, Propagation Delay, and Output-to-Output Skew Test Circuit The feature an integrated differential output resistor. This resistor reduces jitter by damping reflections produced by a mismatch between the transmission line and termination resistor at the far end of the interconnect. Board Layout Separate the differential and single-ended signals to reduce crosstalk. A four-layer printed circuit board with separate layers for power, ground, differential signals, and single-ended logic signals is recommended. Separate the differential signals from the logic signals with power and ground planes for best results. IEC Level 4 ESD Protection The IEC standard (Figure 9) specifies ESD tolerance for electronic systems. The IEC model specifies a 50pF capacitor that is discharged into the device through a 330Ω resistor. The MAX974/ MAX975 differential inputs and outputs are rated for IEC level 4 (±8kV Contact Discharge and ±5kV Air-Gap Discharge). The Human Body Model (HBM, Figure 0) specifies a 00pF capacitor that is discharged into the device through a.5kω resistor. IEC level 4 discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor. 9

10 V OD- t PLH t PHL OUT_- OUT_+ V OS = ((V OUT_ +) + (V OUT_- ))/2 80% 80% V OD+ 0V 0V (OUT_+) - (OUT_-) 20% 20% t R t F Figure 5. Transition Time and Propagation Delay Timing OUT0+ OUT+ OUT0- OUT- t SKOO tskoo Figure 6. Output-to-Output Skew 0

11 PD_ OUT_+ WHEN V ID = +50mV OUT_- WHEN V ID = -50mV OUT_+ WHEN V ID = -50mV OUT_- WHEN V ID = +50mV t PD t PD t PU 50% 50% 50% 50% t PU V CC + V V CC V CC / V V OH.25V.25V V OL Figure 7. Power-Up/Down Delay Waveform MAX974 MAX975 OUT+ R L /2.25V.20V OUT- R L /2.25V.25V.20V OUT0+ R L /2 OUT0- R L /2.25V PULSE GENERATOR 50Ω Figure 8. Power-Up/Down Delay Test Circuit

12 HIGH- VOLTAGE DC SOURCE R C 50Ω TO 00Ω CHARGE-CURRENT- LIMIT RESISTOR Cs 50pF R D 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGH- VOLTAGE DC SOURCE R C MΩ CHARGE-CURRENT- LIMIT RESISTOR Cs 00pF R D.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 9. IEC Contact Discharge ESD Test Model Figure 0. Human Body ESD Test Model Pin Configurations Functional Diagram TOP VIEW OUT+ OUT- V CC OUT0+ GND PD MAX974 MAX OUT+ OUT- V CC OUT0+ GND PD MAX974 MAX MAX974 MAX975 DIFFERENTIAL RECEIVER LVDS DRIVER OUT+ OUT- PD0 5 µmax 6 OUT0- PD0 5 EXPOSED PAD 6 OUT0- THIN QFN (LEADS UNDER PACKAGE) LVDS DRIVER 0 OUT0+ OUT0- PD PD0 TRANSISTOR COUNT: 693 PROCESS: CMOS Chip Information 2

13 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 0.6±0. 0 e ÿ 0.50±0. 0.6±0. TOP VIEW 4X S H BOTTOM VIEW 0 DIM A A MIN MAX MIN MAX A D D2 E E2 H L L b e c S α INCHES MILLIMETERS REF REF BSC BSC REF REF LUMAX.EPS D2 E2 GAGE PLANE A2 A c D b A α E L L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 0L umax/usop APPROVAL DOCUMENT CONTROL NO. REV I 3

14 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to PIN INDEX AREA D E A A A2 L DETAIL A E2 LC b e N C0.35 D2 L C k L L PIN ID [(N/2)-] x e REF. 6, 8, &0L, DFN THIN.EPS e e A DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY TITLE: PACKAGE OUTLINE, 6, 8 & 0L, TDFN, EXPOSED PAD, 3x3x0.80 mm APPROVAL DOCUMENT CONTROL NO. REV D 2 COMMON DIMENSIONS SYMBOL MIN. MAX. A D E A L k 0.25 MIN. A REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-] x e T ± ± BSC MO229 / WEEA 0.40± REF T ± ± BSC MO229 / WEEC 0.30± REF T ± ± BSC MO229 / WEED ± REF PROPRIETARY INFORMATION TITLE: APPROVAL DALLAS SEMICONDUCTOR PACKAGE OUTLINE, 6, 8 & 0L, TDFN, EXPOSED PAD, 3x3x0.80 mm DOCUMENT CONTROL NO REV. D 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 4 Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.