8-Port, 5.5V Constant-Current LED Driver with LED Fault Detection

Transcription

1 ; Rev 2; 7/5 8-Port, 5.5V Constant-Current LE river with General escription The serial-interfaced LE driver provides eight open-drain, constant-current sinking LE driver outputs rated at 5.5V. The operates from a 3V to 5.5V supply. The supply and the LEs supply may power up in any order. The constant-current outputs are programmed together to up to 55mA using a single external resistor. The operates with a 25Mb, industry-standard, 4-wire serial interface. The includes circuitry that automatically detects open-circuit LEs. Fault status is loaded into the serial interface shift register when LE goes high, and is automatically shifted out on OUT when the next data transmission is shifted in. The uses the industry-standard shift-registerplus-latch-type serial interface. The driver accepts data shifted into an 8-bit shift register using data input IN and clock input CLK. Input data appears at the output OUT eight clock cycles later to allow cascading of multiple s. The latch-enable input LE loads the 8 bits of shift register data into an 8-bit output latch to set which LEs are on and which are off. The outputenable input OE gates all eight outputs on and off, and is fast enough to be used as a PWM input for LE intensity control. For safety-related applications requiring a watchdog timer, refer to the MAX6978 data sheet that includes a fail-safe feature that blanks the display if the serial interface becomes inactive for more than 1s. The is one of a family of 12 shift-register-pluslatch-type LE drivers. The family includes 8-port and 16-port types, with 5.5V- or 36V-rated LE outputs, with and without open-circuit LE detection and watchdog. All versions operate from a 3V to 5.5V supply, and are specified over the -4 C to +125 C temperature range. Features 25Mb Industry-Standard 4-Wire Serial Interface at 5V 3V to 5.5V Logic Supply 8 Constant-Current LE Outputs Rated at 5.5V Up to 55mA Continuous Current per Output Output Current Programmed by Single Resistor 3% Current Matching Between Outputs 6% Current Matching Between ICs Reports Open-Circuit LE Faults -4 C to +125 C Temperature Range TOP VIEW Ordering Information PART TEMP RANGE PIN-PACKAGE AUE -4 C to +125 C 16 TSSOP-EP* APE -4 C to +125 C 16 PIP AAE -4 C to +125 C 16 SSOP *EP = Exposed pad. Typical Application Circuit and Selector Guide appear at end of data sheet. Pin Configuration Variable Message Signs Marquee isplays Point-of-Order Signs Traffic Signs Gaming Features Architectural Lighting Applications GN 1 16 V+ IN CLK LE OUT OUT1 OUT2 OUT AUE APE AAE TSSOP/PIP/SSOP 15 SET 14 OUT 13 OE 12 OUT7 11 OUT6 1 OUT5 9 OUT4 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/allas irect! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Voltage (with respect to GN) V V to +6V OUT_...-.3V to +6V IN, CLK, LE, OE, SET...-.3V to (V+ +.3V) OUT Current...±1mA OUT_ Sink Current...6mA Total GN Current...48mA Continuous Power issipation (T A = +7 C) 16-Pin SSOP (derate 7.1mW/ C above +7 C)...571mW 16-Pin PIP (derate 1.5mW/ C above +7 C)...842mW 16-Pin TSSOP (derate 21.3mW/ C above +7 C)...172mW Operating Temperature Range...-4 C to +125 C Junction Temperature C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Typical Operating Circuit, V+ = 3V to 5.5V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V+ = 5V,.) (Note 1) PARAMETER SYMBOL CONITIONS MIN TYP MAX UNITS Operating Supply Voltage V V Output Voltage V OUT 5.5 V Standby Current (Interface Idle, All Output Ports High Impedance, R SET = 36Ω) Standby Current (Interface Running, All Output Ports High Impedance, R SET = 36Ω) Supply Current (Interface Idle, All Output Ports Active Low, R SET = 36Ω) Input High Voltage IN, CLK, LE, OE Input Low Voltage IN, CLK, LE, OE Hysteresis Voltage IN, CLK, LE, OE Input Leakage Current IN, CLK, LE, OE I + All logic inputs at V+ or GN, OUT unloaded I + f CLK = 5MHz, OE = V+, IN and LE = V+ or GN, OUT unloaded I + All logic inputs at V+ or GN, OUT unloaded Output High-Voltage OUT V OH I SOURCE = 4mA ma ma 1 25 ma V IH.7 V+ V V IL.3 V+ V V I.8 V I IH, I IL µa V + -.5V Output Low Voltage V OL I SINK = 4mA.5 V Output Current OUT_ I OUT V+ = 4.5V to 5.5V, V OUT =.8V to 2.5V, R SET = 36Ω ma Output Leakage Current OUT_ I LEAK OE = V+, V OUT = V+ 1 µa Watchdog Timeout t W 1 s V 2

3 5V TIMING CHARACTERISTICS (Typical Operating Circuit, V+ = 4.5V to 5.5V, T A = T MIN to T MAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONITIONS MIN TYP MAX UNITS CLK Clock Period t CP 4 ns CLK Pulse Width High t CH 19 ns CLK Pulse Width Low t CL 19 ns IN Setup Time t S 4 ns IN Hold Time t H 8 ns OUT Propagation elay t O ns OUT Rise and Fall Time t R, t F C OUT = 1pF, 2% to 8% 1 ns LE Pulse Width High t LW 2 ns LE Pulse Width (Fault-etection ata Valid) t LF 2 ns LE Setup Time t LS 1 ns LE Rising to OUT_ Rising elay t LRR (Note 2) 1 ns LE Rising to OUT_ Falling elay t LRF (Note 2) 28 ns CLK Rising to OUT_ Rising elay t CRR (Note 2) 1 ns CLK Rising to OUT_ Falling elay t CRF (Note 2) 31 ns OE Rising to OUT_ Rising elay t OEH 1 ns OE Falling to OUT_ Falling elay t OEL 3 ns LE Output OUT_ Turn-On Fall Time t f 8% to 2% 2 ns LE Output OUT_ Turn-Off Rise Time t r 2% to 8% 12 ns 3

4 3.3V TIMING CHARACTERISTICS (Typical Operating Circuit, V+ = 3V to 5.5V, T A = T MIN to T MAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONITIONS MIN TYP MAX UNITS CLK Clock Period t CP 52 ns CLK Pulse Width High t CH 24 ns CLK Pulse Width Low t CL 24 ns IN Setup Time t S 4 ns IN Hold Time t H 8 ns OUT Propagation elay t O ns OUT Rise and Fall Time C OUT = 1pF, 2% to 8% 1 ns LE Pulse Width High t LW 2 ns LE Pulse Width (Fault-etection ata Valid) t LW 2 ns LE Setup Time t LS 15 ns LE Rising to OUT_ Rising elay 1 ns LE Rising to OUT_ Falling elay 31 ns CLK Rising to OUT_ Rising elay 1 ns CLK Rising to OUT_ Falling elay 33 ns OE Rising to OUT_ Rising elay t OEH 1 ns OE Falling to OUT_ Falling elay t OEL 33 ns LE Output OUT_ Turn-On Fall Time t f 8% to 2% 2 ns LE Output OUT_ Turn-Off Rise Time t r 2% to 8% 12 ns Note 1: All parameters tested at. Specifications over temperature are guaranteed by design. Note 2: See Figure 3. (, unless otherwise noted.) Typical Operating Characteristics SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE (INTERFACE ILE, ALL OUTPUTS OFF, R SET = 72Ω) toc1 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE (INTERFACE ILE, ALL OUTPUTS OFF, R SET = 36Ω) toc2 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE (INTERFACE ILE, ALL OUTPUTS ON, R SET = 72Ω) toc SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 4

5 (, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE (INTERFACE ILE, ALL OUTPUTS ON, R SET = 36Ω) toc4 Typical Operating Characteristics (continued) PORT OUTPUT CURRENT vs. PORT OUTPUT VOLTAGE (R SET = 72Ω, V+ = 3.3V) toc5 PORT OUTPUT CURRENT vs. PORT OUTPUT VOLTAGE (R SET = 36Ω, V+ = 3.3V) toc SUPPLY VOLTAGE (V) PORT OUTPUT VOLTAGE (V) PORT OUTPUT VOLTAGE (V) PORT OUTPUT CURRENT vs. PORT OUTPUT VOLTAGE (R SET = 72Ω, V+ = 5.V) toc7 PORT OUTPUT CURRENT vs. PORT OUTPUT VOLTAGE (R SET = 36Ω, V+ = 5.V) toc PORT OUTPUT CURRENT vs. SUPPLY VOLTAGE (R SET = 72Ω, V OUT = 2V) toc PORT OUTPUT VOLTAGE (V) PORT OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) PORT OUTPUT CURRENT vs. SUPPLY VOLTAGE (R SET = 36Ω, V OUT = 2V) toc PORT OUTPUT CURRENT vs. SET RESISTANCE toc SUPPLY VOLTAGE (V) SET RESISTANCE (Ω) 5

6 PIN NAME FUNCTION 1 GN Ground 2 IN Serial-ata Input. ata is loaded into the internal 8-bit shift register on CLK s rising edge. 3 CLK Serial-Clock Input. ata is loaded into the internal 8-bit shift register on CLK s rising edge. 4 LE Load-Enable Input. ata is loaded transparently from the internal shift register to the output latch while LE is high. ata is latched into the output latch on LE's falling edge, and retained while LE is low OUT OUT7 LE river Outputs. OUT OUT7 are open-drain, constant-current sinking outputs rated to 5.5V. 13 OE O utp ut E nab l e Inp ut. H i g h for ces outp uts OUT OUT7 to hi g h i m p ed ance, w i thout al ter i ng the contents of the outp ut l atches. Low enab l es outp uts OUT OUT7 to fol l ow the state of the outp ut l atches. 14 OUT Serial-ata Output. ata is clocked out of the 8-bit internal shift register to OUT on CLK s rising edge. 15 SET LE Current Setting. Connect SET to GN through a resistor (R SET ) to set the maximum LE current. 16 V+ Positive Supply Voltage. Bypass V+ to GN with a.1µf ceramic capacitor. PA E xp osed p ad * Exposed pad on package underside. Connect to GN. *TSSOP package only. Pin escription CLK IN SERIAL-TO-PARALLEL SHIFT REGISTER 7 OUT LE LATCHES 7 POWER-ON RESET V+ OE V+ CONSTANT-CURRENT SINKS 7 CURRENT REFERENCE FAULT ETECTION R SET GN OUT OUT1 OUT2 OUT5 OUT6 OUT7 GN Figure 1. Block iagram etailed escription The LE driver comprises a 4-wire serial interface driving eight constant-current sinking opendrain output ports. The outputs drive LEs in either static or multiplex applications (Figure 1). The constantcurrent outputs are guaranteed for current accuracy not only with chip-supply voltage variations (5V ±1% and 3V to 5.5V), but also over a realistic range of driver output voltage drop (.5V to 2.5V). The drivers use current-sensing feedback circuitry (not simple current mirrors) to ensure very small current variations over the full allowed range of output voltage (see Typical Operating Characteristics). 6

7 The 4-wire serial interface comprises an 8-bit shift register and an 8-bit transparent latch. The shift register is written through a clock input CLK and a data input IN and the data propagates to a data output OUT. The data output allows multiple drivers to be cascaded and operated together. The contents of the 8-bit shift register are loaded into the transparent latch through a latch-enable input LE. The latch is transparent to the shift register outputs when high, and latches the current state on the falling edge of LE. Each driver output is an open-drain constant-current sink that should be connected to the cathode of either a single LE or a series string of multiple LEs. The LE anode can be connected to a supply voltage of up to 5.5V, independent of the supply, V+. The constant-current capability is up to 55mA per output, set for all eight outputs by an external resistor, R SET. Initial Power-Up and Operation An internal reset circuit clears the internal registers of the on power-up. All outputs OUT to OUT7, therefore, initialize high impedance, and the interface output OUT initializes low, regardless of the initial logic levels of the CLK, IN, OE, and LE inputs. 4-Wire Serial Interface The serial interface on the is a 4-wire serial interface using four inputs (IN, CLK, LE, OE) and a data output (OUT). This interface is used to write display data to the. The serial interface data word length is 8 bits, 7. The functions of the five interface pins follow. IN is the serial-data input, and must be stable when it is sampled on the rising edge of CLK (Table 1). ata is shifted in MSB first. This means that data bit 7 is clocked in first, followed by 7 more data bits finishing with the LSB. CLK is the serial clock input, which shifts data at IN into the 8-bit shift register on its rising edge. LE is the load input of the latch, which transfers data from the 8-bit shift register to its 8- bit latch when LE is a high (transparent latch), and latches the data on the LE falling edge of LE (Figure 2). The rising edge of LE loads fault data into the 8-bit shift register, replacing bits 6 and 5 with fault data. This fault data is automatically shifted out through OUT when the next display data is shifted in. The fourth input provides output enable control of the output drivers. OE is high to force outputs OUT to OUT7 high impedance, without altering the contents of the output latches, and low to enable outputs OUT to OUT7 to follow the state of the output latches. OE is independent of the operation of the serial interface. ata can be shifted into the serial interface shift register and latched regardless of the state of OE. OUT is the serial-data output, which shifts data out from the s 8-bit shift register on the rising edge of CLK. ata at IN is propagated through the shift register and appears at OUT eight clock cycles later. The includes circuitry that detects open-circuit LEs automatically. An open-circuit fault occurs when an output is programmed to sink current but less than about 5% of the programmed current flows. Table 1. 4-Wire Serial Interface Truth Table SERIAL ATA INPUT IN CLOCK INPUT SHIFT REGISTER CONTENTS CLK 1 2 n-1 n LOA INPUT LATCH CONTENTS LE 1 2 n-1 n BLANKING INPUT OUTPUT CONTENTS OE 1 2 n-1 n H H R 1 R 2 R n-2 R n-1 L L R 1 R 2 R n-2 R n-1 X R R 1 R 2 R n-1 R n X X X X X H R R 1 R 2 R n-1 R n P 1 P 2 P 3 P n-1 P n L P P 1 P 2 P n-1 P n L P P 1 P 2 P n-1 P n X X X X X H Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L = Low-logic level H = High-logic level X = on t care P = Present state R = Previous state 7

8 LE CLK IN t S 7 t H t CL 6 t CH 1 t CP t LS t LW t LF t O OUT 7 OE t OEW OUT_ t OEL 8% 2% t OEH. t f t r Figure 2. 4-Wire Serial Interface Timing iagram LE t LRF OUT_ LE t LRR OUT_ CLK t CRF OUT_ CLK t CRR OUT_ Figure 3. LE and CLK to OUT_ Timing 8

9 Open circuits are checked just after the rising edge of LE, when new LE data is loaded into the output latches from the shift register(s). If one or more output port is detected with an open-circuit fault, then the 2 bits, 6 and 5, in the serial interface shift register are both set high. If no open-circuit faults are detected, then 6 and 5 are both cleared low. The data in other 6-bit positions in the serial interface shift register is not altered. Fault status is automatically shifted out on OUT when the next data transmission is shifted in. LE is normally taken high after all 8 bits of new LE data have been clocked into the shift register, and so at that time, OUT is outputting data bit 7. On the next two rising edges of CLK, the 2 fault status bits, 6 and 5, are clocked out in that order, followed by the remaining 5 unchanged data bits 4 to. A typical fault-detecting application tests all the shiftedout data. Bits 4 and 7 are checked against the originally transmitted data to check data link integrity. Bits 5 and 6 are checked first to see that they contain the same data (validating the status), and second whether faults are reported by the actual logic level. The fault status bit identifies which driver chip has at least one open-circuit LE. It is possible to determine how many LEs driven by a chip are at fault by running eight test patterns, each of which lights a different single LE. The fault status bit then effectively identifies only one output at a time. Applications Information Selecting External Component R SET to Set LE Output Current The uses an external resistor R SET to set the LE current for outputs OUT OUT7. The minimum allowed value of R SET is 37.6Ω, which sets the output currents to 55mA. The maximum allowed value of R SET is 1.5kΩ. The reference value, 36Ω, sets the output currents to 5mA. To set a different output current, use the formula: R SET = 18 / I OUT where I OUT is the desired output current in ma. Computing Power issipation The upper limit for power dissipation (P ) for the is determined from the following equation: P = (V+ x I+) + (V OUT x UTY x I OUT x N) where: V+ = supply voltage I+ = operating supply current when sinking I OUT LE drive current into N outputs UTY = PWM duty cycle applied to OE N = number of outputs driving LEs at the same time (maximum is 8) V OUT = port output voltage when driving load LE(s) I OUT = LE drive current programmed by R SET P = power dissipation, in mw if currents are in ma issipation example: I OUT = 47mA, N = 8, UTY = 1, V OUT = 2V, V+ = 5.25V P = (5.25V x 25mA) + (2V x 1 x 47mA x 8) =.883W Thus, for a 16-pin TSSOP package (T JA = 1 /.213 = C/W from Absolute Maximum Ratings), the maximum allowed ambient temperature T A is given by: T J(MAX) = T A + (P x T JA ) = +15 C = T A + (.883 x C/W) so T A = C. Overtemperature Cutoff The contains an internal temperature sensor that turns off all outputs when the die temperature exceeds approximately +165 C. The outputs are enabled again when the die temperature drops below approximately +14 C. Register contents are not affected, so when a driver is overdissipating, the external symptom will be the load LEs cycling between on and off as the driver repeatedly overheats and cools, alternately turning the LEs off and then back on again. Power-Supply Considerations The operates with a chip supply V+, and one or more LE supplies. Bypass each supply to GN with a.1µf capacitor as close to the as possible. This is normally adequate for static LE driving. For multiplex or PWM applications, it is necessary to add an additional bulk electrolytic capacitor of 4.7µF or more to each supply for every 4 to 16 s. The necessary capacitance depends on the LE load current, PWM switching frequency, and serial interface speed. Inadequate V+ decoupling may cause timing problems, and very noisy LE supplies can affect LE current regulation. For the TSSOP version, connect the underside exposed pad to GN. Chip Information TRANSISTOR COUNT: 2382 PROCESS: BiCMOS 9

10 PART MAX6968 NO. OF OUTPUTS MAX OUTPUT VOLTAGE (V) MAX OUTPUT CURRENT LE FAULT ETECTION Selector Guide WATCHOG MAX6978 MAX697 MAX MAX698 55mA MAX6969 MAX MAX6979 MAX6971 MAX MAX6983 Typical Application Circuit 5V +5V µc SCLK MOSI MISO LOA ENABLE 36Ω V+ CLK IN OUT LATCH OE SET OUT OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 GN V V 1

11 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to XX XX TSSOP 4.4mm BOY.EPS PACKAGE OUTLINE, TSSOP, 4.4 MM BOY, EXPOSE PA E

12 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to PIPN.EPS 12

13 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to E H IM A A1 B C E e H L INCHES MILLIMETERS MIN MAX MIN MAX SEE VARIATIONS BSC.65 BSC INCHES MIN MAX MILLIMETERS MIN MAX N 14L 16L 2L 24L 28L SSOP.EPS N A e B A1 L C NOTES: 1. &E O NOT INCLUE MOL FLASH. 2. MOL FLASH OR PROTRUSIONS NOT TO EXCEE.15 MM (.6"). 3. CONTROLLING IMENSION: MILLIMETERS. 4. MEETS JEEC MO LEAS TO BE COPLANAR WITHIN.1 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL OCUMENT CONTROL NO. REV C 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel rive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.