3V RS-232 Serial Transceiver with Logic Selector and15kv ESD Protection C 1 C 2 T 1 IN 7 T 2 IN 8 T 3 IN 9

Transcription

1 SP303E 3V RS-3 Serial ransceiver with Logic Selector and15kv ESD Protection FEAURES 3 Driver/ Receiver Architecture Logic selector function ( ) sets L input/output levels for mixed logic systems Meets true EIA/IA-3-F Standards from a 3.0V to 5.5V power supply Interoperable with EIA/IA-3 and adheres to EIA/IA-56 down to a.7v power source Minimum 50Kbps data rate under load Regulated Charge Pump Yields Stable RS-3 Outputs Regardless of V CC Variations Enhanced ESD Specifications: 15KV Human Body Model 15KV IEC Air Discharge 8KV IEC Contact Discharge Applications Palmtops Cell phone Data Cables PDA's C1 V Now Available in Lead Free Packaging DESCRIPION he SP303E provides a RS-3 transceiver solution for portable and hand-held applications such as palmtops, PDA's and cell phones. he SP303E uses an internal highefficiency, charge-pump that requires only capacitors during 3.3V operation. his charge pump and Sipex's driver architecture allow the SP303E to deliver compliant RS-3 performance from a single power supply ranging from 3.0V to 5.5V. he SP303E is a 3-driver/-receiver device, with a unique pin to program the L input and output logic levels to allow interoperation in mixed-logic voltage systems such as PDA's and cell phones. Receiver outputs will not exceed for V OH and transmitter input logic levels are scaled by the magnitude of the input. C 1 - C C - V- 5 6 SP303E SHUDOWN VCC GND 1 OU OU 3 OU 1 IN 7 14 R 1 IN IN 8 13 R IN 3 IN 9 1 R OU R 1 OU 1

2 ABSOLUE MAXIMUM RAINGS hese are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. V CC V to 6.0V V (NOE 1) V to 7.0V V - (NOE 1)...0.3V to -7.0V V V - (NOE 1)...13V I CC (DC V CC or current)...100ma Input Voltages xin, SHUDOWN = GND V to 6.0V RxIN...5V Output Voltages xou...13.v RxOU V to ( 0.3V) Short-Circuit Duration xou...continuous Storage emperature C to 150 C Power Dissipation per Packages 0-Pin SSOP (derate 7.0mW/ C above70 C)...560mW NOE 1: V and V - can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. ELECRICAL CHARACERISICS (V CC = = 3V to 5.5V, C1-C4 =, tested at 3.3V 10%, C1 = 0.047µF, C-C4 = 0.33µF, tested at 5.0V 10%, A = MIN to MAX, unless otherwise noted. ypical values are at V CC = 3.3V, A = 5 C.) P ARAMEER M IN. YP. MAX. DC CHARACERISICS o ( V = 3.3V or 5V, = 5 C) CC A UNIS CONDIIONS Supply Current ma Shutdown = V, CC no load Shutdown Supply Current 1 10 µa Shutdown = GND LOGIC INPUS Input Logic hreshold Low 0.8 = 3.3V or 5.0V V xin, Shutdown 0.6 =.5V.4 = 5.0V Input Logic hreshold High.0 V xin, Shutdown = 3.3V 1.4 =.5V ransmitter Input Hystersis 0. 5 V 0.9 = 1.8V Input Leakage Current ± 0.01 ± 1 µa xin, Shutdown RECEIVER OUPUS Output Leakage Currents ± 0.05 ± 10 µa RxOU, receivers disabled Output Voltage Low 0. 4 V I = 1.6mA OU Output Voltage High V IOU = -1mA

3 ELECRICAL CHARACERISICS (V CC = = 3V to 5.5V, C1-C4 =, tested at 3.3V 10%, C1 = 0.047µF, C-C4 = 0.33µF, tested at 5.0V 10%, A = MIN to MAX, unless otherwise noted. ypical values are at V CC = 3.3V, A = 5 C.) P ARAMEER M IN. YP. MAX. RECEIVER INPUS UNIS CONDIIONS Input Voltage Range -5 5 V Input hreshold Low Input hreshold High = 5.0V V A = 5 O C =.5V or 3.3V = 5.0V V A = 5 O C =.5V or 3.3V Input Hysteresis 0. 5 V Input Resistance kω A = 5 O C RANSMIER OUPUS Output Voltage Swing ± 5 ± 5. 4 V All transmitter outputs loaded with 3kΩ to GND. A = 5 O C Output Resistance M Ω V CC Output Short-Circuit Current ± 60 ma V = xou = V = V- = 0, transmitter output = ±V 0 Output Leakage Current ± 5 µa V = ±1, transmitter disabled xou = 0 or 3.0V to 5.5V ESD PROECION ; V CC R X IN, OU X ESD Protection ±15 Human Body Model ± 15 kv IEC Air Gap Discharge ± 8 IEC Contact Discharge 3

4 ELECRICAL CHARACERISICS (V CC = = 3V to 5.5V, C1-C4 =, tested at 3.3V 10%, C1 = 0.047µF, C-C4 = 0.33µF, tested at 5.0V 10%, A = MIN to MAX, unless otherwise noted. ypical values are at V CC = 3.3V, A = 5 C.) P ARAMEER M IN. YP. MAX. UNIS CONDIIONS Maximum Data Rate 50 kbps R L = 3kΩ, C L = 1000pF, one transmitter switching Receiver Propagation Delay 0.15 PHL t t 0.15 PLH µs Receiver input to receiver output = 150pF C L Receiver Output Enable ime 00 ns Receiver Output Disable ime 00 ns normal operation normal operation ime to Exit Shutdown 100 µs IV I xou > 3.7V ransmitter Skew ItPHL Receiver Skew ItPHL ransition-region Slew Rate -t I 100 n s (Note ) PLH -t I 50 ns PLH 6 30 V / µs C L = 150pF to 1000pF 4 30 C L = 150pF to 500pF V CC = 3.3V A = 5 o C R L = 3kΩ t o 7kΩ, measured from 3V to -3V or -3V to 3V Note. ransmitter skew is measured at the transmitter zero crosspoint. 4

5 NAME FUNCION PIN NUMBE UMBER SP303E C 1 Positive terminal of the symmetrical charge-pump capacitor, C1. 1 V Regulated 5.5V output generated by the charge pump. C 1- Negative terminal of the symmetrical charge-pump capacitor, C1. 3 C Positive terminal of the symmetrical charge-pump capacitor, C. 4 C - Negative terminal of the symmetrical charge-pump capacitor, C. 5 V - Regulated -5.5V output generated by the charge pump. 6 R 1 I N RS-3 receiver input. 14 R I N RS-3 receiver input. 13 R 1 R O U L/CMOS receiver output. 11 O U L/CMOS receiver output I N L/CMOS driver input. 7 I N L/CMOS driver input. 8 3 I N L/CMOS driver input O U RS-3 driver output. 17 O U RS-3 driver output. 16 O U RS-3 driver output. 15 G ND Ground. 18 V C C 3.0V to 5.5V supply voltage. 19 S HUDOWN Apply logic LOW to shut down drivers and charge pump. 0 Logic-Level Supply Voltage Selection 1 5

6 C1 1 0 SHUDOWN V C 1 - C C - V SP303E 15 VCC GND 1 OU OU 3 OU 1 IN 7 14 R 1 IN IN 8 13 R IN 3 IN R OU R 1 OU Figure 7. SP303E Pinout Configuration 6

7 3V to 5.5V C5 C Shutdown VCC VL C1 V C1- C3 C 4 5 C C- SP303E V- 6 C4 7 1 IN 1 OU 17 L/CMOS INPUS 8 IN OU 16 RS-3 OUPUS 9 3 IN 3 OU 15 L/CMOS OUPUS 11 R 1 OU R 1 IN 14 5KΩ 10 R OU R IN 13 5KΩ RS-3 INPUS GND 18 Figure 8. SP303E ypical Operating Circuit 7

8 DESCRIPION he SP303E is a 3-driver/-receiver device that can be operated as a full duplex, RS-3 serial transceiver with the 3rd driver acting as a control line allowing a Ring Indicator (RI) signal to alert the UAR on the PC. his transceiver meet the EIA/IA-3 and IU- V.8/V.4 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers, PDA's and cell phones. he SP303E devices feature Sipex's proprietary and patented (U.S.#5,306,954) on-board charge pump circuitry that generates ±5.5V RS-3 voltage levels from a single 3.0V to 5.5V power supply. he SP303E devices can operate at a minimum data range of 50kbps, driving a single driver. he SP303E is a 3-driver/-receiver device. HEORY OF OPERAION he SP303E contains four basic circuit blocks: 1. drivers,. receivers, 3. a Sipex proprietary charge pump and 4. circuitry. Drivers he drivers are inverting level transmitters that convert L or CMOS logic levels to 5.0V EIA/ IA-3 levels with an inverted sense relative to the input logic levels. ypically, the RS-3 output voltage swing is 5.4V with no load and 5V minimum fully loaded. he driver outputs are protected against infinite short-circuits to ground without degradation in reliability. hese drivers comply with the EIA-IA-3F and all previous RS-3 versions. he driver output stages are turned off (High Impedance) when the device is in shutdown mode. he drivers typically can operate at a data rate of 50Kbps. he drivers can guarantee a data rate of 10Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. he slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-3D.1.7, Paragraph 5). he transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. he SP303E driver can maintain high data rates up to 50Kbps with a single driver loaded. Figure 9 shows a loopback test circuit used to test the RS-3 Drivers. Figure 10 shows the test results of the loopback circuit with all three drivers active at 10Kbps with typical RS-3 loads in parallel with 1000pF capacitors. Figure 11 shows the test results where one driver was active at 50Kbps and all three drivers loaded with an RS-3 receiver in parallel with a 1000pF capacitor. he transmitter inputs do not have pull-up resistors. Connect unused inputs to ground or Receivers he receivers convert ±5.0V EIA/IA-3 levels to L or CMOS logic output levels. Receivers are disabled when in shutdown. he truth table logic of the SP303E driver and receiver outputs can be found in able 1. Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. his ensures that the receiver is immune to noisy transmission lines. Should an input be left unconnected, an internal 5KΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state. Charge Pump he charge pump is a Sipex patented design (U.S. #5,306,954) and uses a unique approach compared to older less efficient designs. he charge pump still requires four external capacitors, but uses a four phase voltage shifting technique to attain symmetrical 5.5V power supplies. he internal power supply 8

9 DEVICE: SP303E 3V to 5V SHUDOWN X OU R X OU 0 High-Z 1 Active High-Z Active Charge Pump Inactive Active C5 C1 C 1 C1 3 C1-4 C 5 C- 19 VCC SP303E V V- 6 C3 C4 able 1. SHUDOWN ruth able. (Note: When device in shutdown, the SP303E's charge pump is turned off and V decays to V CC. V- is pulled to ground and the transmitter outputs are disabled as High Impendance). L/CMOS INPUS 1 IN X IN 1 OU X OU consists of a regulated dual charge pump that provides output voltages of 5.5V regardless of the input voltage (V CC ) over the 3.0V to 5.5V range. his is important to maintain compliant RS-3 levels regardless of power supply fluctuations. L/CMOS OUPUS VCC R 1 OU R 1 IN 5KΩ R X OU R X IN 5KΩ 0 SHUDOWN GND pF 1 3V to 5.5V 1000pF he charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a of 5.5V, the charge pump is enabled. If the output voltages exceed a of 5.5V, the charge pump is disabled. his oscillator controls the four phases of the voltage shifting (Figure 1). A description of each phase follows. V SS Charge Storage-Phase 1(Figure 13) During this phase of the clock cycle, the positive side of capacitors C 1 and C are initially charged to V CC. C l is then switched to GND and the charge in C 1 is transferred to C. Since C is connected to V CC, the voltage potential across capacitor C is now times V CC. Figure 9. Loopback est Circuit for RS-3 Driver Data ransmission Rates V SS ransfer-phase (Figure 14) Phase two of the clock connects the negative terminal of C to the V SS storage capacitor and the positive terminal of C to GND. his transfers a negative generated voltage to C 3. his generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C 3, the positive side of capacitor C 1 is switched to V CC and the negative side is connected to GND. V DD Charge Storage-Phase 3 (Figure 15) he third phase of the clock is identical to the first phase the charge transferred in C 1 pro- [ ] [ ] 1 IN 1 1 IN 1 1 OU R1 OU 3 1 OU R1 OU 3 Ch1 5.00V Ch 5.00V M 5.00µs Ch1 0V Ch3 5.00V Ch1 5.00V Ch 5.00V M.50µs Ch1 0V Ch3 5.00V Figure 10. Loopback est Circuit Result at 10Kbps (All Drivers Fully Loaded) Figure 11. Loopback est Circuit result at 50Kbps (All Drivers Fully Loaded) 9

10 duces V CC in the negative terminal of C 1, which is applied to the negative side of capacitor C. Since C is at V CC, the voltage potential across C is times V CC. V DD ransfer-phase 4 (Figure 16) he fourth phase of the clock connects the negative terminal of C to GND, and transfers this positive generated voltage across C to C 4, the V DD storage capacitor. his voltage is regulated to 5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C 4, positive side of capacitor C 1 is switched to V CC and the negative side is connected to GND, allowing the charge pump cycle to begin again. he charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V and V are separately generated from V CC, in a no load condition, V and V will be symmetrical. Older charge pump approaches that generate V from V will show a decrease in the magnitude of V compared to V due to the inherent ineffiencies in the design. he clock rate for the charge pump is typically operates at 50kHz. he external capacitors are usually with a 16V breakdown voltage rating. Supply Level Current RS-3 serial tranceivers are designed with fixed 5V or 3.3V L input/output voltages levels. he function in the SP303E allows the end user to set the L input/output voltage levels independent of V CC. By connecting to the main logic bus of system, the L input/ output limits and threshold are reset to interface with the on board low voltage logic circuity. Capacitor Selection able: V C C V) ( C 1 ( µ F ) C -C4( µ F) 3.0 to to to

11 [ ] 6V a) C 1 0V 0V b) C- Ch1.00V Ch.00V M 1.00µs Ch1 1.96V Figure 1. Charge Pump Waveforms -6V Figure 13. Charge Pump Phase 4 - V SS Charge Storage Figure 14. Charge Pump Phase 3 - V SS Charge ransfer Figure 15. Charge Pump Phase - V DD Charge Storage Figure 16. Charge Pump Phase 1 - V DD Charge ransfer 11

12 C5 C1 C 0 Shutdown 1 C1 3 C1-4 C 5 C- 7 1 IN 19 VCC SP303E VL 1 V V- 1 OU 6 17 C3 C4 8 IN OU IN 3 OU R 1 OU R 1 IN R OU R IN 13 DB-9 Connector GND DB-9 Connector Pins: 1. Received Line Signal Detector. Received Data 3. ransmitted Data 4. Data erminal Ready 5. Signal Ground (Common) 6. DCE Ready 7. Request to Send 8. Clear to Send 9. Ring Indicator Figure 17. Circuit for the connectivity of the SP303E with a DB-9 connector 1

13 ESD OLERANCE he SP303E incorporates ruggedized ESD cells on all driver output and receiver input pins. he improved ESD tolerance is at least 15kV without damage nor latch-up. here are different methods of ESD testing applied: a) MIL-SD-883, Method b) IEC Air-Discharge c) IEC Direct Contact he Human Body Model has been the generally accepted ESD testing method for semiconductors. his method is also specified in MIL-SD-883, Method for ESD testing. he premise of this ESD test is to simulate the human body s potential to store electro-static energy and discharge it to an integrated circuit. he simulation is performed by using a test model as shown in Figure 18. his method will test the IC s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. he IEC , formerly IEC801-, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. he premise with IEC is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. he transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. he test circuit for IEC is shown on Figure 19. here are two methods within IEC , the Air Discharge method and the Contact Discharge method. With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EU) through air. his simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. he high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. his energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. he Contact Discharge Method applies the ESD current directly to the EU. his method was devised to reduce the unpredictability of the ESD arc. he discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. he current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC. he circuit model in Figures 18 and 19 represent the typical ESD testing circuit used for all three methods. he C S is initially charged with the DC R C R S SW1 SW DC Power Source C S Device Under est Figure 18. ESD est Circuit for Human Body Model 13

14 R C R S Contact-Discharge Module R V SW1 SW DC Power Source C S Device Under est R S and R V add up to 330Ω for IEC Figure 19. ESD est Circuit for IEC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW) is on while SW1 switches off. he voltage stored in the capacitor is then applied through R S, the current limiting resistor, onto the device under test (DU). In ESD tests, the SW switch is pulsed so that the device under test receives a duration of voltage. For the Human Body Model, the current limiting resistor (R S ) and the source capacitor (C S ) are 1.5kW an 100pF, respectively. For IEC , the current limiting resistor (R S ) and the source capacitor (C S ) are 330W an 150pF, respectively. he higher C S value and lower R S value in the IEC model are more stringent than the Human Body Model. he larger storage capacitor injects a higher voltage to the test point when SW is switched on. he lower current limiting resistor increases the current charge onto the test point. i 30A 15A 0A t=0ns t=30ns t Figure 0. ESD est Waveform for IEC DEVICE PIN HUMAN BODY IEC ESED MODEL Air Discharge Direct Contact Level Driver Outputs ±15kV ±15kV ±8kV 4 Receiver Inputs ±15kV ±15kV ±8kV 4 able. ransceiver ESD olerance Levels 14

15 PACKAGE: 0 Pin SSOP e 0.16 BSC (3. BSC) 0.5 BSC (6.4 BSC) DIMENSIONS in inches (mm) Minimum/Maximum 1.0 OIA (4.30) (4.50) Symbol 0 Lead D 0.5/0.60 (6.40/6.60) (1.0) e 0.06 BSC (0.65 BSC) REF e/ (1.0) D (1.10) Max (0.85) (0.95) (0.19) 0.01 (0.30) 0.00 (0.05) (0.15) (θ) (0.0) (0.09) Min (0.09) Min Gage Plane (0.5) (θ3) 0.00 (0.50) 0.06 (0.75) (θ1) 1.0 REF 15

16 ORDERING INFORMAION Model emperature Range Package ypes SP303ECY 0 C to 70 C 0-pin SSOP SP303ECY/R 0 C to 70 C 0-pin SSOP SP303EEY -40 C to 85 C 0-pin SSOP SP303EEY/R -40 C to 85 C 0-pin SSOP Available in lead free packaging. o order add "-L" suffix to part number. Example: SP303EEY/R = standard; SP303EEY-L/R = lead free R = ape and Reel Pack quantity is 1500 for SSOP. CLICK HERE O ORDER SAMPLES Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 33 South Hillview Drive Milpitas, CA EL: (408) FAX: (408) Sales Office Linnell Circle Billerica, MA 0181 EL: (978) FAX: (978) sales@sipex.com Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. 16