SP3222E/3232E. True +3.0V to +5.5V RS-232 Transceivers

Transcription

1 SP3E/33E True 3.0V to 5.5V RS-3 Transceivers FEATURES Meets true EIA/TIA-3-F Standards from a 3.0V to 5.5V power supply Minimum 10Kbps Data Rate Under Full oad 1µA ow-power Shutdown with Receivers Active (SP3E) Interoperable with RS-3 down to.7v power source Enhanced ESD Specifications: ±15kV Human Body Model ±15kV IEC Air Discharge ±8kV IEC Contact Discharge EN 1 18 SHDN C1 V C GND T1OUT C 5 SP3E 14 R1IN C R1OUT V- 7 1 T1IN TOUT 8 11 TIN RIN 9 10 ROUT DIP/SO Now Available in ead Free Packaging Note: See page 6 for other pinouts DESCRIPTION The SP3E/33E series is an RS-3 transceiver solution intended for portable or handheld applications such as notebook or palmtop computers. The SP3E/33E series has a high-efficiency, charge-pump power supply that requires only capacitors in 3.3V operation. This charge pump allows the SP3E/33E series to deliver true RS-3 performance from a single power supply ranging from 3.3V to 5.0V. The SP3E/33E are -driver/-receiver devices. This series is ideal for portable or hand-held applications such as notebook or palmtop computers. The ESD tolerance of the SP3E/33E devices are over ±15kV for both Human Body Model and IEC Air discharge test methods. The SP3E device has a low-power shutdown mode where the devices' driver outputs and charge pumps are disabled. During shutdown, the supply current falls to less than 1µA. SEECTION TABE MODE Power Supplies RS-3 Driver rivers RS-3 Receiver eceivers External Component omponents Shutdown TT 3-Stat -State No. of Pin ins SP3 SP33 3.0V to 5.5V 4 Yes 3.0V to 5.5V 4 No Yes 18, 0 No Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 1

2 ABSOUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. V CC V to 6.0V V (NOTE 1) V to 7.0V V- (NOTE 1)...0.3V to -7.0V V V- (NOTE 1)...13V I CC (DC V CC or GND current)...±100ma Input Voltages TxIN, EN, SHDN V to 0.3V RxIN... ±15V Output Voltages TxOUT... ±13.V RxOUT V to (V CC 0.3V) Short-Circuit Duration TxOUT... Continuous Storage Temperature C to 150 C Power Dissipation Per Package 0-pin SSOP (derate 9.5mW/ o C above 70 o C) mW 18-pin PDIP (derate 15.mW/ o C above 70 o C)... 10mW 18-pin SOIC (derate 15.7mW/ o C above 70 o C)... 0mW 0-pin TSSOP (derate 11.1mW/ o C above 70 o C).. 890mW -pin SSOP (derate 9.69mW/ o C above 70 o C) mW -pin PDIP (derate 14.3mW/ o C above 70 o C) mW -pin Wide SOIC (derate 11.mW/ o C above 70 o C) 900mW -pin TSSOP (derate 10.5mW/ o C above 70 o C).. 850mW -pin nsoic (derate 13.57mW/ C above 70 C) mW NOTE 1: V and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. EECTRICA CHARACTERISTICS Unless otherwise noted, the following specifications apply for V CC = 3.0V to 5.0V with T AMB = T MIN to T MAX P ARAMETER M IN. T YP. MAX. DC CHARACTERISTICS UNITS CONDITIONS Supply Current ma no load, T 5 AMB o = C, V Shutdown Supply Current µa o SHDN = GND, T AMB = 5 C, V OGIC INPUTS AND RECEIVER OUTPUTS Input ogic Threshold OW 0. 8 V TxIN, EN, SHDN, Note Input ogic Threshold HIGH. 0.4 V V CC = 3.3V, Note V CC = 5.0V, Note Input eakage Current ± 0.01 ± 1. 0 µa TxIN, EN, SHDN, T AMB = 5 o C Output eakage Current ± 0.05 ± 10 µa receivers disabled Output Voltage OW 0. 4 V I = 1.6mA OUT Output Voltage HIGH DRIVER OUTPUTS V CC V CC V IOUT = -1.0mA Output Voltage Swing ± 5. 0 ± 5. 4 V 3kΩ load to ground at all driver outputs, T = o C AMB 5 Output Resistance 300 Ω V CC = V = V- = GND, TO UT O utput Short-Circuit Current ma V OUT = Zero Volts Output eakage Current ± 5 µa V O UT = V, V disabled 1 CC = CC = 3.3V CC = V = GND to 5.5V,drivers 3.3V Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation

3 EECTRICA CHARACTERISTICS Unless otherwise noted, the following specifications apply for V CC = 3.0V to 5.0V with T AMB = T MIN to T MAX. Typical Values apply at V CC = 3.3V or 5.0V and T AMB = 5 o C. P ARAMETER M IN. T YP. MAX. RECEIVER INPUTS UNITS CONDITIONS Input Voltage Range V Input Threshold OW V V CC V CC =3.3V =5.0V Input Threshold HIGH V V CC V CC =3.3V =5.0V Input Hysteresis 0. 3 V Input Resistance kω TIMING CHARACTERISTICS Maximum Data Rate kbps R = 3kΩ, C =1000pF, one driver switching Driver Propagation Delay µs µs t PH tph, R = 3KΩ, C = 1000pF, R = 3KΩ, C = 1000pF Receiver Propagation Delay µs t, RxIN to RxOUT, C =150pF PH, RxIN to RxOUT, C =150pF tph Receiver Output Enable Time 00 ns Receiver Output Disable Time 00 ns Driver Skew ns Receiver Skew ns Transition-Region Slew Rate 30 V / µs tph tph V CC - t, T PH - t H P 5 AMB = o C o = 3.3V, R = 3KΩ, T = 5 C, AMB measurements taken from -3.0V to 3.0V or 3.0V to -3.0V NOTE : Driver input hysteresis is typically 50mV. Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 3

4 TYPICA PERFORMANCE CHARACTERISTICS Unless otherwise noted, the following performance characteristics apply for V CC = 3.3V, 10kbps data rates, all drivers loaded with 3kΩ, charge pump capacitors, and T AMB = 5 C Transmitter Output Voltage [V] Vout Vout- Slew Rate [V/µs] Slew -Slew -6 oad Capacitance [pf] oad Capacitance [pf] Figure 1. Transmitter Output Voltage VS. oad Capacitance for the SP3 and the SP33 Figure. Slew Rate VS. oad Capacitance for the SP3 and the SP KHz 60KHz 10KHz 35 Supply Current [ma] oad Capacitance [pf] Figure 3. Supply Current VS. oad Capacitance when Transmitting Data for the SP3 and the SP33 Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 4

5 PIN NUMBER NAME FUNCTION SP3E SSOP/- DIP/SO TSSO SSOP SP33E EN Receiver Enable. Apply logic OW for normal operation. Apply logic HIGH to disable the receiver outputs (high-z state) C 1 Positive terminal of the voltage doubler charge-pump capacitor. 1 V 5.5V generated by the charge pump. 3 3 C 1- Negative terminal of the voltage doubler charge-pump capacitor C Positive terminal of the inverting charge-pump capacitor C - Negative terminal of the inverting charge-pump capacitor V V generated by the charge pump T 1OUT RS-3 driver output T OUT RS-3 driver output R 1IN RS-3 receiver input R IN RS-3 receiver input R 1OUT TT/CMOS reciever output R OUT TT/CMOS reciever output T 1IN TT/CMOS driver input T IN TT/CMOS driver input G ND Ground V CC 3.0V to 5.5V supply voltage SHDN Shutdown Control Input. Drive HIGH for normal device operation. Drive OW to shutdown the drivers (high-z output) and the on- board power supply N.C. No Connect. - 11, 14 - Table 1. Device Pin Description Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 5

6 EN 1 0 SHDN EN 1 18 SHDN C1 19 C1 17 V 3 18 GND V 3 GND C1- C SP3E T1OUT R1IN C1- C SP3E 14 T1OUT R1IN C R1OUT C R1OUT V N.C. V- 7 1 T1IN TOUT RIN T1IN TIN TOUT RIN TIN ROUT ROUT N.C. DIP/SO SSOP/TSSOP Figure 4. Pinout Configurations for the SP3E C1 V C1- C C- V- TOUT RIN SP33E GND T1OUT R1IN R1OUT T1IN TIN ROUT Figure 5. Pinout Configuration for the SP33E Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 6

7 C5 C1 C 19 SP3E SSOP TSSOP V V- 3 7 *C3 C4 C5 C1 C C1 4 C1-5 C 6 C- C1 4 C1-5 C 6 C- 17 SP3E DIP/SO V V- 3 7 *C3 C4 OGIC INPUTS 13 T1IN 1 TIN T1OUT TOUT 17 8 RS-3 OUTPUTS OGIC INPUTS 1 T1IN 11 TIN T1OUT TOUT 15 8 RS-3 OUTPUTS OGIC OUTPUTS 15 R1OUT 10 ROUT 1 GND 18 5kΩ 5kΩ R1IN RIN EN 0 SHDN 9 RS-3 INPUTS *can be returned to either or GND OGIC OUTPUTS 13 R1OUT 10 ROUT 1 GND 5kΩ 5kΩ R1IN RIN 14 EN 18 SHDN 9 RS-3 INPUTS *can be returned to either or GND Figure 6. SP3E Typical Operating Circuits C5 C C1 1 C1 3 C1-4 C 5 C- SP33E V V- 6 *C3 C4 OGIC INPUTS 11 T1IN 10 TIN T1OUT TOUT 14 7 RS-3 OUTPUTS OGIC OUTPUTS 1 R1OUT R1IN 13 5kΩ 9 ROUT RIN 8 5kΩ RS-3 INPUTS Figure 7. SP33E Typical Operating Circuit GND 15 *can be returned to either or GND Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 7

8 DESCRIPTION The SP3E/33E transceivers meet the EIA/ TIA-3 and V.8/V.4 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3E/ 33E devices all feature Sipex's proprietary on-board charge pump circuitry that generates x V CC for RS-3 voltage levels from a single 3.0V to 5.5V power supply. This series is ideal for 3.3V-only systems, mixed 3.3V to 5.5V systems, or 5.0V-only systems that require true RS-3 performance. The SP3E/ 33E series have drivers that operate at a typical data rate of 35Kbps fully loaded. The SP3E and SP33E are -driver/-receiver devices ideal for portable or hand-held applications. The SP3E features a 1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1µA supply current. THEORY OF OPERATION The SP3E/33E series are made up of three basic circuit blocks: 1. Drivers,. Receivers, and 3. the Sipex proprietary charge pump. Drivers The drivers are inverting level transmitters that convert TT or CMOS logic levels to ±5.0V EIA/TIA-3 levels inverted relative to the input logic levels. Typically, the RS-3 output voltage swing is ±5.5V with no load and at least ±5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Driver outputs will meet EIA/TIA-56 levels of ±3.7V with supply voltages as low as.7v. The drivers typically can operate at a data rate of 35Kbps. The drivers can guarantee a data rate of 10Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-3D.1.7, Paragraph 5). The transition of the loaded output from HIGH to OW also meets the monotonicity requirements of the standard. The SP3E/33E drivers can maintain high data rates up to 35Kbps fully loaded. Figure 8 shows a loopback test circuit used to test the RS-3 drivers. Figure 9 shows the test results of the loopback circuit with all drivers active at 10Kbps with RS-3 loads in parallel with 1000pF capacitors. Figure 10 shows the test results where one driver was active at 35Kbps and all drivers loaded with an RS-3 receiver in parallel with a 1000pF capacitor. A solid RS-3 data transmission rate of 10Kbps provides compatibility with many designs in personal computer peripherals and AN applications. The SP3E driver's output stages are turned off (tri-state) when the device is in shutdown mode. When the power is off, the SP3E device permits the outputs to be driven up to ±1V. The driver's inputs do not have pull-up resistors. Designers should connect unused inputs to V CC or GND. In the shutdown mode, the supply current falls to less than 1µA, where SHDN = OW. When the SP3E device is shut down, the device's driver outputs are disabled (tri-stated) and the charge pumps are turned off with V pulled down to V CC and V- pulled to GND. The time required to exit shutdown is typically 100µs. Connect SHDN to V CC if the shutdown mode is not used. SHDN has no effect on RxOUT or RxOUTB. As they become active, the two driver outputs go to opposite RS-3 levels where one driver input is HIGH and the other OW. Note that the drivers are enabled only when the magnitude of V- exceeds approximately 3V. Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 8

9 C5 C1 C C1 C1- C C- SP3E SP33E V V- C3 C4 OGIC INPUTS TxIN TxOUT OGIC OUTPUTS RxOUT 5kΩ RxIN EN *SHDN GND 1000pF Figure 8. SP3E/33E Driver oopback Test Circuit * SP3 only [ T ] [ T ] T1 IN 1 T T1 IN 1 T T1 OUT T1 OUT T T T T R1 OUT 3 R1 OUT 3 Ch1 Ch3 5.00V Ch 5.00V M 5.00µs Ch1 0V 5.00V Ch1 Ch3 5.00V Ch 5.00V M.50µs Ch1 0V 5.00V Figure 9. Driver oopback Test Results at 10kbps Figure 10. Driver oopback Test Results at 35kbps Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 9

10 Receivers The receivers convert EIA/TIA-3 levels to TT or CMOS logic output levels. All receivers have an inverting tri-state output. These receiver outputs (RxOUT) are tri-stated when the enable control EN = HIGH. In the shutdown mode, the receivers can be active or inactive. EN has no effect on TxOUT. The truth table logic of the SP3E/33E driver and receiver outputs can be found in Table. Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, a 5kΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state. Charge Pump The charge pump is a Sipexpatented design (#5,306,954) and uses a unique approach compared to older, lessefficient designs. The charge pump still requires four external capacitors, but uses a fourphase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages of 5.5V regardless of the input voltage (V CC ) over the 3.0V to 5.5V range. SHDN EN TxOUT 0 0 Tri-state 0 1 Tri-state 1 0 Active 1 1 Active RxOUT Active Tri-state Active Tri-state Table. Truth Table ogic for Shutdown and Enable Control In most circumstances, decoupling the power supply can be achieved adequately using a bypass capacitor at C5 (refer to Figures 6 and 7). In applications that are sensitive to power-supply noise, decouple V CC to ground with a capacitor of the same value as charge-pump capacitor C1. Physically connect bypass capacitors as close to the IC as possible. The charge pumps operate in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pumps are enabled. If the output voltage exceed a magnitude of 5.5V, the charge pumps are disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows. Phase 1 V SS charge storage During this phase of the clock cycle, the positive side of capacitors C 1 and C are initially charged to V CC. C l is then switched to GND and the charge in C 1 is transferred to C. Since C is connected to V CC, the voltage potential across capacitor C is now times V CC. Phase V SS transfer Phase two of the clock connects the negative terminal of C to the V SS storage capacitor and the positive terminal of C to GND. This transfers a negative generated voltage to C 3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C 3, the positive side of capacitor C 1 is switched to V CC and the negative side is connected to GND. Phase 3 V DD charge storage The third phase of the clock is identical to the first phase: The charge transferred in C 1 produces V CC in the negative terminal of C 1, which is applied to the negative side of capacitor C. Since C is at V CC, the voltage potential across C is times V CC. Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 10

11 Phase 4 V DD transfer The fourth phase of the clock connects the negative terminal of C to GND, and transfers this positive generated voltage across C to C 4, the V DD storage capacitor. This voltage is regulated to 5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C 4, the positive side of capacitor C 1 is switched to V CC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V and V are separately generated from V CC, in a noload condition V and V will be symmetrical. Older charge pump approaches that generate V from V will show a decrease in the magnitude of V compared to V due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 50kHz. The external capacitors can be as low as with a V breakdown voltage rating. ESD Tolerance The SP3E/33E series incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. The improved ESD tolerance is at least ±15kV without damage nor latch-up. There are different methods of ESD testing applied: a) MI-STD-883, Method b) IEC Air-Discharge c) IEC Direct Contact The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MI-STD- 883, Method for ESD testing. The premise of this ESD test is to simulate the human body s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 17. This method will test the IC s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. The IEC , formerly IEC801-, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC is shown on Figure 18. There are two methods within IEC , the Air Discharge method and the Contact Discharge method. With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 11

12 V CC = 5V 5V C 1 C 5V 5V C 4 C 3 V DD Storage Capacitor V SS Storage Capacitor Figure 1. Charge Pump Phase 1 V CC = 5V C 1 C 10V C 4 C 3 V DD Storage Capacitor V SS Storage Capacitor Figure 13. Charge Pump Phase [ T ] 6V a) C GND 1 T GND b) C- T -6V Ch1.00V Ch.00V M 1.00µs Ch1 5.48V Figure 14. Charge Pump Waveforms V CC = 5V 5V C 1 C 5V 5V C 4 C 3 V DD Storage Capacitor V SS Storage Capacitor Figure 15. Charge Pump Phase 3 V CC = 5V 10V C 1 C C 4 C 3 V DD Storage Capacitor V SS Storage Capacitor Figure. Charge Pump Phase 4 Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 1

13 R C R S SW1 SW DC Power Source C S Device Under Test Figure 17. ESD Test Circuit for Human Body Model The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC. The circuit models in Figures 17 and 18 represent the typical ESD testing circuits used for all three methods. The C S is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW) is on while SW1 switches off. The voltage stored in the capacitor is then applied through R S, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW switch is pulsed so that the device under test receives a duration of voltage. R RCC R S Contact-Discharge Module R V SW1 SW DC Power Source C S Device Under Test R S and R V add up to 330Ω for IEC Figure 18. ESD Test Circuit for IEC Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 13

14 For the Human Body Model, the current limiting resistor (R S ) and the source capacitor (C S ) are 1.5kΩ an 100pF, respectively. For IEC , the current limiting resistor (R S ) and the source capacitor (C S ) are 330Ω and 150pF, respectively. The higher C S value and lower R S value in the IEC model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW is switched on. The lower current limiting resistor increases the current charge onto the test point. I 30A 15A 0A t=0ns t=30ns t Figure 19. ESD Test Waveform for IEC Device Pin Human Body IEC Tested Model Air Discharge Direct Contact evel Driver Outputs ±15kV ±15kV ±8kV 4 Receiver Inputs ±15kV ±15kV ±8kV 4 Table 3. Transceiver ESD Tolerance evels Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 14

15 PACKAGE: PASTIC SHRINK SMA OUTINE (SSOP) E H D A Ø e B A1 DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H Ø PIN 0.068/0.078 (1.73/1.99) 0.00/0.008 (0.05/0.1) 0.010/0.015 (0.5/0.38) 0.39/0.49 (6.07/6.33) 0.05/0.1 (5.0/5.38) BSC (0.65 BSC) 0.301/0.311 (7.65/7.90) 0.0/0.037 (0.55/0.95) 0 /8 (0 /8 ) 0PIN 0.068/0.078 (1.73/1.99) 0.00/0.008 (0.05/0.1) 0.010/0.015 (0.5/0.38) 0.78/0.89 (7.07/7.33) 0.05/0.1 (5.0/5.38) BSC (0.65 BSC) 0.301/0.311 (7.65/7.90) 0.0/0.037 (0.55/0.95) 0 /8 (0 /8 ) Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 15

16 PACKAGE: PASTIC DUAININE (NARROW) E1 E D1 = 0.005" min. (0.17 min.) D A1 = 0.015" min. (0.381min.) A = 0.10" max. (5.334 max). e = BSC (.540 BSC) B1 B ATERNATE END PINS (BOTH ENDS) A Ø C e A = BSC (7.60 BSC) DIMENSIONS (Inches) Minimum/Maximum (mm) A B B1 C D E E1 Ø PIN 0.115/0.195 (.91/4.953) 0.014/0.0 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.03/0.356) 0.780/ /0.90 (19.81/0.30) (.35/3.368) 0.300/0.35 (7.60/8.55) 0.40/0.80 (6.096/7.11) 0.115/0.150 (.91/3.810) 0 / 15 (0 /15 ) 18PIN 0.115/0.195 (.91/4.953) 0.014/0.0 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.03/0.356) 0.300/0.35 (7.60/8.55) 0.40/0.80 (6.096/7.11) 0.115/0.150 (.91/3.810) 0 / 15 (0 /15 ) Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation

17 PACKAGE: PASTIC SMA OUTINE (SOIC) (WIDE) E H D A Ø e B A1 DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H Ø PIN 0.090/0.104 (.9/.649) 0.004/0.01 (0.10/0.300) 0.013/0.00 (0.330/0.508) 0.398/0.413 (10.10/10.49) 0.91/0.99 (7.40/7.600) BSC (1.70 BSC) 0.394/0.419 (10.00/10.64) 0.0/0.050 (0.406/1.70) 0 /8 (0 /8 ) 18PIN 0.090/0.104 (.9/.649)) 0.004/0.01 (0.10/0.300) 0.013/0.00 (0.330/0.508) 0.447/0.463 (11.35/11.74) 0.91/0.99 (7.40/7.600) BSC (1.70 BSC) 0.394/0.419 (10.00/10.64) 0.0/0.050 (0.406/1.70) 0 /8 (0 /8 ) Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 17

18 PACKAGE: PASTIC SMA OUTINE (SOIC) (NARROW) E H D h x 45 A Ø e B A1 DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H h Ø PIN 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.10/0.49) 0.013/0.00 (0.330/0.508) 0.386/0.394 (9.80/10.000) 0.150/0.157 (3.80/3.988) BSC (1.70 BSC) 0.8/0.44 (5.801/6.198) 0.010/0.00 (0.54/0.498) 0.0/0.050 (0.406/1.70) 0 /8 (0 /8 ) Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 18

19 DIMENSIONS in inches (mm) Minimum/Maximum Symbol ead 0 ead D 0.193/ /0.60 (4.90/5.10) (6.40/6.60) e 0.06 BSC 0.06 BSC (0.65 BSC) (0.65 BSC) PACKAGE: PASTIC THIN SMA OUTINE (TSSOP) e 0. BSC (3. BSC) 1.0 OIA 0.9 (4.30) (4.50) 0.5 BSC (6.4 BSC) (1.0) REF e/ (1.0) D (1.10) Max (0.85) (0.95) (0.19) 0.01 (0.30) 0.00 (0.05) (0.15) (θ) (0.0) (0.09) Min (0.09) Min Gage Plane (0.5) (θ3) 0.00 (0.50) 0.06 (0.75) (θ1) 1.0 REF Date: 8//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 19

20 ORDERING INFORMATION Model Temperature Range Package Type SP3ECA... 0 C to 70 C... 0-Pin SSOP SP3ECA/TR... 0 C to 70 C... 0-Pin SSOP SP3ECP... 0 C to 70 C Pin PDIP SP3ECT... 0 C to 70 C Pin WSOIC SP3ECT/TR... 0 C to 70 C Pin WSOIC SP3ECY... 0 C to 70 C... 0-Pin TSSOP SP3ECY/TR... 0 C to 70 C... 0-Pin TSSOP SP3EEA C to 85 C... 0-Pin SSOP SP3EEA/TR C to 85 C... 0-Pin SSOP SP3EEP C to 85 C Pin PDIP SP3EET C to 85 C Pin WSOIC SP3EET/TR C to 85 C Pin WSOIC SP3EEY C to 85 C... 0-Pin TSSOP SP3EEY/TR C to 85 C... 0-Pin TSSOP SP33ECA... 0 C to 70 C... -Pin SSOP SP33ECA/TR... 0 C to 70 C... -Pin SSOP SP33ECP... 0 C to 70 C... -Pin PDIP SP33ECT... 0 C to 70 C... -Pin WSOIC SP33ECT/TR... 0 C to 70 C... -Pin WSOIC SP33ECN... 0 C to 70 C... -Pin nsoic SP33ECN/TR... 0 C to 70 C... -Pin nsoic SP33ECY... 0 C to 70 C... -Pin TSSOP SP33ECY/TR... 0 C to 70 C... -Pin TSSOP SP33EEA C to 85 C... -Pin SSOP SP33EEA/TR C to 85 C... -Pin SSOP SP33EEP C to 85 C... -Pin PDIP SP33EET C to 85 C... -Pin WSOIC SP33EET/TR C to 85 C... -Pin WSOIC SP33EEN C to 85 C... -Pin nsoic SP33EEN/TR C to 85 C... -Pin nsoic SP33EEY C to 85 C... -Pin TSSOP SP33EEY/TR C to 85 C... -Pin TSSOP Available in lead free packaging. To order add - suffix to part number. Example: SP33EEN/TR = standard; SP33EEN-/TR = lead free /TR = Tape and Reel Pack quantity is 1,500 for SSOP, 0-pin TSSOP or WSOIC; and pack quantity is,500 for NSOIC or -pin TSSOP. CICK HERE TO ORDER SAMPES Corporation ANAOG EXCEENCE Sipex Corporation Headquarters and Sales Office 33 South Hillview Drive Milpitas, CA TE: (408) FAX: (408) Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Date: 08//05 SP3E, SP33E True 3.0 to 5.0V RS-3 Transceivers Copyright 005 Sipex Corporation 0