APPLICATIO S. LTC485 Low Power RS485 Interface Transceiver FEATURES DESCRIPTIO TYPICAL APPLICATIO

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Low Power S85 Interface Transceiver FETES Low Power: I CC = 3µ Typ Designed for S85 Interface pplications Single 5V supply 7V to 12V us Common Mode ange Permits ±7V Ground Difference etween Devices

1 Low Power S85 Interface Transceiver FETES Low Power: I CC = 3µ Typ Designed for S85 Interface pplications Single 5V supply 7V to 12V us Common Mode ange Permits ±7V Ground Difference etween Devices on the us Thermal Shutdown Protection Power-p/Down Glitch-Free Driver Outputs Permit Live Insertion or emoval of Transceiver Driver Maintains High Impedance in Three-State or with the Power Off Combined Impedance of a Driver Output and eceiver llows p to 32 Transceivers on the us 7mV Typical Input Hysteresis 3ns Typical Driver Propagation Delays with 5ns Skew Pin Compatible with ±6V Protected LT1785 and 52Mbps LTC1685 PPLICTIO S Low Power S85/S22 Transceiver Level Translator DESCIPTIO The LTC 85 is a low power differential bus/line transceiver designed for multipoint data transmission standard S85 applications with extended common mode range (12V to 7V). It also meets the requirements of S22. The CMOS design offers significant power savings over its bipolar counterpart without sacrificing ruggedness against overload of ESD damage. The driver and receiver feature three-state outputs, with the driver outputs maintaining high impedance over the entire common mode range. Excessive power dissipation caused by bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state. The receiver has a fail-safe feature which guarantees a high output state when the inputs are left open. The LTC85 is fully specified over the commercial and extended industrial temperature range., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICL PPLICTIO Driver Outputs O1 E1 DE1 1 D V CC1 GND1 t O2 E2 V CC2 t DE2 2 D GND2 LTC85 T1 LTC85 T2 sn 85LTC85ffs 1

2 SOLTE XI TI GS W W W (Note 1) Supply Voltage... 12V Control Input Voltages....5V to V CC +.5V Driver Input Voltage....5V to V CC +.5V Driver Output Voltage... ±1V eceiver Input Voltage... ±1V eceiver Output Voltages....5V to V CC +.5V Operating Temperature ange LTC85I... C T 85 C LTC85C... C T 7 C LTC85M (OSOLETE) C T 125 C Lead Temperature (Soldering, 1 sec)... 3 C PCKGE/ODE I FO O E DE N8 PCKGE 8-LED PLSTIC P TOP VIEW D V CC GND S8 PCKGE 8-LED PLSTIC SOIC T JMX = 125 C, θ J = 1 C/ W (N) T JMX = 15 C, θ J = 15 C/ W (S) J8 PCKGE 8-LED CEMIC P T JMX = 155 C, θ J = 1 C/ W (J) W OSOLETE PCKGE Consider the N8 Package for lternate Source TIO ODE PT NME LTC85CN8 LTC85CS8 LTC85IN8 LTC85IS8 S8 PT MKING 85 85I ODE PT NME LTC85CJ8 LTC85MJ8 Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTICL CHCTEISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25 C. V CC = 5V ±5%, unless otherwise noted. (Notes 2 and 3) SYMOL PMETE CONTIONS MIN TYP MX NITS V OD1 Differential Driver Output Voltage (nloaded) I O = 5 V V OD2 Differential Driver Output Voltage (with Load) = 5Ω (S22) 2 V = 27Ω (S85), Figure V V OD Change in Magnitude of Driver Differential = 27Ω or = 5Ω, Figure 1.2 V Output Voltage for Complementary States V OC Driver Common Mode Output Voltage = 27Ω or = 5Ω, Figure 1 3 V V OC Change in Magnitude of Driver Common-Mode = 27Ω or = 5Ω, Figure 1.2 V Output Voltage for Complementary States V IH Input High Voltage DE,, E 2 V V IL Input Low Voltage DE,, E.8 V I IN1 Input Current DE,, E ±2 µ I IN2 Input Current (, ) DE =, V CC = V V IN = 12V ±1 m or 5.25V V IN = 7V.8 m V TH Differential Input Threshold Voltage 7V V CM 12V.2.2 V for eceiver V TH eceiver Input Hysteresis V CM = V 7 mv V OH eceiver Output High Voltage I O = m, V ID = 2mV 3.5 V V OL eceiver Output Low Voltage I O = m, V ID = 2mV. V I OZ Three-State (High Impedance) Output V CC = Max,.V V O 2.V ±1 µ Current at eceiver IN eceiver Input esistance 7V V CM 12V 12 kω 2 sn85 LTC85ffs

3 SWITCHI G CHCTEISTICS LTC85 The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25 C.V CC = 5V ±5%, unless otherwise noted. (Notes 2 and 3) SYMOL PMETE CONTIONS MIN TYP MX NITS I CC Supply Current No Load, Pins 2, Outputs Enabled 5 9 µ 3, = V or 5V Outputs Disabled 3 5 µ I OSD1 Driver Short-Circuit Current, V OT = HIGH V O = 7V m I OSD2 Driver Short-Circuit Current, V OT = LOW V O = 1V m I OS eceiver Short-Circuit Current V V O V CC 7 85 m t PLH Driver Input to Output FF = 5Ω, C L1 = C L2 = 1pF, ns t PHL Driver Input to Output (Figures 3 and 5) ns t SKEW Driver Output to Output 5 1 ns t r, t f Driver ise or Fall Time ns t ZH Driver Enable to Output High C L = 1pF (Figures and 6) S2 Closed 7 ns t ZL Driver Enable to Output Low C L = 1pF (Figures and 6) S1 Closed 7 ns t LZ Driver Disable Time from Low C L = 15pF (Figures and 6) S1 Closed 7 ns t HZ Driver Disable Time from High C L = 15pF (Figures and 6) S2 Closed 7 ns t PLH eceiver Input to Output FF = 5Ω, C L1 = C L2 = 1pF, ns t PHL (Figures 3 and 7) ns t SKD t PLH t PHL Differential eceiver Skew 13 ns t ZL eceiver Enable to Output Low C L = 15pF (Figures 2 and 8) S1 Closed 2 5 ns t ZH eceiver Enable to Output High C L = 15pF (Figures 2 and 8) S2 Closed 2 5 ns t LZ eceiver Disable from Low C L = 15pF (Figures 2 and 8) S1 Closed 2 5 ns t HZ eceiver Disable from High C L = 15pF (Figures 2 and 8) S2 Closed 2 5 ns Note 1: bsolute maximum ratings are those beyond which the safety of the device cannot be guaranteed. Note 2: ll currents into device pins are positive; all currents out ot device pins are negative. ll voltages are referenced to device ground unless otherwise specified. Note 3: ll typicals are given for V CC = 5V and T = 25 C. Note : The LTC85 is guaranteed by design to be functional over a supply voltage range of 5V ±1%. Data sheet parameters are guaranteed over the tested supply voltage range of 5V ±5%. TYPICL PEFO CE CHCTEISTICS W eceiver Output Low Voltage vs Output Current T = 25 C eceiver Output High Voltage vs Output Current T = 25 C.8.6 eceiver Output High Voltage vs Temperature I = 8m OTPT CENT (m) OTPT CENT (m) OTPT VOLTGE (V) OTPT VOLTGE (V) 5 3 OTPT VOLTGE (V) TEMPETE ( C) LTC85 TPC1 LTC85 TPC2 LTC85 TPC3 sn 85LTC85ffs 3

4 TYPICL PEFO W CE CHCTEISTICS.9.8 eceiver Output Low Voltage vs Temperature I = 8m 72 6 Driver Differential Output Voltage vs Output Current T = 25 C Driver Differential Output Voltage vs Temperature I = 5Ω OTPT VOLTGE (V) OTPT CENT (m) FFEENTIL VOLTGE (V) TEMPETE ( C) OTPT VOLTGE (V) TEMPETE ( C) LTC85 TPC3 LTC85 TPC5 LTC85 TPC6 Driver Output Low Voltage vs Output Current Driver Output High Voltage vs Output Current TTL Input Threshold vs Temperature 9 8 T = 25 C T = 25 C OTPT CENT (m) OTPT CENT (m) INPT THESHOLD VOLTGE (V) OTPT VOLTGE (V) OTPT VOLTGE (V) TEMPETE ( C) LTC85 TPC7 LTC85 TPC8 LTC85 TPC9 7.5 eceiver t PLH t PHL vs Temperature 5. Driver Skew vs Temperature 6 Supply Current vs Temperature TIME (ns) TIME (ns) SPPLY CENT (µ) VE ENLED VE SLED TEMPETE ( C) TEMPETE ( C) TEMPETE ( C) LTC85 TPC1 LTC85 TPC11 LTC85 TPC12 sn85 LTC85ffs

5 PI F CTIO S O (Pin 1): eceiver Output. If the receiver output is enabled(e low), then if > by 2mV, O will be high. If < by 2mV, then O will be low. E (Pin 2): eceiver Output Enable. low enables the receiver output, O. high input forces the receiver output into a high impedance state. DE (Pin 3): Driver Outputs Enable. high on DE enables the driver output. and, and the chip will function as a line driver. low input will force the driver outputs into a high impedance state and the chip will function as a line receiver. (Pin ): Driver Input. If the driver outputs are enabled (DE high), then a low on forces the outputs low and high. high on with the driver outputs enabled will force high and low. GND (Pin 5): Ground Connection. (Pin 6): Driver Output/eceiver Input. (Pin 7): Driver Output/eceiver Input. V CC (Pin 8): Positive Supply;.75 < V CC < TEST CICITS V OD V OC ECEIVE OTPT TEST POINT C L 15pF 1k S1 S2 1k V CC LTC85 F1 LTC85 F2 Figure 1. Driver DC Test Load Figure 2. eceiver Timing Test Load 3V DE FF C L1 C L2 E 15pF O OTPT NDE TEST 5Ω C L S1 S2 V CC LTC85 F2 LTC85 F3 Figure 3. Driver/eceiver Timing Test Circuit Figure. Driver Timing Test Load #2 SWITCHI G TI E WVEFO S W W 3V V t PLH f = 1MHz, t r 1ns, t f 1ns t PLH 1/2 V O V O V V O V O 1/2 VO 1% t r t SKEW 8% V FF = V() V() t f t SKEW 9% 2% LTC85 F5 Figure 5. Driver Propagation Delays sn 85LTC85ffs 5

6 SWITCHI G TI E WVEFO S W W 3V V f = 1MHz, t r 1ns, t f 1ns 5V, V OL t ZL 2.3V OTPT NOMLLY LOW t LZ.5V V OH, V t ZH 2.3V OTPT NOMLLY HIGH t HZ.5V LTC85 F6 Figure 6. Driver Enable and Disable Times V OH V OL t PHL OTPT f = 1MHz, t r 1ns, t f 1ns t PLH V OD2, V V OD2 INPT LTC85 F7 Figure 7. eceiver Propagation Delays E 3V V f = 1MHz, t r 1ns, t f 1ns 5V t ZL OTPT NOMLLY LOW t LZ.5V V t ZH OTPT NOMLLY HIGH t HZ.5V LTC85 F8 Figure 8. eceiver Enable and Disable Times F CTIO TLES LTC85 Transmitting 6 INPTS LINE OTPTS E DE CONTION X 1 1 No Fault 1 X 1 No Fault 1 X X X Z Z X 1 X Fault Z Z LTC85 eceiving INPTS OTPTS E DE.2V 1.2V Inputs Open 1 1 X Z sn85 LTC85ffs

7 W PPLICTIO S I FO TIO asic Theory of Operation Previous S85 transceivers have been designed using bipolar technology because the common-mode range of the device must extend beyond the supplies and the device must be immune to ESD damage and latchup. nfortunately, the bipolar devices draw a large amount of supply current, which is unacceptable for the numerous applications that require low power consumption. The LTC85 is the first CMOS S85/S22 transceiver which features ultra-low power consumption without sacrificing ESD and latchup immunity. The LTC85 uses a proprietary driver output stage, which allows a common-mode range that extends beyond the power supplies while virtually eliminating latchup and providing excellent ESD protection. Figure 9 shows the LTC85 output stage while Figure 1 shows a conventional CMOS output stage. When the conventional CMOS output stage of Figure 1 enters a high impedance state, both the P-channel (P1) and the N-channel (N1) are turned off. If the output is then driven above V CC or below ground, the P + /N-well diode (D1) or the N + /P-substrate diode (D2) respectively will turn on and clamp the output to the supply. Thus, the output stage is no longer in a high impedance state and is not able to meet the S85 common-mode range requirement. In addition, the large amount of current flowing through either diode will induce the well known CMOS latchup condition, which could destroy the device. The LTC85 output stage of Figure 9 eliminates these problems by adding two Schottky diodes, SD3 and SD. The Schottky diodes are fabricated by a proprietary modification to the standard N-well CMOS process. When the output stage is operating normally, the Schottky diodes are forward biased and have a small voltage drop across them. When the output is in the high impedance state and is driven above V CC or below ground, the parasitic diodes D1 or D2 still turn on, but SD3 or SD will reverse bias and prevent current from flowing into the N-well or the substrate. Thus, the high impedance state is maintained even with the output voltage beyond the supplies. With no minority carrier current flowing into the N-well or substrate, latchup is virtually eliminated under power-up or power-down conditions. V CC P1 SD3 P1 V CC D1 D1 LOGIC SD OTPT LOGIC OTPT N1 D2 N1 D2 LTC85 F9 LTC85 F1 Figure 9. LTC85 Output Stage Figure 1. Conventional CMOS Output Stage sn 85LTC85ffs 7

W PPLICTIO S I FO TIO The LTC85 output stage will maintain a high impedance state until the breakdown of the N-channel or P-channel is reached when going positive or negative respectively.

This clamp protects the MOS gates from ESD voltages well over 2V.

8 W PPLICTIO S I FO TIO The LTC85 output stage will maintain a high impedance state until the breakdown of the N-channel or P-channel is reached when going positive or negative respectively. The output will be clamped to either V CC or ground by a Zener voltage plus a Schottky diode drop, but this voltage is way beyond the S85 operating range. This clamp protects the MOS gates from ESD voltages well over 2V. ecause the ESD injected current in the N-well or substrate consists of majority carriers, latchup is prevented by careful layout techniques. Propagation Delay Many digital encoding schemes are dependent upon the difference in the propagation delay times of the driver and the receiver. sing the test circuit of Figure 13, Figures 11 and 12 show the typical LTC85 receiver propagation delay. The receiver delay times are: t PLH t PHL = 9ns Typ, V CC = 5V The driver skew times are: Skew = 5ns Typ, V CC = 5V 1ns Max, V CC = 5V, T = C to 85 C VE OTPTS VE OTPTS ECEIVE OTPT O ECEIVE OTPT O LTC85 F11 LTC85 F12 Figure 11. eceiver t PHL Figure 12. eceiver t PLH TTL IN t r, t f < 6ns D 1pF 1Ω ECEIVE OT 1pF LTC85 F13 Figure 13. eceiver Propagation Delay Test Circuit 8 sn85 LTC85ffs

W PPLICTIO S I FO TIO LTC85 Line Length vs Data ate The maximum line length allowable for the S22/S85 standard is feet.

1Ω O TTL IN LTC85 NOISE GENETO C D FT 26WG TWISTED PI LTC85 TTL OT COMMON MODE VOLTGE ( + )/2 Figure 1.

the line, The LTC85 is able to reconstruct the data stream at the end of feet of twisted pair wire. Figure 17.

System Differential Voltage at 11kHz When specifying line length vs maximum data rate the curve in Figure 19 should be used: Figure

9 W PPLICTIO S I FO TIO LTC85 Line Length vs Data ate The maximum line length allowable for the S22/S85 standard is feet. Figures 17 and 18 show that the LTC85 is able to comfortably drive feet of wire at 11kHz. 1Ω O TTL IN LTC85 NOISE GENETO C D FT 26WG TWISTED PI LTC85 TTL OT COMMON MODE VOLTGE ( + )/2 Figure 1. Line Length Test Circuit sing the test circuit in Figure 1, Figures 15 and 16 show that with ~2V P-P common mode noise injected on the line, The LTC85 is able to reconstruct the data stream at the end of feet of twisted pair wire. Figure 17. System Common Mode Voltage at 11kHz O LTC85 F17 COMMON MODE VOLTGE ( ) O COMMON MODE VOLTGE ( + )/2 LTC85 F15 LTC85 F18 Figure 18. System Differential Voltage at 11kHz When specifying line length vs maximum data rate the curve in Figure 19 should be used: Figure 15. System Common Mode Voltage at 19.2kHz 1k O FFEENTIL VOLTGE CLE LENGTH (FT) 1k 1 1 1k 1k 1M 2.5M 1M MXIMM DT TE LTC85 F16 LTC85 F19 Figure 16. System Differential Voltage at 19.2kHz Figure 19. Cable Length vs Maximum Data ate sn 85LTC85ffs 9

10 PCKGE DESCIPTIO LTC85 TYPICL PPLICTIO S Typical S85 Network t t LTC85 T3 J8 Package 8-Lead CEP (Narrow.3 Inch, Hermetic) (eference LTC DWG # ).5.68 ( ) FLL LED OPTION.3 SC (.762 SC) CONE LEDS OPTION ( PLCS).23.5 ( ) HLF LED OPTION.5 (.127) MIN.25 (.635) D TYP.5 (1.287) MX ( ).2 (5.8) MX.15.6 ( ).8.18 (.23.57) 15 NOTE: LED MENSIONS PPLY TO SOLDE P/PLTE O TIN PLTE LEDS.5.65 ( ).1.26 (.36.66).1 (2.5) SC MIN J OSOLETE PCKGE 1 sn85 LTC85ffs

11 PCKGE DESCIPTIO LTC85 N8 Package 8-Lead PP (Narrow.3 Inch) (eference LTC DWG # ).* (1.16) MX ±.15* (6.77 ±.381) ( ).5.65 ( ).13 ±.5 (3.32 ±.127).9.15 ( ) ( ).65 (1.651) TYP.1 (2.5) SC *THESE MENSIONS DO NOT INCLDE MOLD FLSH O POTSIONS. MOLD FLSH O POTSIONS SHLL NOT EXCEED.1 INCH (.25mm).125 (3.175) MIN.18 ±.3 (.57 ±.76).2 (.58) MIN N8 198 S8 Package 8-Lead Plastic Small Outline (Narrow.15 Inch) (eference LTC DWG # ) * (.81 5.) ( ) ** ( ) SO (.23.25).1.2 (.25.58) 5 8 TYP ( )..1 (.11.25).16.5 ( ) * MENSION DOES NOT INCLDE MOLD FLSH. MOLD FLSH SHLL NOT EXCEED.6" (.152mm) PE SIDE ** MENSION DOES NOT INCLDE INTELED FLSH. INTELED FLSH SHLL NOT EXCEED.1" (.25mm) PE SIDE.1.19 ( ) TYP.5 (1.27) SC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. sn 85LTC85ffs 11

12 ELTED PTS PT NME DESCIPTION COMMENTS LTC86/LTC87 Low Power Quad S85 Drivers 11µ Supply Current LTC88/LTC89 Low Power Quad S85 eceivers 7m Supply Current LTC9/LTC91 Low Power Full-Duplex S85 Transceivers 3µ Supply Current LTC18 3.3V Supply S85 Transceiver Lower Supply Voltage LTC181 Low Power S85 Transceiver with Shutdown Lowest Power LTC182 S85 Transceiver with Carrier Detect ±15kV ESD, Fail-Safe LTC183 Low Power, Low EMI S85 Transceiver Slew ate Limited Driver Outputs, Lowest Power LTC18 S85 Transceiver with Fail-Safe ±15kV ESD, MSOP Package LTC185 1Mbps S85 Transceiver High Speed LTC1518/LTC Mbps Quad S85 eceivers Higher Speed, LTC88/LTC89 Pin-Compatible LTC152 LVDS-Compatible Quad eceiver 1mV Threshold, Low Channel-to-Channel Skew LTC V Isolated S85 Transceiver Full-Duplex, Self-Powered sing External Transformer LTC Mbps S85 Transceiver Industry-Standard Pinout, 5ps Propagation Delay Skew LTC1686/LTC Mbps Full-Duplex S85 Transceiver LTC9/LTC91 Pin Compatible LTC1688/LTC1689 1Mbps Quad S85 Drivers Highest Speed, LTC86/LTC87 Pin Compatible LTC169 Full-Duplex S85 Transceiver with Fail-Safe ±15kV ESD, LTC9 Pin Compatible LT1785/LTC1785 ±6V Protected S85 Transceivers ±15kV ESD, Fail-Safe (LT1785) LT1791/LTC1791 ±6V Protected Full-Duplex S85 Transceivers ±15kV ESD, Fail-Safe (LT1791) 12 sn85 LTC85ffs LT/LCG K EV F PINTED IN THE S Linear Technology Corporation 163 McCarthy lvd., Milpitas, C (8) FX: (8) LINE TECHNOLOGY COPOTION 199

FEATURES DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO LTC1481 Ultralow Power RS485 Transceiver with Shutdown

FEATURES DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO LTC1481 Ultralow Power RS485 Transceiver with Shutdown FETES Low Power: I CC = 12µ Max with Driver Disabled Drivers/eceivers Have ±1kV ESD Protection 1µ Quiescent Current in Shutdown Mode High Speed: p to 2.5Mbits/s Data ate I CC = 5µ Max with Driver Enabled,