5 V, Slew-Rate Limited, Half-Duplex and Full-Duplex RS-485/RS-422 Transceivers

Transcription

1 5 V, Slew-ate Limited, Half-Duplex and Full-Duplex S-485/S-422 Transceivers DM4850/DM485/DM4852/DM4853/DM4854/DM4855/DM4856/DM4857 FETUES EI S-485-/S-422-compliant Data rate options DM4850/DM4854: 5 kbps DM485/DM4855: 500 kbps DM4852/DM4856: 2.5 Mbps DM4853/DM4857: 0 Mbps Half- and full-duplex options educed slew rates for low EMI True fail-safe receiver inputs 5 µ (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-z when disabled or powered off 7 V to +2 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with the MX308x Specified over the 40 C to +85 C temperature range vailable in 8-lead SOIC, LFCSP, and MSOP packages PPLICTIONS Low power S-485 applications EMI-sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators GENEL DESCIPTION The DM4850/DM485/DM4852/DM4853/DM4854/ DM4855/DM4856/DM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EI Standards S-485 and S-422. The DM4850/DM485/DM4852/DM4853 are halfduplex transceivers that share differential lines and have separate enable inputs for the driver and receiver. The full-duplex DM4854/DM4855/DM4856/DM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The parts have a /8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. ecause only one driver should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ends. ev. C Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective owners. FUNCTIONL LOCK DIGMS O E DE DI O DI D V CC DM4850/DM485/ DM4852/DM4853 GND Figure. D V CC DM4854/DM4855/ DM4856/DM4857 GND Figure 2. The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The parts are fully specified over the commercial and industrial temperature ranges and are available in 8-lead SOIC, LFCSP (DM4850/DM485/DM4852/DM4853), and MSOP (DM4850 only) packages. Table. Selection Table Part No. Half-/Full-Duplex Data ate DM4850 Half 5 kbps DM485 Half 500 kbps DM4852 Half 2.5 Mbps DM4853 Half 0 Mbps DM4854 Full 5 kbps DM4855 Full 500 kbps DM4856 Full 2.5 Mbps DM4857 Full 0 Mbps One Technology Way, P.O. ox 906, Norwood, M , U.S.. Tel: Fax: nalog Devices, Inc. ll rights reserved. Z Y

2 TLE OF CONTENTS Features... pplications... Functional lock Diagrams... General Description... evision History... 2 Specifications... 3 DM4850/DM4854 Timing Specifications... 4 DM485/DM4855 Timing Specifications... 4 DM4852/DM4856 Timing Specifications... 5 DM4853/DM4857 Timing Specifications... 5 bsolute Maximum atings... 6 ESD Caution... 6 Pin Configurations and Function Descriptions... 7 Typical Performance Characteristics... 8 Test Circuits... 0 Switching Characteristics... Circuit Description... 2 Slew-ate Control... 2 eceiver Input Filtering... 2 Half-/Full-Duplex Operation... 2 High eceiver Input Impedance... 3 Three-State us Connection... 3 Shutdown Mode... 3 Fail-Safe Operation... 3 Current Limit and Thermal Shutdown... 3 Outline Dimensions... 4 Ordering Guide... 5 EVISION HISTOY / ev. to ev. C Change to Table 8, Pin 3 Description... 7 Changes to Figure Changes to Ordering Guide /09 ev. to ev. dded MSOP Package... Throughout Changes to Table Changes to Table dded Figure 4; enumbered Figures Sequentially... 7 Moved Typical Performance Characteristics Section... 8 Changes to Figure 24, Figure Changes to Figure Change to Shutdown Mode Section... 3 Updated Outline Dimensions... 4 Changes to Ordering Guide /09 ev. 0 to ev. Changes to Ordering Guide /04 evision 0: Initial Version ev. C Page 2 of 6

3 SPECIFICTIONS VCC = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Differential Output Voltage, VOD VCC V =, see Figure V = 50 Ω (S-422), see Figure V = 27 Ω (S-485), see Figure 8 VOD3.5 5 V VTST = 7 V to 2 V, see Figure 9 VOD for Complementary Output States 0.2 V = 27 Ω or 50 Ω, see Figure 8 Common-Mode Output Voltage, VOC 3 V = 27 Ω or 50 Ω, see Figure 8 VOC for Complementary Output States 0.2 V = 27 Ω or 50 Ω, see Figure 8 Output Short-Circuit Current, VOUT = High m 7 V < VOUT < +2 V Output Short-Circuit Current, VOUT = Low m 7 V < VOUT < +2 V DIVE INPUT LOGIC CMOS Input Logic Threshold Low 0.8 V CMOS Input Logic Threshold High 2.0 V CMOS Logic Input Current (DI) ± µ DE Input esistance to GND 220 kω ECEIVE Differential Input Threshold Voltage, VTH mv 7 V < VOC < +2 V Input Hysteresis 20 mv 7 V < VOC < +2 V Input esistance (, ) kω 7 V < VOC < +2 V Input Current (, ) 0.25 m VIN = +2 V 0. m VIN = 7 V CMOS Logic Input Current (E) ± µ CMOS Output Voltage Low 0.4 V IOUT = +4 m CMOS Output Voltage High 4.0 V IOUT = 4 m Output Short-Circuit Current 7 85 m VOUT = GND or VCC Three-State Output Leakage Current ±2 µ 0.4 V VOUT 2.4 V POWE SUPPLY CUENT 5 kbps Options (DM4850/DM4854) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V µ DE = VCC 500 kbps Options (DM485/DM4855) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V µ DE = VCC 2.5 Mbps Options (DM4852/DM4856) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V µ DE = VCC 0 Mbps Options (DM4853/DM4857) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V Guaranteed by design µ DE = VCC ev. C Page 3 of 6

4 DM4850/DM4854 TIMING SPECIFICTIONS VCC = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 5 kbps Propagation Delay, tplh, tphl ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Skew, tskew 70 ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 ise/fall Times, t, tf ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Enable Time, tzh 2000 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM4850 Disable Time, tzl 2000 ns L = 500 Ω, CL = 5 pf, see Figure 2, DM4850 Enable Time from Shutdown 4000 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM4850 ECEIVE Propagation Delay, tplh, tphl ns CL = 5 pf, see Figure 22 Differential Skew, tskew 255 ns CL = 5 pf, see Figure 22 Enable Time 5 50 ns L = kω, CL = 5 pf, see Figure 23, DM4850 Disable Time ns L = kω, CL = 5 pf, see Figure 23, DM4850 Enable Time from Shutdown 4000 ns L = kω, CL = 5 pf, see Figure 23, DM4850 Time to Shutdown ns DM4850 The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. DM485/DM4855 TIMING SPECIFICTIONS VCC = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 500 kbps Propagation Delay, tplh, tphl ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Skew, tskew 40 ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 ise/fall Times, t, tf ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Enable Time, tzh 000 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM485 Disable Time, tzl 000 ns L = 500 Ω, CL = 5 pf, see Figure 2, DM485 Enable Time from Shutdown 4000 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM485 ECEIVE Propagation Delay, tplh, tphl ns CL = 5 pf, see Figure 22 Differential Skew, tskew 250 ns CL = 5 pf, see Figure 22 Enable Time 5 50 ns L = kω, CL = 5 pf, see Figure 23, DM485 Disable Time ns L = kω, CL = 5 pf, see Figure 23, DM485 Enable Time from Shutdown 4000 ns L = kω, CL = 5 pf, see Figure 23, DM485 Time to Shutdown ns DM485 The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ev. C Page 4 of 6

5 DM4852/DM4856 TIMING SPECIFICTIONS VCC = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 5. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 2.5 Mbps Propagation Delay, tplh, tphl ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Skew, tskew 50 ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 ise/fall Times, t, tf 40 ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Enable Time, tzh 80 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM4852 Disable Time, tzl 80 ns L = 500 Ω, CL = 5 pf, see Figure 2, DM4852 Enable Time from Shutdown 4000 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM4852 ECEIVE Propagation Delay, tplh, tphl ns CL = 5 pf, see Figure 22 Differential Skew, tskew 50 ns CL = 5 pf, see Figure 22 Enable Time 5 50 ns L = kω, CL = 5 pf, see Figure 23, DM4852 Disable Time ns L = kω, CL = 5 pf, see Figure 23, DM4852 Enable Time from Shutdown 4000 ns L = kω, CL = 5 pf, see Figure 23, DM4852 Time to Shutdown ns DM4852 The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. DM4853/DM4857 TIMING SPECIFICTIONS VCC = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 6. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 0 Mbps Propagation Delay, tplh, tphl 0 30 ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Skew, tskew 0 ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 ise/fall Times, t, tf 30 ns LDIFF = 54 Ω, CL = CL2 = 00 pf, see Figure 20 Enable Time, tzh 35 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM4853 Disable Time, tzl 35 ns L = 500 Ω, CL = 5 pf, see Figure 2, DM4853 Enable Time from Shutdown 4000 ns L = 500 Ω, CL = 00 pf, see Figure 2, DM4853 ECEIVE Propagation Delay, tplh, tphl ns CL = 5 pf, see Figure 22 Differential Skew, tskew 30 ns CL = 5 pf, see Figure 22 Enable Time 5 50 ns L = kω, CL = 5 pf, see Figure 23, DM4853 Disable Time ns L = kω, CL = 5 pf, see Figure 23, DM4853 Enable Time from Shutdown 4000 ns L = kω, CL = 5 pf, see Figure 23, DM4853 Time to Shutdown ns DM4853 The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ev. C Page 5 of 6

6 SOLUTE MXIMUM TINGS Table 7. Parameter VCC to GND Digital I/O Voltage (DE, E, DI, O) ating 6 V 0.3 V to VCC V Driver Output/eceiver Input Voltage 9 V to +4 V Operating Temperature ange 40 C to +85 C Storage Temperature ange 65 C to +25 C θj Thermal Impedance SOIC 0 C/W LFCSP 62 C/W MSOP 33. C/W Lead Temperature Soldering (0 sec) 300 C Vapor Phase (60 sec) 25 C Infrared (5 sec) 220 C Stresses above those listed under bsolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CUTION ev. C Page 6 of 6

7 PIN CONFIGUTIONS ND FUNCTION DESCIPTIONS DM4850/DM485/ DM4852/DM4853 DM4850/ E 2 DM485/ DM4852/ DM O 8 V CC DE 3 6 TOP VIEW DI 4 (Not to Scale) 5 GND Figure 3. DM4850/DM485/DM4852/DM4853 Pin Configuration, SOIC and MSOP O E 2 DE 3 DI 4 PIN INDICTO TOP VIEW (Not to Scale) 8 V CC GND NOTES. THE EXPOSED PDDLE ON THE UNDESIDE OF THE PCKGE SHOULD E SOLDEED TO THE GOUND PLNE TO INCESE THE ELIILITY OF THE SOLDE JOINTS ND TO MXIMIZE THE THEML CPILITY OF THE PCKGE. Figure 4. DM4850/DM485/DM4852/DM4853 Pin Configuration, LFCSP Table 8. DM4850/DM485/DM4852/DM4853 Pin Descriptions Pin No. Mnemonic Description O eceiver Output. When O is enabled, if ( ) 30 mv, O = high; if ( ) 200 mv, O = low. 2 E eceiver Output Enable. low level on this pin enables the receiver output, O. high level places O into a high impedance state. 3 DE Driver Output Enable. high level on this pin enables the driver differential outputs, and. low level places them into a high impedance state. 4 DI Driver Input. When the driver is enabled, a logic low on DI forces low and high, whereas a logic high on DI forces high and low. 5 GND Ground. 6 Noninverting eceiver Input /Noninverting Driver Output. 7 Inverting eceiver Input /Inverting Driver Output. 8 VCC 5 V Power Supply. V CC DM4854/ 8 DM4855/ O 2 7 DM4856/ DI 3 DM Z TOP VIEW GND 4 (Not to Scale) 5 Y Figure 5. DM4854/DM4855/DM4856/DM4857 Pin Configuration, SOIC Table 9. DM4854/DM4855/DM4856/DM4857 Pin Descriptions Pin No. Mnemonic Description VCC 5 V Power Supply. 2 O eceiver Output. When O is enabled, if ( ) 30 mv, O = high; if ( ) 200 mv, O = low. 3 DI Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low. 4 GND Ground. 5 Y Noninverting Driver Output. 6 Z Inverting Driver Output. 7 Inverting eceiver Input. 8 Noninverting eceiver Input. ev. C Page 7 of 6

8 TYPICL PEFOMNCE CHCTEISTICS DM4853: DE = V CC 350 UNLODED SUPPLY CUENT ( ) DM4853: DE = GND DM4850: DE = V CC DM4850: DE = GND TEMPETUE ( C) OUTPUT LOW VOLTGE (V) TEMPETUE ( C) Figure 6. Unloaded Supply Current vs. Temperature Figure 9. eceiver Output Low Voltage vs. Temperature ECEIVE OUTPUT CUENT (m) ECEIVE OUTPUT LOW VOLTGE (V) OUTPUT HIGH VOLTGE (V) TEMPETUE ( C) Figure 7. eceiver Output Current vs. eceiver Output Low Voltage Figure 0. eceiver Output High Voltage vs. Temperature 90 ECEIVE OUTPUT CUENT (m) DIVE OUTPUT CUENT (m) ECEIVE OUTPUT HIGH VOLTGE (V) DIFFEENTIL OUTPUT VOLTGE (V) Figure 8. eceiver Output Current vs. eceiver Output High Voltage Figure. Driver Output Current vs. Differential Output Voltage ev. C Page 8 of 6

9 DM4855 OUTPUT CUENT (m) OUTPUT VOLTGE (V) POPGTION DELY (ns) DM TEMPETUE ( C) Figure 2. Output Current vs. Driver Output Low Voltage Figure 5. eceiver Propagation Delay vs. Temperature 0 OUTPUT CUENT (m) OUTPUT VOLTGE (V) CH.00VΩ W CH2.00VΩ W M 400ns CH3 2.00V CH3 2.00VΩ W CH4 5.00VΩ Figure 3. Output Current vs. Driver Output High Voltage Figure 6. Driver/eceiver Propagation Delay (DM4855, 500 kbps) POPGTION DELY (ns) 350 DM DM TEMPETUE ( C) Figure 4. Driver Propagation Delay vs. Temperature CH 2.00VΩ W CH2.00VΩ M 50.0ns CH 480mV CH3.00VΩ W CH4 5.00VΩ Figure 7. Driver/eceiver Propagation Delay (DM4857, 4 Mbps) ev. C Page 9 of 6

10 TEST CICUITS V OD V OC V O 3V DE IN DE S C L L V OUT V CC S Figure 8. Driver Voltage Measurement Figure 2. Driver Enable/Disable 3 75 &! V O D3 6 0 &! 3 75 &! V T ST E C L V OUT Figure 9. Driver Voltage Measurement over Common-Mode Voltage ange Figure 22. eceiver Propagation Delay LDIFF C L C L V.5V E IN S E C L L V OUT V CC S Figure 20. Driver Propagation Delay Figure 23. eceiver Enable/Disable ev. C Page 0 of 6

11 SWITCHING CHCTEISTICS 3V 3V.5V.5V DE.5V.5V 0V t PLH t PHL t ZL t LZ 0V /2V OD V OD 5V 90% POINT 0% POINT 0V t t SKEW = t PLH t PHL t F 90% POINT 0% POINT ,, t ZH 2.3V 2.3V t HZ V OL + 0.5V V OH 0.5V V OL V OH 0V Figure 24. Driver Propagation Delay, ise/fall Timing Figure 26. Driver Enable/Disable Timing 3V E.5V.5V, 0V 0V t ZL t LZ 0V O t PLH t PHL.5V.5V t SKEW = t PLH t PHL V OH V OL O O 0V tzh.5v OUTPUT LOW OUTPUT HIGH.5V t HZ V OL + 0.5V V OH 0.5V V OL V OH Figure 25. eceiver Propagation Delay Figure 27. eceiver Enable/Disable Timing ev. C Page of 6

12 CICUIT DESCIPTION The DM4850/DM485/DM4852/DM4853/DM4854/ DM4855/DM4856/DM4857 are high speed S-485/ S-422 transceivers offering enhanced performance over industry-standard devices. ll devices in the family contain one driver and one receiver, but offer a choice of performance options. The devices feature true fail-safe operation, which means that a logic high receiver output is guaranteed when the receiver inputs are open-circuit or short-circuit, or when they are connected to a terminated transmission line with all drivers disabled (see the Fail-Safe Operation section). SLEW-TE CONTOL The DM4850 and DM4854 feature a controlled slew-rate driver that minimizes electromagnetic interference (EMI) and reduces reflections caused by incorrectly terminated cables, allowing error-free data transmission rates up to 5 kbps. The DM485 and DM4855 offer a higher limit on driver output slew rate, allowing data transmission rates up to 500 kbps. The driver slew rates of the DM4852 and DM4856 and the DM4853 and DM4857 are not limited, offering data transmission rates up to 2.5 Mbps and 0 Mbps, respectively. ECEIVE INPUT FILTEING The receivers of all the devices incorporate input hysteresis. In addition, the receivers of the 5 kbps DM4850 and DM4854 and the 500 kbps DM485 and DM4855 incorporate input filtering. This enhances noise immunity with differential signals that have very slow rise and fall times. However, it causes the propagation delay to increase by 20%. HLF-/FULL-DUPLEX OPETION Half-duplex operation implies that the transceiver can transmit and receive, but it can do only one of these at any given time. However, with full-duplex operation, the transceiver can transmit and receive simultaneously. The DM4850/DM485/DM4852/ DM4853 are half-duplex devices in which the driver and the receiver share differential bus terminals. The DM4854/ DM4855/DM4856/DM4857 are full-duplex devices that have dedicated driver output and receiver input pins. Figure 28 and Figure 29 show typical half- and full-duplex topologies. DM4850/DM485/ DM4852/DM4853 DM4850/DM485/ DM4852/DM4853 O O E E DE DE DI D D DI DM4850/DM485/ DM4852/DM4853 D DM4850/DM485/ DM4852/DM4853 D O E DE DI O E DE DI MXIMUM NUME OF TNSCEIVES ON US: Figure 28. Typical Half-Duplex S-485 Network Topology V CC V CC O DI DM4854/DM4855/ DM4856/DM4857 D GND Z Y Y Z DM4854/DM4855/ DM4856/DM4857 Figure 29. Typical Full-Duplex Point-to-Point S-485 Network Topology D GND DI O ev. C Page 2 of 6

13 HIGH ECEIVE INPUT IMPEDNCE The input impedance of the DM4850/DM485/DM4852/ DM4853/DM4854/DM4855/DM4856/DM4857 receivers is 96 kω, which is eight times higher than the standard S-485 unit load of 2 kω. This 96 kω impedance enables a standard driver to drive 32 unit loads or to be connected to 256 DM4850/ DM485/DM4852/DM4853/DM4854/DM4855/ DM4856/DM4857 receivers. n S-485 bus, driven by a single standard driver, can be connected to a combination of DM4850/DM485/DM4852/DM4853/DM4854/ DM4855/DM4856/DM4857 devices and standard unit load receivers, up to an equivalent of 32 standard unit loads. THEE-STTE US CONNECTION The half-duplex parts (DM4850/DM485/DM4852/ DM4853) have a driver enable (DE) pin that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. Similarly, the half-duplex devices have an active low receiver enable (E) pin. Taking this pin low enables the receiver, whereas taking it high puts the receiver outputs into a high impedance state. This allows several driver outputs to be connected to an S-485 bus. Note that only one driver should be enabled at a time, but that many receivers can be enabled. SHUTDOWN MODE The DM4850/DM485/DM4852/DM4853 have a low power shutdown mode, which is enabled by taking E high and DE low. If shutdown mode is not used, the fact that DE is active high and E is active low offers a convenient way of switching the device between transmit and receive by tying DE and E together. If DE is driven low and E is driven high for less than 50 ns, the devices are guaranteed not to enter shutdown mode. If DE is driven low and E is driven high for at least 3000 ns, the devices are guaranteed to enter shutdown mode. FIL-SFE OPETION The DM4850/DM485/DM4852/DM4853/DM4854/ DM4855/DM4856/DM4857 offer true fail-safe operation while remaining fully compliant with the ±200 mv EI/TI-485 standard. logic high receiver output is generated when the receiver inputs are shorted together or open circuit, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between 30 mv and 200 mv. If the differential receiver input voltage ( ) is greater than or equal to 30 mv, O is logic high. If ( ) is less than or equal to 200 mv, O is logic low. In the case of a terminated bus with all transmitters disabled, the differential input voltage of the receiver is pulled to 0 V by the internal circuitry of the DM4850/DM485/DM4852/ DM4853/DM4854/DM4855/DM4856/DM4857, which results in a logic high with 30 mv minimum noise margin. CUENT LIMIT ND THEML SHUTDOWN The DM4850/DM485/DM4852/DM4853/DM4854/ DM4855/DM4856/DM4857 incorporate two protection mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 m. Under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 50 C, and does not turn them back on until the temperature falls to 30 C. ev. C Page 3 of 6

14 OUTLINE DIMENSIONS 4.00 (0.574) 3.80 (0.497) 0.25 (0.0098) 0.0 (0.0040) COPLNITY 0.0 SETING PLNE 5.00 (0.968) 4.80 (0.890) (0.0500) SC 6.20 (0.244) 5.80 (0.2284).75 (0.0688).35 (0.0532) 0.5 (0.020) 0.3 (0.022) 0.25 (0.0098) 0.7 (0.0067) 0.50 (0.096) 0.25 (0.0099).27 (0.0500) 0.40 (0.057) COMPLINT TO JEDEC STNDDS MS-02- CONTOLLING DIMENSIONS E IN MILLIMETES; INCH DIMENSIONS (IN PENTHESES) E OUNDED-OFF MILLIMETE EQUIVLENTS FO EFEENCE ONLY ND E NOT PPOPITE FO USE IN DESIGN. 8 0 Figure Lead Standard Small Outline Package [SOIC_N] Narrow ody (-8) Dimensions shown in millimeters and (inches) PIN IDENTIFIE COPLNITY SC MX MX COMPLINT TO JEDEC STNDDS MO-87- Figure 3. 8-Lead Mini Small Outline Package [MSOP] (M-8) Dimensions shown in millimeters SQ MX 0.60 MX 0.50 SC PIN INDICTO TOP VIEW SQ EXPOSED PD (OTTOM VIEW) MX 0.70 MX MX 0.65 TYP 0.85 NOM 0.05 MX 0.0 NOM SETING PLNE EF PIN INDICTO FO POPE CONNECTION OF THE EXPOSED PD, EFE TO THE PIN CONFIGUTION ND FUNCTION DESCIPTIONS SECTION OF THIS DT SHEET. Figure Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm 3 mm ody, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ev. C Page 4 of 6

15 ODEING GUIDE Model Temperature ange Package Description Package Option randing DM4850CPZ-EEL7 40 C to +85 C 8-Lead LFCSP_VD CP-8-2 M8Q DM C to +85 C 8-Lead SOIC_N -8 DM4850Z 40 C to +85 C 8-Lead SOIC_N -8 DM4850Z-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4850MZ 40 C to +85 C 8-Lead MSOP M-8 M8Q DM4850MZ-EEL7 40 C to +85 C 8-Lead MSOP M-8 M8Q DM C to +85 C 8-Lead SOIC_N -8 DM485-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM485Z 40 C to +85 C 8-Lead SOIC_N -8 DM485Z-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4852CPZ-EEL7 40 C to +85 C 8-Lead LFCSP_VD CP-8-2 M9M DM C to +85 C 8-Lead SOIC_N -8 DM4852-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4852Z 40 C to +85 C 8-Lead SOIC_N -8 DM4852Z-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4853CPZ-EEL7 40 C to +85 C 8-Lead LFCSP_VD CP-8-2 F0 DM C to +85 C 8-Lead SOIC_N -8 DM4853-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4853Z 40 C to +85 C 8-Lead SOIC_N -8 DM4853Z-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM C to +85 C 8-Lead SOIC_N -8 DM4854-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4854Z 40 C to +85 C 8-Lead SOIC_N -8 DM C to +85 C 8-Lead SOIC_N -8 DM4855-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4855Z 40 C to +85 C 8-Lead SOIC_N -8 DM C to +85 C 8-Lead SOIC_N -8 DM4856-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4856Z 40 C to +85 C 8-Lead SOIC_N -8 DM4856Z-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM C to +85 C 8-Lead SOIC_N -8 DM4857-EEL7 40 C to +85 C 8-Lead SOIC_N -8 DM4857Z 40 C to +85 C 8-Lead SOIC_N -8 DM4857Z-EEL7 40 C to +85 C 8-Lead SOIC_N -8 Z = ohs Compliant Part. ev. C Page 5 of 6

16 NOTES nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /(C) ev. C Page 6 of 6