3.3 V Slew Rate Limited, Half Duplex RS-485/RS-422 Transceiver ADM3493

Transcription

1 3.3 V Slew ate Limited, Half uplex S-485/S-422 Transceiver M3493 FETUES Operates with 3.3 V supply Interoperable with 5 V logic EI S-422 and S-485 compliant over full CM range ata rate: 25 kbps Half duplex transceiver educed slew rates for low EMI 2 n supply current in shutdown mode Up to 256 transceivers on a bus 7 V to +12 V bus common-mode range Specified over 4 C to +85 C temperature range 8 ns skew vailable in 8-lead SOIC FUNCTIONL LOCK IGM M3493 O E E I GN Figure PPLICTIONS Low power S-485 applications EMI sensitive systems TE-CE interfaces Industrial control Packet switching Local area networks Level translators GENEL ESCIPTION The M3493 is a low power, differential line transceiver designed to operate using a single 3.3 V power supply. Low power consumption, coupled with a shutdown mode, makes it ideal for power-sensitive applications. The M3493 is suitable for communication on multipoint bus transmission lines. The device contains one driver and one receiver. esigned for half-duplex communication, the M3493 features a slew rate limited driver that minimizes EMI and reduces reflections caused by improperly terminated cables, allowing error-free data transmission at data rates up to 25 kbps. The receiver input impedance is 96 kω, allowing up to 256 transceivers to be connected on the bus. thermal shutdown circuit prevents excessive power dissipation caused by bus contention or by output shorting. If a significant temperature increase is detected in the internal driver circuitry during fault conditions then the thermal shutdown circuit forces the driver output into a high impedance state. The receiver contains a failsafe feature that results in a logic high output state, if the inputs are unconnected (floating). The M3493 is fully specified over the commercial and industrial temperature ranges and is available in an 8-lead SOIC. ev. Information furnished by nalog evices is believed to be accurate and reliable. However, no responsibility is assumed by nalog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. ox 916, Norwood, M , U.S.. Tel: Fax: nalog evices, Inc. ll rights reserved.

2 TLE OF CONTENTS Features... 1 pplications... 1 Functional lock iagram... 1 General escription... 1 evision History... 2 Specifications... 3 Timing Specifications... 4 bsolute Maximum atings... 5 ES Caution... 5 Pin Configurations and Function escriptions... 6 Switching Characteristics...8 Typical Performance Characteristics...9 Circuit escription educed EMI and eflections Low Power Shutdown Mode river Output Protection Propagation elay Typical pplications Outline imensions Ordering Guide Test Circuits... 7 EVISION HISTOY 1/5 ev. : Initial Version ev. Page 2 of 12

3 SPECIFICTIONS VCC = 3.3 V ±.3 V, T = TM to TMX, unless otherwise noted. M3493 Table 1. Parameter Min Typ Max Units Test Conditions/Comments IVE ifferential Output Voltage, VO 2. V L = 1 Ω (S-422), Vcc = 3.3 V ±5% (see Figure 3) 1.5 V L = 54 Ω (S-485) (see Figure 3) 1.5 V L = 6 Ω (S-485), Vcc = 3.3 V (see Figure 4) Δ VO for Complementary Output States 1.2 V L = 54 Ω or 1 Ω (see Figure 3) Common-Mode Output Voltage, VOC 3 V L = 54 Ω or 1 Ω (see Figure 3) Δ VOC for Common-Mode Output Voltage 1.2 V L = 54 Ω or 1 Ω (see Figure 3) IVE PUT LOGIC CMOS Input Logic Threshold Low, VIH.8 V E, I, E CMOS Input Logic Threshold High, VIL 2. V E, I, E CMOS Logic Input Current, 1 ±2 μ E, I, E Input Current (, ), 2 6 μ V = 12 V 6 μ V = 7 V E = V VCC = V or 3.6 V ECEIVE ifferential Input Threshold Voltage, VTH.2.2 V 7V < VCM < + 12 V Input Hysteresis, Δ VTH 5 mv VCM = V CMOS Output Voltage High, VOH Vcc.4 V I = 1.5 m, VI = 2 mv (see Figure 5) CMOS Output Voltage Low, VOL.4 V I = 2.5m, VI = 2mV (see Figure 5) Three-State Output Leakage Current, IOZ ±1 μ Vcc = 3.6 V, V V Vcc Input esistance, 96 kω 7 V < VCM < + 12 V POWE SUPPLY CUENT Supply Current m E = VCC m E = V or VCC E = VCC E = V No load, I = V or VCC Supply Current in Shutdown Mode, ISHN.2 1 μ E = V, E = VCC, I = VCC or V river Short-Circuit Output Current, IOS 25 m V = 7 V 25 m V = 12 V eceiver Short-Circuit Output Current, IOS ±8 ±6 m V < VO < VCC 1 ΔVO and ΔVOC are the changes in VO and VOC, respectively, when I input changes state. ev. Page 3 of 12

4 TIMG SPECIFICTIONS VCC = 3.3 V, T = 25 C, unless otherwise noted. Table 2. Parameter Min Typ Max Units Test Conditions/Comments IVE ifferential Output elay, t ns L = 6 Ω (see Figure 6 and Figure 12) ifferential Output Transition Time, tt ns L = 6 Ω (see Figure 6 and Figure 12) Propagation elay, Low-to-High Level, tplh ns L = 27 Ω (see Figure 7 and Figure 13) Propagation elay, High-to-Low Level, tphl ns L = 27 Ω (see Figure 7 and Figure 13) tplh tphl Propagation elay Skew 1, tps 1 ns L = 27 Ω (see Figure 7 and Figure 13) IVE PUT ENLE/ISLE TIMES Output Enable Time to Low Level, tpzl 9 13 ns L = 11 Ω (see Figure 9 and Figure 15) Output Enable Time to High Level, tpzh 6 8 ns L = 11 Ω (see Figure 8 and Figure 14) Output isable Time from High Level, tphz 5 8 ns L = 11 Ω (see Figure 8 and Figure 14) Output isable Time from Low Level, tplz 5 8 ns L = 11 Ω (see Figure 9 and Figure 15) Output Enable Time from Shutdown to μs L = 11 Ω (see Figure 9 and Figure 15) Low Level, tpsl Output Enable Time from Shutdown to μs L = 11 Ω (see Figure 8 and Figure 14) High Level, tpsh ECEIVE Time to Shutdown 2, tshn ns Propagation elay, Low-to-High Level, tplh ns VI = V to 3. V, CL = 15 pf (see Figure 1 and Figure 16) Propagation elay, High-to-Low Level, tphl ns VI = V to 3. V, CL = 15 pf (see Figure 1 and Figure 16) tplh tphl Propagation elay Skew, tps 5 ns VI = V to 3. V, CL = 15 pf (see Figure 1 and Figure 16) ECEIVE PUT ENLE/ISLE TIMES Output Enable Time to Low Level, tpzl 25 5 ns CL = 15 pf (see Figure 11 and Figure 17) Output Enable Time to High Level, tpzh 25 5 ns CL = 15 pf (see Figure 11 and Figure 17) Output isable Time from High Level, tphz ns CL = 15 pf (see Figure 11 and Figure 17) Output isable Time from Low Level, tplz ns CL = 15 pf (see Figure 11 and Figure 17) Output Enable Time from Shutdown to ns CL = 15 pf (see Figure 11 and Figure 17) Low Level, tpsl Output Enable Time from Shutdown to High Level, tpsh ns CL = 15 pf (see Figure 11 and Figure 17) 1 Measured on tplh () tphl () and tplh () tphl (). 2 The transceivers are put into shutdown by bringing E high and E low. If the inputs are in this state for less than 8 ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 3 ns, the parts are guaranteed to enter shutdown. ev. Page 4 of 12

5 SOLUTE MXIMUM TGS T = 25 C, unless otherwise noted. Table 3. Parameter VCC to GN igital I/O Voltage (E, E, I) igital I/O Voltage () river Output/eceiver Input Voltage Operating Temperature ange Storage Temperature ange θj Thermal Impedance 8-Lead SOIC ating 7 V.3 V to VCC +.3 V VCC.5 V to VCC +.5 V 7.5 V to V 4 C to +85 C 65 C to +125 C 121 C/W Lead Temperature Soldering (1 seconds) 3 C Vapor Phase (6 seconds) 215 C Infrared (15 seconds) 22 C Stresses above those listed under bsolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ES CUTION ES (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough this product features proprietary ES protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ES precautions are recommended to avoid performance degradation or loss of functionality. ev. Page 5 of 12

6 P CONFIGUTION N FUNCTION ESCIPTIONS O 1 E 2 E 3 I 4 M3493 TOP VIEW (Not to Scale) GN Figure 2. Pin Configuration Table 4.. Pin Function escriptions Pin No. Mnemonic escription 1 O eceiver Output. When enabled, if > by 2 mv, then O = high. If < by 2 mv, then O = low. 2 E eceiver Output Enable. low level enables the receiver output, O. high level places it in a high impedance state. If E is high and E is low, the device enters a low power shutdown mode. 3 E river Output Enable. high level enables the driver differential Outputs and. low level places it in a high impedance state. If E is high and E is low, the device enters a low power shutdown mode. 4 I river Input. When the driver is enabled, a logic low on I forces low and high while a logic high on I forces high and low. 5 GN Ground. 6 Noninverting eceiver Input and Noninverting river Output. 7 Inverted eceiver Input and Inverted river Output. 8 VCC Power Supply, 3.3 V ±.3 V. ev. Page 6 of 12

7 TEST CICUITS L /2 V O 3V S1 C L = 5pF 2 L = 11Ω V O L /2 V OC Figure 3. river VO and VOC 375Ω GENETO 1 5Ω = V OH +V OL 1.5V 2 1 PP = 25kHz, 5% UTY CYCLE, t 6.ns, Z O =5Ω. 2 C L CLUES POE N STY CPCITNCE V O L V CM = 7V TO +12V Figure 8. river Enable and isable Times (tpzh, tpsh, tphz) 375Ω V O 3V S1 L = 11Ω Figure 4. river VO with Varying Common-Mode Voltage C L =5pF 2 V I GENETO 1 5Ω V OL I OL (+) V OH Figure 5. eceiver VOH and VOL I OH ( ) PP = 25kHz, 5% UTY CYCLE, t 6.ns, Z O =5Ω. 2 C L CLUES POE N STY CPCITNCE. Figure 9. river Enable and isable Times (tpzl, tpsl, tplz) GENETO 1 5Ω VCC C L L = 6Ω C L = 15pF 2 1 PP = 25kHz, 5% UTY CYCLE, t 6.ns, Z O =5Ω. 2 C L CLUES POE N STY CPCITNCE. Figure 6. river ifferential Output elay and Transition Times GENETO 1 1.5V 5Ω V I = 2 1 PP = 25kHz, 5% UTY CYCLE, t 6.ns, Z O =5Ω. 2 C L CLUES POE N STY CPCITNCE. Figure 1. eceiver Propagation elay C L = 15pF GENETO 1 5Ω S1 L =27Ω C L = 15pF V S3 1kΩ 1.5V V I C 2 L GENETO 1 5Ω S1 S2 = V OH +V OL 1.5V 2 1 PP = 25kHz, 5% UTY CYCLE, t 6.ns, Z O =5Ω. 2 C L CLUES POE N STY CPCITNCE PP = 25kHz, 5% UTY CYCLE, t 6.ns, Z O =5Ω. 2C L CLUES POE N STY CPCITNCE Figure 7. river Propagation elays Figure 11. eceiver Enable and isable Times ev. Page 7 of 12

8 SWITCHG CHCTEISTICS +3V 3V 1.5V 1.5V 1.5V 1.5V t t t PSL t PLZ 5% 1% +2V 9% 9% 5% 1% 2V t T t T Figure 12. river ifferential Output elay and Transition Times V V OL Figure 15. river Enable and isable Times (tpzl, tpsl, tplz) V 3V 1.5V 1.5V V 1.5V 1.5V t PLH t PHL t PLH t PHL V OH V OL t PHL t PLH Figure 13. river Propagation elays V OH V OL t PZH t PSH +1.5V Figure 16. eceiver Propagation elay +1.5V +3V V OH S1 OPEN S2 CLOSE S3 = +1.5V t PZL t PSL +1.5V +1.5V +3V S1 CLOSE S2 OPEN S3 = 1.5V 3V V OL t PZH 1.5V t PHZ 1.5V +1.5V t PHZ +3V S1 OPEN S2 CLOSE S3 = +1.5V +1.5V t PLZ +3V S1 CLOSE S2 OPEN S3 = 1.5V.25V V OH V V OH +.25V V OL Figure 14. river Enable and isable Times (tpzh, tpsh, tphz) Figure 17. eceiver Enable and isable Times ev. Page 8 of 12

9 TYPICL PEFOMNCE CHCTEISTICS 3.8 PUT CUENT (m) PUT VOLTGE (V) PUT VOLTGE (V) TEMPETUE ( C) Figure 18. Output Current vs. eceiver Output Low Voltage Figure 21. eceiver Output Low Voltage vs. Temperature, IO = 2.5 m PUT CUENT (m) PUT CUENT (m) PUT VOLTGE (V) PUT VOLTGE (V) Figure 19. Output Current vs. eceiver Output High Voltage Figure 22. river Output Current vs. ifferential Output Voltage PUT VOLTGE (V) PUT VOLTGE (V) TEMPETUE ( C) TEMPETUE ( C) Figure 2. eceiver Output High Voltage vs. Temperature, IO = 1.5 m Figure 23. river ifferential Output Voltage vs. Temperature, I = 54 Ω ev. Page 9 of 12

10 PUT CUENT (m) SUPPLY CUENT (m) E = E = X* PUT VOLTGE (V) E = E = GN *X = ON T CE TEMPETUE ( C) Figure 24. Output Current vs. river Output Low Voltage Figure 26. Supply Current vs. Temperature PUT CUENT (m) SHUTOWN CUENT (n) PUT VOLTGE (V) TEMPETUE ( C) Figure 25. Output Current vs. river Output High Voltage Figure 27. Shutdown Current vs. Temperature, VCC = 3.3 V ev. Page 1 of 12

11 CICUIT ESCIPTION The M3493 is a low power transceiver for S-485 and S-422 communications. The M3493 can transmit and receive at data rates up to 25 kbps in a half duplex configuration. river Enable (E) and eceiver Enable (E) pins are included when disabled; the driver and receiver outputs are high impedance. Table 5. Transmitting Truth Table Transmitting Inputs Transmitting Outputs Mode E E I X Normal X Normal X 1 High-Z 2 High-Z 2 Normal 1 X 1 High-Z 2 High-Z 2 Shutdown 1 X = on t care. 2 High-Z = High Impedance. Table 6. eceiving Truth Table eceiving Inputs eceiving Outputs Mode E E - O +.2 V 1 Normal.2 V Normal Inputs Open 1 Normal 1 X 1 High-Z 2 Shutdown 1 X = on t care. 2 High-Z = High Impedance EUCE EMI N EFLECTIONS The M3493 is a slew rate limited transceiver, minimizing EMI and reducing reflections caused by improperly terminated cables. LOW POWE SHUTOWN MOE low power shutdown mode is initiated by bringing both E high and E low. The M3493 does not shut down unless both the driver and receiver are disabled (high impedance). In shutdown, the M3493 typically draws only 2 n of supply current. For the M3493, the tpsh and tpsl enable times assume the part was in the low power shutdown mode; the tpzh and tpzl enable times assume the receiver or driver was disabled, but the part was not shut down. IVE PUT POTECTION Two methods are implemented to prevent excessive output current and power dissipation caused by faults or by bus contention. Current limit protection on the output stage provides immediate protection against short circuits over the whole common-mode voltage range (see Typical Performance Characteristics). In addition, a thermal shutdown circuit forces the driver outputs into a high impedance state if the die temperature rises excessively. POPGTION ELY Skew time is simply the difference between the low-to-high and high-to-low propagation delay. Small driver/receiver skew times help maintain a symmetrical mark-space ratio (5% duty cycle). The receiver skew time, tplh - tphl, is 2 ns for the M3493. The driver skew time is typically under 1 ns. TYPICL PPLICTIONS The M3493 transceiver is designed for bidirectional data communications on multipoint bus transmission lines. Figure 22 shows a typical network application s circuits. To minimize reflections, the line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possible. The slew rate limited M3493 is tolerant of imperfect termination. M3493 MXIMUM NUME OF TNSCEIVES ON US = 256 M3493 O 1 O E E T T E E I 2 I M3493 M3493 O E E I O E E I NOTES 1. T IS EQUL TO THE CHCTEISTIC IMPENCE OF THE CLE Figure 28. M3493 Typical Half uplex S-485 Network ev. Page 11 of 12

12 LE IMENSIONS 5. (.1968) 4.8 (.189) 4. (.1574) 3.8 (.1497) (.244) 5.8 (.2284).25 (.98).1 (.4) COPLNITY (.5) SC SETG PLNE 1.75 (.688) 1.35 (.532).51 (.21).31 (.122).25 (.98).17 (.67) 8.5 (.196).25 (.99) (.5).4 (.157) COMPLINT TO JEEC STNS MS-12- CONTOLLG IMENSIONS E MILLIMETES; CH IMENSIONS ( PENTHESES) E OUNE-OFF MILLIMETE EQUIVLENTS FO EFEENCE ONLY N E NOT PPOPITE FO USE ESIGN Figure Lead Standard Small Outline Package [SOIC_N] Narrow ody (-8) imensions shown in millimeters and (inches) OEG GUIE Model Temperature ange Package escription Package Options Ordering Quantity M3493Z 1 4 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] -8 M3493Z-EEL7 1 4 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] -8 1, 1 Z = Pb-free part. 25 nalog evices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners /5() ev. Page 12 of 12