5 V Slew-Rate Limited Half- and Full-Duplex RS-485/RS-422 Transceivers ADM4850 ADM4857

Transcription

1 5 V Slew-ate Limited Half- and Full-Duplex S-485/S-422 Transceivers DM4850 DM4857 FETUES EI S-485-/S-422-compliant Data rate options DM4850/DM kbps DM4851/DM kbps DM4852/DM Mbps DM4853/DM Mbps Half- and full-duplex options educed slew rates for low EMI True fail-safe receiver inputs 5 µ (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-z when disabled or powered off 7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with MX308x Specified over the 40 C to +85 C temperature range vailable in 8-lead SOIC and LFCSP packages PPLICTIONS Low power S-485 applications EMI-sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators GENEL DESCIPTION The DM4850 DM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EI Standards S-485 and S-422. The DM4850 DM4853 are half-duplex transceivers, which share differential lines and have separate enable inputs for the driver and receiver. The full-duplex DM4854 DM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The parts have a 1/8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ends. ev. 0 Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective owners. O E DE DI FUNCTIONL LOCK DIGM D V CC DM4850/DM4851/ DM4852/DM4853 GND One Technology Way, P.O. ox 9106, Norwood, M , U.S.. Tel: Fax: nalog Devices, Inc. ll rights reserved. O DI Figure 1. D V CC DM4854/DM4855/ DM4856/DM4857 GND The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The parts are fully specified over the commercial and industrial temperature ranges, and are available in 8-lead SOIC and LFCSP packages. Table 1. Selection Table Part No Half-/Full-Duplex Data ate DM4850 Half 115 kbps DM4851 Half 500 kbps DM4852 Half 2.5 Mbps DM4853 Half 10 Mbps DM4854 Full 115 kbp DM4855 Full 500 kbps DM4856 Full 2.5 Mbps DM4857 Full 10 Mbps Z Y

2 TLE OF CONTENTS Specifications... 3 DM4850/DM4854 Timing Specifications... 4 DM4851/DM4855 Timing Specifications... 4 DM4852/DM4856 Timing Specifications... 5 DM4853/DM4857 Timing Specifications... 5 bsolute Maximum atings... 6 ESD Caution... 6 Pin Configurations and Function Descriptions... 7 Test Circuits... 8 Switching Characteristics... 9 Typical Performance Characteristics Circuit Description Slew-ate Control eceiver Input Filtering Half-/Full-Duplex Operation High eceiver Input Impedance Three-State us Connection Shutdown Mode Fail-Safe Operation Current Limit and Thermal Shutdown Outline Dimensions Ordering Guide EVISION HISTOY 10/04 evision 0: Initial Version ev. 0 Page 2 of 16

3 SPECIFICTIONS V = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. DM4850 DM4857 Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Differential Output Voltage, VOD VCC V =, Figure V = 50 Ω (S-422), Figure V = 27 Ω (S-485), Figure V VTST = 7 V to 12 V, Figure 5 VOD for Complementary Output States 0.2 V = 27 Ω or 50 Ω, Figure 4 Common-Mode Output Voltage, VO 3 V = 27 Ω or 50 Ω, Figure 4 VO for Complementary Output States 0.2 V = 27 Ω or 50 Ω, Figure 4 Output Short-Circuit Current, VOUT = High m 7 V < VOUT < +12 V Output Short-Circuit Current, VOUT = Low m 7 V < VOUT < +12 V DIVE INPUT LOGIC CMOS Input Logic Threshold Low V CMOS Input Logic Threshold High V CMOS Logic Input Current (DI) ±1 µ DE Input esistance to GND 220 kω ECEIVE Differential Input Threshold Voltage, VTH mv 7 V < VM < +12 V Input Hysteresis 20 mv 7 V < VM < +12 V Input esistance (, ) kω 7 V < VM < +12 V Input Current (, ) m VIN = +12 V 0.1 m VIN = 7 V CMOS Logic Input Current (E) ±1 µ CMOS Output Voltage Low 0.4 V IOUT = +4 m CMOS Output Voltage High 4.0 V IOUT = 4 m Output Short Circuit Current 7 85 m VOUT = GND or VCC Three-State Output Leakage Current ±2 µ 0.4 V VOUT 2.4 V POWE SUPPLY CUENT I (115 kbps Options) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V µ DE = VCC I (500 kbps Options) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V µ DE = VCC I (2.5 Mbps Options) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V µ DE = VCC I (10 Mbps Options) 5 µ DE = 0 V, E = VCC (shutdown) µ DE = 0 V, E = 0 V µ DE = VCC 1 Guaranteed by design. ev. 0 Page 3 of 16

4 DM4850/DM4854 TIMING SPECIFICTIONS V = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 115 kbps Propagation Delay tplh, tphl ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Skew tskew 70 ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 ise/fall Time t, tf ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Enable Time 2000 ns L = 500 Ω, CL = 100 pf, Figure 7, DM4850 Disable Time 2000 ns L = 500 Ω, CL = 15 pf, Figure 7, DM4850 Enable Time from Shutdown 4000 ns L = 500 Ω, CL = 100 pf, Figure 7, DM4850 ECEIVE Propagation Delay tplh, tph ns CL = 15 pf, Figure 8 Differential Skew tskew 255 ns CL = 15 pf, Figure 8 Enable Time 5 50 ns L = 1 kω, CL = 15 pf, Figure 9, DM4850 Disable Time ns L = 1 kω, CL = 15 pf, Figure 9, DM4850 Enable Time from Shutdown 4000 ns L = 1 kω, CL = 15 pf, Figure 9, DM4850 Time to Shut Down ns DM The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. DM4851/DM4855 TIMING SPECIFICTIONS V = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 500 kbps Propagation Delay tplh, tphl ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Skew tskew 40 ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 ise/fall Time t, tf ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Enable Time 1000 ns L = 500 Ω, CL = 100 pf, Figure 7, DM4851 Disable Time 1000 ns L = 500 Ω, CL = 15 pf, Figure 7, DM4851 Enable Time from Shutdown 4000 ns L = 500 Ω, CL = 100 pf, Figure 7, DM4851 ECEIVE Propagation Delay tplh, tphl ns CL = 15 pf, Figure 8 Differential Skew tskew 250 ns CL = 15 pf, Figure 8 Enable Time 5 50 ns L = 1 kω, CL = 15 pf, Figure 9, DM4851 Disable Time ns L =1 kω, CL = 15 pf, Figure 9, DM4851 Enable Time from Shutdown 4000 ns L =1 kω, CL = 15 pf, Figure 9, DM4851 Time to Shut Down ns DM The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ev. 0 Page 4 of 16

5 DM4852/DM4856 TIMING SPECIFICTIONS V = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 5. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 2.5 Mbps Propagation Delay tplh, tphl ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Skew tskew 50 ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 ise/fall Time t, tf 140 ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Enable Time 180 ns L = 500 Ω, CL = 100 pf, Figure 7, DM4852 Disable Time 180 ns L = 500 Ω, CL = 15 pf, Figure 7, DM4852 Enable Time from Shutdown 4000 ns L =500 Ω, CL = 100 pf, Figure 7, DM4852 ECEIVE Propagation Delay tplh, tphl ns CL = 15 pf, Figure 8 Differential Skew tskew 50 ns CL = 15 pf, Figure 8 Enable Time 5 50 ns L = 1 kω, CL = 15 pf, Figure 9, DM4852 Disable Time ns L = 1 kω, CL = 15 pf, Figure 9, DM4852 Enable Time from Shutdown 4000 ns L = 1 kω, CL = 15 pf, Figure 9, DM4852 Time to Shut Down ns DM The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. DM4853/DM4857 TIMING SPECIFICTIONS V = 5 V ± 5%, T = TMIN to TMX, unless otherwise noted. Table 6. Parameter Min Typ Max Unit Test Conditions/Comments DIVE Maximum Data ate 10 Mbps Propagation Delay tplh, tphl 0 30 ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Skew tskew 10 ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 ise/fall Time t, tf 30 ns LDIFF = 54 Ω, CL1 = CL2 = 100 pf, Figure 6 Enable Time 35 ns L = 500 Ω, CL = 100 pf, Figure 7, DM4853 Disable Time 35 ns L = 500 Ω, CL = 15 pf, Figure 7, DM4853 Enable Time from Shutdown 4000 ns L = 500 Ω, CL = 100 pf, Figure 7, DM4853 ECEIVE Propagation Delay tplh, tphl ns CL = 15 pf, Figure 8 Differential Skew tskew 30 ns CL = 15 pf, Figure 8 Enable Time 5 50 ns L = 1 kω, CL = 15 pf, Figure 9, DM4853 Disable Time ns L = 1 kω, CL = 15 pf, Figure 9, DM4853 Enable Time from Shutdown 4000 ns L = 1 kω, CL = 15 pf, Figure 9, DM4853 Time to Shut Down ns DM The half-duplex device is put into shutdown mode by driving E high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ev. 0 Page 5 of 16

6 SOLUTE MXIMUM TINGS Table 7. Parameter ating VCC to GND 6 V Digital I/O Voltage (DE, E, DI, OUT) 0.3 V to VCC V Driver Output/eceiver Input Voltage 9 V to +14 V Operating Temperature ange 40 C to +85 C Storage Temperature ange 65 C to +125 C θj Thermal Impedance SOIC 110 C/W LFCSP 62 C/W Lead Temperature Soldering (10 s) 300 C Vapour Phase (60 s) 215 C Infrared (15 s) 220 C Stresses above those listed under bsolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. lthough this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ev. 0 Page 6 of 16

7 PIN CONFIGUTIONS ND FUNCTION DESCIPTIONS DM4850/ DM4851/ DM4852/ DM4853 O 1 8 V CC E 2 7 DE 3 6 TOP VIEW DI 4 (Not to Scale) 5 GND Figure 2. DM4850 DM4853 Pin Configuration Table 8. DM4850 DM4853 Pin Descriptions Pin No. Mnemonic Description 1 O eceiver Output. When enabled, if ( ) 30 mv, then O = high. If ( ) 200 mv, then O = low. 2 E eceiver Output Enable. low level enables the receiver output, O. high level places it in a high impedance state. 3 DE Driver Output Enable. high level enables the driver differential inputs and. low level places it in a high impedance state. 4 DI Driver Input. When the driver is enabled, a logic low on DI forces low and high, while a logic high on DI forces high and low. 5 GND Ground. 6 Noninverting eceiver Input /Driver Output. 7 Inverting eceiver Input /Driver Output. 8 VCC 5 V Power Supply. DM4854/ DM4855/ DM4856/ DM4857 V CC 1 8 O 2 7 DI 3 6 Z TOP VIEW GND 4 (Not to Scale) 5 Y Figure 3. DM4854 DM4857 Pin Configuration Table 9. DM4854 DM4857 Pin Descriptions Pin No. Mnemonic Description 1 VCC 5 V Power Supply. 2 O eceiver Output. When enabled, if ( ) 30 mv, then O = high. If ( ) 200 mv, then O = low. 3 DI Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, while a logic high on DI forces Y high and Z low. 4 GND Ground. 5 Y Driver Noninverting Output. 6 Z Driver Inverting Output. 7 eceiver Inverting Input. 8 eceiver Noninverting Input. ev. 0 Page 7 of 16

8 TEST CICUITS V CC V OD V OC V O 3V DE IN DE S1 C L L V OUT S Figure 4. Driver Voltage Measurement Figure 7. Driver Enable/Disable 375Ω V OD3 60Ω 375Ω V TST E C L V OUT Figure 5. Driver Voltage Measurement over Common-Mode Voltage ange Figure 8. eceiver Propagation Delay LDIFF C L1 C L V 1.5V E IN S1 E C L L V OUT V CC S Figure 6. Driver Propagation Delay Figure 9. eceiver Enable/Disable ev. 0 Page 8 of 16

9 SWITCHING CHCTEISTICS 3V 3V 1.5V 1.5V DE 1.5V 1.5V 0V t PLH t PHL t ZL t LZ 0V 1/2VO VO t SKEW = t PLH t PHL 5V 90% POINT 10% POINT 0V t t F 90% POINT Figure 10. Driver Propagation Delay, ise/fall Timing 10% POINT ,, 2.3V V OL +0.5V t ZH t HZ V OH 0.5V 2.3V Figure 12. Driver Enable/Disable Timing V OL V OH 0V V E 1.5V 1.5V, 0V 0V t ZL t LZ 0V t PLH t PHL 1.5V O/P LOW V OL +0.5V V OL O 1.5V 1.5V t SKEW = t PLH t PHL V OH V OL V t ZH 1.5V O/P HIGH t HZ V OH 0.5V V OH Figure 11. eceiver Propagation Delay Figure 13. eceiver Enable/Disable Timing ev. 0 Page 9 of 16

10 TYPICL PEFOMNCE CHCTEISTICS UNLODED SUPPLY CUENT (µ) 400 DM4853: DE = V CC DM4853: DE = GND DM4850: DE = V CC DM4850: DE = GND TEMPETUE ( C) Figure 14. Unloaded Supply Current vs. Temperature OUTPUT LOW VOLTGE (V) TEMPETUE ( C) Figure 17. eceiver Output Low Voltage vs. Temperature ECEIVE OUTPUT CUENT (m) ECEIVE OUTPUT LOW VOLTGE (V) Figure 15. Output Current vs. eceiver Output Low Voltage OUTPUT HIGH VOLTGE (V) TEMPETUE ( C) Figure 18. eceiver Output High Voltage Temperature ECEIVE OUTPUT CUENT (m) ECEIVE OUTPUT HIGH VOLTGE (V) Figure 16. Output Current vs. eceiver Output High Voltage DIVE OUTPUT CUENT (m) DIFFEENTIL OUTPUT VOLTGE (V) Figure 19. Driver Output Current vs. Differential Output Voltage ev. 0 Page 10 of 16

11 DM4855 OUTPUT CUENT (m) OUTPUT VOLTGE (V) Figure 20. Output Current vs. Driver Low Voltage POPGTION DELY (ns) DM TEMPETUE ( C) Figure 23. eceiver Propagation Delay vs. Temperature OUTPUT CUENT (m) OUTPUT VOLTGE (V) Figure 21. Output Current vs. Driver Output High Voltage CH1 1.00VΩ W CH2 1.00VΩ W M400ns CH3 2.00V CH3 2.00VΩ W CH4 5.00VΩ Figure 24. Driver/eceiver Propagation Delay (DM4855, 500 kbps) POPGTION DELY (ns) 350 DM DM TEMPETUE ( C) Figure 22. Driver Propagation Delay vs. Temperature CH1 2.00VΩ W CH2 1.00VΩ M 50.0ns CH1 480mV CH3 1.00VΩ W CH4 5.00VΩ Figure 25. Driver/ eceiver Propagation Delay (DM4855, 4 Mbps) ev. 0 Page 11 of 16

12 CICUIT DESCIPTION The DM4850 DM4857 are high speed S-485/S-422 transceivers offering enhanced performance over industrystandard devices. ll devices in the family contain one driver and one receiver, but offer a choice of performance options. The devices feature true fail-safe operation, which means that a logic high receiver output is guaranteed when the receiver inputs are open-circuit or short-circuit, or when they are connected to a terminated transmission line with all drivers disabled (see the Fail-Safe Operation section). SLEW-TE CONTOL The DM4850/DM4854 feature a controlled slew-rate driver that minimizes electromagnetic interference (EMI) and reduces reflections caused by incorrectly terminated cables, allowing error-free data transmission rates up to 115 kbps. The DM4851/ DM4855 offer a higher limit on driver output slew rate, allowing data transmission rates up to 500 kbps. The driver slew rates of the DM4852/DM4856 and the DM4853/DM4857 are not limited, offering data transmission rates up to 2.5 Mbps and 10 Mbps, respectively. ECEIVE INPUT FILTEING The receivers of all the devices incorporate input hysteresis. In addition, the receivers of the 115 kbps DM4850/DM485 and the 500 kbps DM4851/DM4855 incorporate input filtering. This enhances noise immunity with differential signals that have very slow rise and fall times. However, it causes the propagation delay to increase by 20%. HLF-/FULL-DUPLEX OPETION Half-duplex operation implies that the transceiver can transmit and receive, but it can only do one of these at any given time. However, with full-duplex operation, the transceiver can transmit and receive simultaneously. The DM4850 DM4853 are half-duplex devices in which the driver and receiver share differential bus terminals. The DM4854 DM4857 are fullduplex devices, which have dedicated driver output and receiver input pins. Figure 26 and Figure 27 show typical half- and fullduplex topologies. DM4850/DM4851/ DM4852/DM4853 DM4850/DM4851/ DM4852/DM4853 O O E E DE DE DI D D DI DM4850/DM4851/ DM4852/DM4853 D DM4850/DM4851/ DM4852/DM4853 D O E DE DI O E DE DI MXIMUM NUME OF TNSCEIVES ON US: Figure 26. Typical Half-Duplex S-485 Network Topology V DD V DD DM4854/DM4855/ DM4856/DM4857 Z DM4854/DM4855/ DM4856/DM4857 O D DI Z Y DI D O GND Y GND Figure 27. Typical Full-Duplex Point-to-Point S-485 Network Topology ev. 0 Page 12 of 16

13 HIGH ECEIVE INPUT IMPEDNCE The input impedance of the DM485x receivers is 96 kω, which is 8 times higher than the standard S-485 unit load of 12 kω. This 96 kω impedance, enables a standard driver to drive 32 unit loads or be connected to 256 DM485x receivers. n S-485 bus, driven by a single standard driver, can be connected to a combination of DM485x and standard unit load receivers, up to an equivalent of 32 standard unit loads. THEE-STTE US CONNECTION The half-duplex parts have a driver enable (DE) pin that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. Similarly, the halfduplex devices have an active-low receiver enable (E) pin. Taking this pin low enables the receiver, while taking it high puts the receiver outputs into a high impedance state. This allows several driver outputs to be connected to an S-485 bus. Note that only one driver should be enabled at a time, while many receivers can be enabled. SHUTDOWN MODE The DM4850 DM4853 have a low power shutdown mode, which is enabled by taking E high and DE low. If shutdown mode is not used, the fact that DE is active high and E is active low offers a convenient way of switching the device between transmit and receive by tying DE and E together. FIL-SFE OPETION The DM4850 DM4857 offer true fail-safe operation while remaining fully compliant with the ±200 mv EI/TI-485 standard. logic-high receiver output is generated when the receiver inputs are shorted together or open-circuit, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between 30 mv and 200 mv. If the differential receiver input voltage (-) is greater than or equal to 30 mv, O is logic high. If - is less than or equal to 200 mv, O is logic low. In the case of a terminated bus with all transmitters disabled, the receiver s differential input voltage is pulled to 0 V by the DM485x s internal circuitry, which results in a logic high with 30 mv minimum noise margin. CUENT LIMIT ND THEML SHUTDOWN The DM485x incorporates two protection mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current-limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 m. Under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 150 C, and does not turn them back on until the temperature falls to 130 C. The devices are guaranteed not to enter shutdown mode if DE and E are driven in this way. If DE is low and E is high for less than 50 ns, the device does not enter shutdown mode. If DE is low and E is high for less than 3000 ns, the device is guaranteed to enter shutdown mode. ev. 0 Page 13 of 16

14 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 0.25 (0.0098) 0.10 (0.0040) COPLNITY SETING PLNE (0.0500) SC 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.25 (0.0098) 0.17 (0.0067) (0.0196) 0.25 (0.0099) (0.0500) 0.40 (0.0157) COMPLINT TO JEDEC STNDDS MS-012 CONTOLLING DIMENSIONS E IN MILLIMETES; INCH DIMENSIONS (IN PENTHESES) E OUNDED-OFF MILLIMETE EQUIVLENTS FO EFEENCE ONLY ND E NOT PPOPITE FO USE IN DESIGN Figure Lead Standard Small Outline Package [SOIC] Narrow ody (-8) Dimensions shown in millimeters and (inches) PIN 1 INDICTO SETING PLNE 12 MX 3.00 SC SQ TOP VIEW MX 0.65TYP 2.75 SC SQ 0.20 EF MX 0.02 NOM 0.50 SC MX 0.30 PIN 1 INDICTO 0.25 MIN EXPOSED PD (OTTOM VIEW) EF Figure Lead Lead Frame Chip Scale Package [LFCSP] (CP-8-2) Dimensions shown in millimeters ev. 0 Page 14 of 16

15 ODEING GUIDE Model Temperature ange Package Description Package Type randing DM4850CP-EEL 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0 DM4850CP-EEL7 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0 DM C to +85 C 8-Lead Standard Small Outline Package -8 DM4850-EEL 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4850-EEL7 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4851CP-EEL 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0S DM4851CP-EEL7 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0S DM C to +85 C 8-Lead Standard Small Outline Package -8 DM4851-EEL 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4851-EEL7 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4852CP-EEL 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0T DM4852CP-EEL7 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0T DM C to +85 C 8-Lead Standard Small Outline Package -8 DM4852-EEL 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4852-EEL7 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4853CP-EEL 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0U DM4853CP-EEL7 40 C to +85 C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0U DM C to +85 C 8-Lead Standard Small Outline Package -8 DM4853-EEL 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4853-EEL7 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM C to +85 C 8-Lead Standard Small Outline Package -8 DM C to +85 C 8-Lead Standard Small Outline Package -8 DM4855-EEL 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4855-EEL7 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM C to +85 C 8-Lead Standard Small Outline Package -8 DM4856-EEL 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4856-EEL7 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM C to +85 C 8-Lead Standard Small Outline Package -8 DM4857-EEL 40 C to +85 C 8-Lead Standard Small Outline Package -8 DM4857-EEL7 40 C to +85 C 8-Lead Standard Small Outline Package -8 ev. 0 Page 15 of 16

16 NOTES 2004 nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /04(0) ev. 0 Page 16 of 16