2.7 V to 5.5 V, Serial-Input, Voltage-Output, 12-/16-Bit DAC AD5512A/AD5542A

Transcription

1 .7 V to 5.5 V, Serial-Input, Voltage-Output, -/6-Bit DAC AD55A/AD554A FEATURES -/6-bit resolution LSB INL.8 nv/ Hz noise spectral density µs settling time. nv-sec glitch energy.5 ppm/ C temperature drift 5 kv HBM ESD classification.375 mw power consumption at 3 V.7 V to 5.5 V single-supply operation Hardware CLR and LDAC functions 5 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface Power-on reset clears DAC output to midscale Available in 3 mm 3 mm, -/6-lead LFP and 6-lead TSSOP APPLICATIONS Automatic test equipment Precision source-measure instruments Data acquisition systems Medical and aerospace instrumentation Communication equipment GENERAL DESCRIPTION The AD55A/AD554A are single, -/6-bit, serial input, unbuffered voltage output digital-to-analog converters (DAC) that operate from a single.7 V to 5.5 V supply. The DAC output range extends from V to VREF and is guaranteed monotonic, providing LSB INL accuracy at 6 bits without adjustment over the full specified temperature range of 4 C to +85 C (AD554A) or 4 C to +5 C (AD55A). Offering unbuffered outputs, the AD55A/AD554A achieve a μs settling time with low offset errors ideal for high speed open loop control. The AD55A/AD554A incorporate a bipolar mode of operation that generates a ±VREF output swing. The AD55A/AD554A also include Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. The AD55A/AD554A are available in a 6-lead LFP with the AD554A also available in a -lead LFP and a 6-lead TSSOP. The AD55A/AD554A use a versatile 3-wire interface that is compatible with 5 MHz SPI, QSPI, MICROWIRE, and DSP interface standards. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. REFF REFS V LOGIC LDAC REF CLR FUNCTIONAL BLOCK DIAGRAM CONTROL LOGIC CLR R INV V DD 6-BIT DAC 6-BIT DAC LATCH DGND AD55A/ AD554A V OUT One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved. R FB SERIAL INPUT REGISTER Figure. 6-Lead TSSOP and 6-Lead LFP AD554A- CONTROL LOGIC R INV GND 9 6-BIT DAC 6-BIT DAC LATCH SERIAL INPUT REGISITER V DD Figure. -Lead LFP R FB 6 R FB INV AGNDF AGNDS 7 INV R FB V OUT Table. Related Devices Part No. Description AD54/AD56.7 V to 5.5 V 4-/6-bit buffed output DACs AD554/AD554.7 V to 5.5 V 6-bit voltage output DACs AD578/AD579 8-/-bit voltage output DACs AD557 6-bit ± V/±5 V bipolar output DAC AD54/AD V to 5.5 V, -/6-bit quad channel DAC AD bit, bipolar, voltage output DAC PRODUCT HIGHLIGHTS. 6-bit performance without adjustment...7 V to 5.5 V single supply operation. 3. Low.8 nv/ Hz noise spectral density. 4. Low.5 ppm/ C temperature drift mm 3 mm LFP and TSSOP packaging. 999-

2 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Product Highlights... Revision History... Specifications... 3 AD55A... 3 AD554A... 4 AC Characteristics... 5 Timing Characteristics... 6 Absolute Maximum Ratings... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 Typical Performance Characteristics... Terminology... 4 Theory of Operation... 5 Digital-to-Analog Section... 5 Serial Interface... 5 Unipolar Output Operation... 5 Bipolar Output Operation... 6 Output Amplifier Selection... 7 Force Sense Amplifier Selection... 7 Reference and Ground... 7 Power-On Reset... 7 Power Supply and Reference Bypassing... 7 Applications Information... 8 Microprocessor Interfacing... 8 AD55A/AD554A to ADSP-BF53 Interface... 8 AD55A/AD554A to SPORT Interface... 8 AD55A/AD554A to 68HC/68L Interface... 8 AD55A/AD554A to ADSP- Interface... 8 AD55A/AD554A to MICROWIRE Interface... 8 Layout Guidelines... 9 Galvanically Isolated Interface... 9 Decoding Multiple DACs... 9 Outline Dimensions... Ordering Guide... REVISION HISTORY 5/ Rev. to Rev. A Changes to Table 3, Power Dissipation Value and Endnote... 4 Changes to Table Changes to Ordering Guide... / Revision : Initial Version Rev. A Page of 4

3 SPECIFICATIONS AD55A AD55A/AD554A V DD =.7 V to 5.5 V, V LOGIC =.7 V to 5.5 V, V REF =.5 V, AGND = DGND = V, 4 C < T A < +5 C, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution Bits Relative Accuracy (INL) ±.5 ±. LSB Differential Nonlinearity (DNL) ±.5 ±. LSB Guaranteed monotonic Gain Error +.5 ± LSB Gain Error Temperature Coefficient ±. ppm/ C Unipolar Zero-Code Error.3 ±.5 LSB Unipolar Zero-Code Temperature Coefficient ±.5 ppm/ C Bipolar Resistor Matching Ω/Ω R FB /R INV, typically R FB = R INV = 8 kω ±. ±.8 % Ratio error Bipolar Zero Offset Error ±.7 ± LSB Bipolar Zero Temperature Coefficient ±. ppm/ C Bipolar Zero-Code Offset Error ±. ±.5 LSB Bipolar Gain Error ±.7 ± LSB Bipolar Gain Temperature Coefficient ±. ppm/ C OUTPUT CHARACTERISTI Output Voltage Range V REF LSB V Unipolar operation V REF +V REF LSB V Bipolar operation DAC Output Impedance 6.5 kω Tolerance typically % Power Supply Rejection Ratio ±. LSB ΔV DD ± % Output Noise Spectral Density.8 nv/ Hz DAC code = x84 (AD55A) or x84 (AD554A), frequency = khz, unipolar mode Output Noise.34 μv p-p. Hz to Hz, unipolar mode DAC REFERENCE INPUT Reference Input Range. V DD V Reference Input Resistance 3 9 kω Unipolar operation 7.5 kω Bipolar operation Reference Input Capacitance 6 pf Code x 6 pf Code x3fff LOGIC INPUTS Input Current ± μa Input Low Voltage, V INL.8 V V DD =.7 V to 5.5 V Input High Voltage, V INH.4 V V DD =.7 V to 5.5 V Input Capacitance pf Hysteresis Voltage.5 V POWER REQUIREMENTS V DD V All digital inputs at V, V LOGIC, or V DD I DD 5 5 µa V IH = V LOGIC or V DD and V IL = GND V LOGIC V I LOGIC 5 4 µa All digital inputs at V, V LOGIC, or V DD Power Dissipation mw Temperatures are as follows: A version 4 C to +5 C. Guaranteed by design, not subject to production test. 3 Reference input resistance is code-dependent, minimum at x855. Rev. A Page 3 of 4

4 AD554A V DD =.7 V to 5.5 V, V LOGIC =.7 V to 5.5 V, V REF =.5 V, AGND = DGND = V, 4 C < T A < +85 C, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 6 Bits Relative Accuracy (INL) ±.5 ±. LSB B grade ±. A grade Differential Nonlinearity (DNL) ±.5 ±. LSB Guaranteed monotonic Gain Error +.5 ± LSB ±3 LSB Gain Error Temperature Coefficient ±. ppm/ C Unipolar Zero-Code Error.3 ±.7 LSB ±.5 LSB Unipolar Zero-Code Temperature Coefficient ±.5 ppm/ C Bipolar Resistor Matching. Ω/Ω R FB /R INV, typically R FB = R INV = 8 kω ±.5 ±.76 % Ratio error Bipolar Zero Offset Error ± ±5 LSB ±6 LSB Bipolar Zero Temperature Coefficient ±. ppm/ C Bipolar Zero-Code Offset Error ± ±5 LSB ±6 LSB Bipolar Gain Error ± ±5 LSB ±6 LSB Bipolar Gain Temperature Coefficient ±. ppm/ C OUTPUT CHARACTERISTI Output Voltage Range V REF LSB V Unipolar operation V REF +V REF LSB V Bipolar operation DAC Output Impedance 6.5 kω Tolerance typically % Power Supply Rejection Ratio ±. LSB ΔV DD ± % Output Noise Spectral Density.8 nv/ Hz DAC code = x84 (AD55A) or x84 (AD554A), frequency = khz, unipolar mode Output Noise.34 μv p-p. Hz to Hz DAC REFERENCE INPUT Reference Input Range. V DD V Reference Input Resistance 3 9 kω Unipolar operation 7.5 kω Bipolar operation Reference Input Capacitance 6 pf Code x 6 pf Code xffff LOGIC INPUTS Input Current ± μa Input Low Voltage, V INL.8 V V DD =.7 V to 5.5 V Input High Voltage, V INH.4 V V DD =.7 V to 5.5 V Input Capacitance pf Hysteresis Voltage.5 V POWER REQUIREMENTS V DD V All digital inputs at V, V LOGIC, or V DD I DD 5 5 µa V IH = V LOGIC or V DD and V IL = GND V LOGIC V I LOGIC 5 4 µa All digital inputs at V, V LOGIC, or V DD Power Dissipation mw For.7 V V LOGIC 5.5 V, temperatures are as follows: A, B versions 4 C to +85 C. Guaranteed by design, not subject to production test. 3 Reference input resistance is code-dependent, minimum at x8555. Rev. A Page 4 of 4

5 AC CHARACTERISTI AD55A/AD554A V DD =.7 V to 5.5 V, V LOGIC =.7 V to 5.5 V,.5 V V REF V DD, AGND = DGND = V, 4 C < T A < +5 C, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Test Condition Output Voltage Settling Time μs To / LSB of FS, C L = pf Slew Rate 7 V/µs C L = pf, measured from % to 63% Digital-to-Analog Glitch Impulse. nv-sec LSB change around major carry Reference 3 db Bandwidth. MHz All s loaded Reference Feedthrough mv p-p All s loaded, V REF = V p-p at khz Digital Feedthrough. nv-sec Signal-to-Noise Ratio 9 db Spurious Free Dynamic Range 8 db Digitally generated sine wave at khz Total Harmonic Distortion 74 db DAC code = x3fff (AD55A) or xffff (AD554A), frequency khz, V REF =.5 V ± V p-p Rev. A Page 5 of 4

6 TIMING CHARACTERISTI VDD = 5 V,.5 V VREF VDD, VINH = 9% of VLOGIC, VINL = % of VLOGIC, AGND = DGND = V, unless otherwise noted. Table 5. Parameter, Limit.8 VLOGIC.7 V 3 Limit.7 V VLOGIC 5.5 V 4 Unit Description f 4 5 MHz max cycle frequency t 7 ns min cycle time t 35 ns min high time t 3 35 ns min low time t ns min low to high setup t ns min high to high setup t ns min high to low hold time t 7 5 ns min high to high hold time t 8 35 ns min Data setup time t ns min Data hold time (VINH = 9% of VDD, VINL = % of VDD) t ns min Data hold time (VINH = 3 V, VINL = V) t ns min LDAC pulsewidth t ns min high to LDAC low setup t 5 5 ns min high time between active periods t ns CLR pulsewidth Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = ns/v and timed from a voltage level of (VINL + VINH)/. 3 4 C < TA < +5 C. 4 4 C < TA < +5 C. t t 6 t4 t t 3 t 7 t 5 t t8 t 9 DB5 DB t LDAC t CLR t 3 NOTES. FOR AD554A = DB5.. FOR AD55A = DB. Figure 3. Timing Diagram Rev. A Page 6 of 4

7 ABSOLUTE MAXIMUM RATINGS, unless otherwise noted. Table 6. Parameter Rating V DD to AGND.3 V to +6 V Digital Input Voltage to DGND.3 V to V DD +.3 V V OUT to AGND.3 V to V DD +.3 V AGNDF, AGNDS to DGND.3 V to +.3 V Input Current to Any Pin Except Supplies ± ma Operating Temperature Range AD55A Industrial (A Version) 4 C to +5 C AD554A Industrial (A, B Versions) 4 C to +85 C Storage Temperature Range 65 C to +5 C Maximum Junction Temperature (T J max) 5 C Package Power Dissipation (T J max T A )/θ JA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Thermal Impedance, θ JA TSSOP (RU-6) 3 C/W LFP (CP-6-) 73 C/W LFP (CP--9) 74 C/W Lead Temperature, Soldering Peak Temperature 6 C ESD 5 kv As per JEDEC Standard. HBM classification. Rev. A Page 7 of 4

8 REFF NC AD55A/AD554A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 6 R FB 5 V DD 4 V LOGIC 3 INV REF GND V OUT AGNDF AGNDS REFS 3 4 TOP VIEW DGND LDAC CLR 9 CLR AD554A- TOP VIEW Not to Scale 9 V DD 8 R FB 7 INV 6 V OUT NC = NO CONNECT (Not to Scale) Figure 4. AD55A/AD554A 6-Lead LFP Pin Configuration NOTES. THE EXPOSED PADDLE SHOULD BE TIED TO THE POINT OF LOWEST POTENTIAL, IN THIS CASE, GND. Figure 5. AD554A- -Lead LFP Pin Configuration Table 7. AD55A/AD554A Pin Function Descriptions Pin No. 6-Lead LFP -Lead LFP Mnemonic Description 6 V OUT Analog Output Voltage from the DAC. AGNDF Ground Reference Point for Analog Circuitry (Force). 3 AGNDS Ground Reference Point for Analog Circuitry (Sense). 4 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external.5 V reference. Reference can range from V to V DD. 5 REFF Voltage Reference Input (Force) for the DAC. Connect to an external.5 V reference. Reference can range from V to V DD. 6 Logic Input Signal. The chip select signal is used to frame the serial data input. 7 NC No Connect. 8 3 Clock Input. Data is clocked into the input register on the rising edge of. Duty cycle must be between 4% and 6%. 9 4 Serial Data Input. This device accepts 6-bit words. Data is clocked into the input register on the rising edge of. 5 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale. LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. DGND Digital Ground. Ground reference for digital circuitry. 3 7 INV Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting input in bipolar mode. 4 V LOGIC Logic Power Supply. 5 9 V DD Analog Supply Voltage, 5 V ± %. 6 8 R FB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. REF Voltage Reference Input for the DAC. Connect this pin to an external.5 V reference. Reference can range from V to V DD. GND Ground. EPAD Exposed Pad The exposed pad should be tied to the point of lowest potential, in this case, GND. Rev. A Page 8 of 4

9 R FB 6 V DD V OUT 5 V LOGIC AGNDF AGNDS REFS AD554A TOP VIEW (Not to Scale) 4 3 INV DGND LDAC REFF 6 CLR NC NC = NO CONNECT Figure 6. AD554A 6-Lead TSSOP Pin Configuration Table 8. AD554A Pin Function Descriptions Pin No. Mnemonic Description R FB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. V OUT Analog Output Voltage from the DAC. 3 AGNDF Ground Reference Point for Analog Circuitry (Force). 4 AGNDS Ground Reference Point for Analog Circuitry (Sense). 5 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external.5 V reference. Reference can range from V to V DD. 6 REFF Voltage Reference Input (Force) for the DAC. Connect to an external.5 V reference. Reference can range from V to V DD. 7 NC No Connect. 8 Logic Input Signal. The chip select signal is used to frame the serial data input. 9 Clock Input. Data is clocked into the input register on the rising edge of. Duty cycle must be between 4% and 6%. Serial Data Input. This device accepts 6-bit words. Data is clocked into the input register on the rising edge of. CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale. LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. 3 DGND Digital Ground. Ground reference for digital circuitry. 4 INV Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting input in bipolar mode. 5 V LOGIC Logic Power Supply. 6 V DD Analog Supply Voltage, 5 V ± %. Rev. A Page 9 of 4

10 TYPICAL PERFORMANCE CHARACTERISTI.5.5 INTEGRAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) ,384 4,576 3,768 4,96 49,5 57,344 65,536 CODE Figure 7. AD554A Integral Nonlinearity vs. Code ,384 4,576 3,768 4,96 49,5 57,344 65,536 CODE Figure. AD554A Differential Nonlinearity vs. Code INTEGRAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) TEMPERATURE ( C) Figure 8. AD554A Integral Nonlinearity vs. Temperature TEMPERATURE ( C) Figure. AD554A Differential Nonlinearity vs. Temperature LINEARITY ERROR (LSB).5 DNL LINEARITY ERROR (LSB).5 DNL INL.5.5 INL SUPPLY VOLTAGE (V) Figure 9. AD554A Linearity Error vs. Supply Voltage REFERENCE VOLTAGE (V) Figure. AD554A Linearity Error vs. Reference Voltage 999- Rev. A Page of 4

11 GAIN ERROR (LSB) ZERO-CODE ERROR (LSB) TEMPERATURE ( C) Figure 3. AD55A/AD554A Gain Error vs. Temperature TEMPERATURE ( C) Figure 6. AD55A/AD554A Zero-Code Error vs. Temperature SUPPLY CURRENT (µa) SUPPLY CURRENT (µa).5..5 REFERENCE VOLTAGE SUPPLY VOLTAGE TEMPERATURE ( C) Figure 4. AD55A/AD554A Supply Current vs. Temperature VOLTAGE (V) Figure 7. AD55A/AD554A Supply Current vs. Reference Voltage or Supply Voltage SUPPLY CURRENT (µa) REFERENCE CURRENT (µa) DIGITAL INPUT VOLTAGE (V) Figure 5. AD55A/AD554A Supply Current vs. Digital Input Voltage 999-4,, 3, 4, 5, 6, 7, CODE (Decimal) Figure 8. AD55A/AD554A Reference Current vs. Code Rev. A Page of 4

12 9 (5V/DIV) V OUT (V/DIV) 9 V OUT (5mV/DIV) V OUT (5mV/DIV) GAIN = 6 LSB = V REF /( N ) µs/div µs/DIV 999- Figure 9. AD55A/AD554A Digital Feedthrough Figure. AD55A/AD554A Small Signal Settling Time C +5 C 55 C VOLTAGE (V) V OUT HITS TIME (ns) Figure. AD55A/AD554A Digital-to-Analog Glitch Impulse I DD SUPPLY (µa) Figure 3. AD55A/AD554A Analog Supply Current Histogram µs/div pf (5V/DIV) C +5 C 55 C 5pF HITS 3 pf pf Figure. AD55A/AD554A Large Signal Settling Time V OUT (.5V/DIV) I LOGIC AT RAILS (µa) Figure 4. AD55A/AD554A Digital Supply Current Histogram Rev. A Page of 4

13 OUTPUT NOISE (µv rms) 5 DATA = x V OUT (dbm) V REF = 5V FREQUENCY (Hz) Figure 5. AD55A/AD554A. Hz to Hz Output Noise ,, 3, 4, 5, 6, 7, FREQUENCY (Hz) Figure 8. AD55A/AD554A Total Harmonic Distortion NOISE SPECTRAL DENSITY (nv rms/ Hz) V OUT /V REF (dbm) ±.V FREQUENCY (Hz) Figure 6. AD55A/AD554A Noise Spectral Density vs. Frequency, khz k k k M M M FREQUENCY (Hz) Figure 9. AD55A/AD554A Multiplying Bandwidth NOISE SPECTRAL DENSITY (nv rms/ Hz) ,,,,3,4 FREQUENCY (Hz) Figure 7. AD55A/AD554A Noise Spectral Density vs. Frequency, khz Rev. A Page 3 of 4

14 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 7. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal LSB change between any two adjacent codes. A specified differential nonlinearity of ± LSB maximum ensures monotonicity. A typical DNL vs. code plot is shown in Figure. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/ C. Zero-Code Error Zero-code error is a measure of the output error when zero code is loaded to the DAC register. Zero-Code Temperature Coefficient This is a measure of the change in zero-code error with a change in temperature. It is expressed in mv/ C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nv-sec and is measured when the digital input code is changed by LSB at the major carry transition. A digital-to-analog glitch impulse plot is shown in Figure. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. is held high while the and signals are toggled. It is specified in nv-sec and is measured with a full-scale code change on the data bus, that is, from all s to all s and vice versa. A typical digital feedthrough plot is shown in Figure 9. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. The power supply rejection ratio is quoted in terms of percent change in output per percent change in V DD for full-scale output of the DAC. V DD is varied by ±%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the V REF input to the DAC output when the DAC is loaded with all s. A khz, V p-p is applied to V REF. Reference feedthrough is expressed in mv p-p. Rev. A Page 4 of 4

15 THEORY OF OPERATION The AD55A/AD554A are single, -/6-bit, serial input, voltage output DACs. They operate from a single supply ranging from.7 V to 5 V and consume typically 5 µa with a supply of 5 V. Data is written to these devices in a -bit (AD55A) or 6-bit (AD554A) word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, these parts are designed with a power-on reset function. In unipolar mode, the output is reset to midscale; in bipolar mode, the output is set to V. Kelvin sense connections for the reference and analog ground are included on the AD55A/ AD554A. DIGITAL-TO-ANALOG SECTION The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 3. The DAC architecture of the AD55A/AD554A is segmented. The four MSBs of the 6-bit (AD554A)/-bit (AD55A) data-word are decoded to drive 5 switches, E to E5. Each switch connects one of 5 matched resistors to either AGND or V REF. The remaining bits of the data-word drive the S to S switches of a -bit voltage mode R-R ladder network. V REF R R S R R..... S BIT R-R LADDER R S R R E Figure 3. DAC Architecture R..... E..... R E5 FOUR MSBs DECODED INTO 5 EQUAL SEGMENTS V OUT With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage, as shown in the following equation: VREF D VOUT = N where: D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. For a reference of.5 V, the equation simplifies to the following:.5 D V OUT = 65,536 This gives a V OUT of.5 V with midscale loaded, and.5 V with full scale loaded to the DAC. The LSB size is V REF /65, SERIAL INTERFACE The AD55A/AD554A are controlled by a versatile 3- or 4- wire serial interface that operates at clock rates of up to 5 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram is shown in Figure 3. Input data is framed by the chip select input,. After a highto-low transition on, data is shifted synchronously and latched into the input register on the rising edge of the serial clock,. Data is loaded MSB first in -bit (AD55A) or 6-bit (AD554A) words. After (AD55A) or 6 (AD554A) data bits have been loaded into the serial input register, a low-to-high transition on transfers the contents of the shift register to the DAC. Data can be loaded to the part only while is low. The AD55A/AD554A have an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC can be tied permanently low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of loads the data to the DAC. UNIPOLAR OUTPUT OPERATION These DACs are capable of driving unbuffered loads of 6 kω. Unbuffered operation results in low supply current, typically 3 μa, and a low offset error. The AD55A/AD554A provide a unipolar output swing ranging from V to V REF. The AD55A/AD554A can be configured to output both unipolar and bipolar voltages. Figure 3 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table 9. SERIAL INTERFACE.µF 5V.5V +.µf µf V DD REFF REFS AD55A/ V OUT AD554A LDAC DGND AGNDF AGNDS Figure 3. Unipolar Output AD8/ OP96 EXTERNAL OP AMP UNIPOLAR OUTPUT Table 9. AD554A Unipolar Code Table DAC Latch Contents MSB LSB Analog Output V REF (65,535/65,536) V REF (3,768/65,536) = ½ V REF V REF (/65,536) V Rev. A Page 5 of 4

16 Assuming a perfect reference, the unipolar worst-case output voltage can be calculated from the following equation: V D = N ( V + V ) + V INL OUT UNI REF GE ZSE + where: V OUT UNI is the unipolar mode worst-case output. D is the code loaded to DAC. N is the resolution of the DAC. V REF is the reference voltage applied to the part. V GE is the gain error in volts. V ZSE is the zero-scale error in volts. INL is the integral nonlinearity in volts. BIPOLAR OUTPUT OPERATION With the aid of an external op amp, the AD55A/AD554A can be configured to provide a bipolar voltage output. A typical circuit is shown in Figure 3. The matched bipolar offset resistors, R FB and R INV, are connected to an external op amp to achieve this bipolar output swing, typically R FB = R INV = 8 kω. Table shows the transfer function for this output operating mode. Also provided on the AD554A are a set of Kelvin connections to the analog ground inputs. The example includes the ADR4 +5V +.5V µf +.5 V reference and the AD868 low offset and zero-drift reference buffer. Table. AD554A Bipolar Code Table DAC Latch Contents MSB LSB Analog Output +V REF (3,767/3,768) +V REF (/3,768) V V REF (/3,768) V REF (3,768/3,768) = V REF Assuming a perfect reference, the worst-case bipolar output voltage can be calculated from the following equation: [( VOUT UNI + VOS )( + RD) V V OUT BIP = + ( + RD ) A where: V OUT BIP is the bipolar mode worst-case output V OUT UNI is the unipolar mode worst-case output. V OS is the external op amp input offset voltage. RD is the R FB and R INV resistor matching error. A is the op amp open-loop gain. REF ( + RD)].µF.µF SERIAL INTERFACE R FB V DD REFF REFS R FB INV R INV V AD55A/ OUT AD554A LDAC DGND AGNDF AGNDS Figure 3. Bipolar Output +5V BIPOLAR OUTPUT 5V EXTERNAL OP AMP Rev. A Page 6 of 4

17 OUTPUT AMPLIFIER SELECTION For bipolar mode, a precision amplifier should be used and supplied from a dual power supply. This provides the ±V REF output. In a single-supply application, selection of a suitable op amp may be more difficult because the output swing of the amplifier does not usually include the negative rail, in this case, AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp must have a very low-offset voltage (the DAC LSB is 38 μv for the AD554A with a.5 V reference) to eliminate the need for output offset trims. Input bias current should also be very low because the bias current, multiplied by the DAC output impedance (approximately 6 kω), adds to the zero-code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 db bandwidth of MHz or greater. The amplifier adds another time constant to the system, thus increasing the settling time of the output. A higher 3 db amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier. FORCE SENSE AMPLIFIER SELECTION Use single-supply, low-noise amplifiers. A low-output impedance at high frequencies is preferred because the amplifiers must be able to handle dynamic currents of up to ± ma. REFERENCE AND GROUND Because the input impedance is code-dependent, the reference pin should be driven from a low impedance source. The AD55A/AD554A operate with a voltage reference ranging from V to V DD. References below V result in reduced accuracy. The full-scale output voltage of the DAC is determined by the reference. Table 9 and Table outline the analog output voltage or particular digital codes. For optimum performance, Kelvin sense connections are provided on the AD55A/AD554A. If the application doesn t require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die. POWER-ON RESET The AD55A/AD554A have a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all s until the data is loaded from the serial register. However, the serial register is not cleared on power-up; therefore, its contents are undefined. When loading data initially to the DAC, 6 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 6 bits are loaded, the last 6 are kept, and if less than 6 bits are loaded, bits remain from the previous word. If the AD55A/AD554A must be interfaced with data shorter than 6 bits, the data should be padded with s at the LSBs. POWER SUPPLY AND REFERENCE BYPASSING For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a μf tantalum capacitor in parallel with a. μf ceramic capacitor. Rev. A Page 7 of 4

18 APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD55A/AD554A is via a serial bus that uses standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD55A/AD554A require a 6-bit data-word with data valid on the rising edge of. The DAC update can be done automatically when all the data is clocked in, or it can be done under the control of the LDAC. AD55A/AD554A TO ADSP-BF53 INTERFACE The SPI interface of the AD55A/AD554A is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 33 shows how the AD55A/AD554A can be connected to the Analog Devices, Inc., Blackfin DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD55A/AD554A. ADSP-BF53 SPISELx SCK MOSI PF9 LDAC AD55A/ AD554A Figure 33. AD55A/AD554A to ADSP-BF53 Interface AD55A/AD554A TO SPORT INTERFACE The Analog Devices ADSP-BF57 has one SPORT serial port. Figure 34 shows how one SPORT interface can be used to control the AD55A/AD554A. ADSP-BF57 SPORT_TFS SPORT_TSCK SPORT_DTO GPIO AD55A/ AD554A LDAC Figure 34. AD55A/AD554A to ADSP-BF57 Interface AD55A/AD554A TO 68HC/68L INTERFACE Figure 35 shows a serial interface between the AD55A/ AD554A and the 68HC/68L microcontroller. SCK of the 68HC/68L drives the of the DAC, and the MOSI output drives the serial data line serial. The signal is driven from one of the port lines. The 68HC/68L is configured for master mode: MSTR =, CPOL =, and CPHA =. Data appearing on the MOSI output is valid on the rising edge of SCK. 68HC/ 68L* PC6 PC7 MOSI SCK *ADDITIONAL PINS OMITTED FOR CLARITY. LDAC AD55A/ AD554A* Figure 35. AD55A/AD554A to 68HC/68L Interface AD55A/AD554A TO ADSP- INTERFACE Figure 36 shows a serial interface between the AD55A/ AD554A and the ADSP-. The ADSP- should be set to operate in the SPORT transmit alternate framing mode. The ADSP- is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 6-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out on each rising edge of the serial clock, an inverter is required between the DSP and the DAC, because the AD55A/AD554A clock data in on the falling edge of the. FO TFS ADSP- DT *ADDITIONAL PINS OMITTED FOR CLARITY. LDAC AD55A/ AD554A* Figure 36. AD55A/AD554A to ADSP- Interface AD55A/AD554A TO MICROWIRE INTERFACE Figure 37 shows an interface between the AD55A/AD554A and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD55A/ AD554A on the rising edge of the serial clock. No glue logic is required because the DAC clocks data into the input shift register on the rising edge AD55A/ MICROWIRE* SO AD554A* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 37. AD55A/AD554A to MICROWIRE Interface Rev. A Page 8 of 4

19 LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD55A/AD554A is mounted so that the analog and digital sections are separated and confined to certain areas of the board. If the AD55A/AD554A are in a system where multiple devices require an analog ground-todigital ground connection, make the connection at one point only. Establish the star ground point as close as possible to the device. The AD55A/AD554A should have ample supply bypassing of μf in parallel with. μf on each supply located as close to the package as possible, ideally right up against the device. The μf capacitors are the tantalum bead type. The. μf capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. icoupler products from Analog Devices provide voltage isolation in excess of.5 kv. The serial loading structure of the AD55A/AD554A makes the parts ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 38 shows a 4-channel isolated interface to the AD55A/AD554A using an ADuM4. For further information, visit DECOG MULTIPLE DA The pin of the AD55A/AD554A can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device receives the signal at any one time. The DAC addressed is determined by the decoder. There is some digital feedthrough from the digital input lines. Using a burst clock minimizes the effects of digital feedthrough on the analog signal channels. Figure 39 shows a typical circuit. ENABLE CODED ADDRESS EN V DD DECODER DGND Figure 39. Addressing Multiple DACs AD55A/ AD554A V OUT AD55A/ AD554A V OUT AD55A/ AD554A V OUT AD55A/ AD554A V OUT CONTROLLER ADuM4 SERIAL CLOCK IN V IA ENCODE DECODE V OA TO SERIAL DATA OUT V IB ENCODE DECODE V OB TO SYNC OUT V IC ENCODE DECODE V OC TO LOAD DAC OUT V ID ENCODE DECODE V OD TO LDAC ADDITIONAL PINS OMITTED FOR CLARITY. Figure 38. Isolated Interface Rev. A Page 9 of 4

20 OUTLINE DIMENSIONS PIN INDICATOR SQ.9.5 BSC PIN INDICATOR EXPOSED PAD.75.6 SQ SEATING PLANE TOP VIEW MAX. NOM COPLANARITY.8. REF 9 8 BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO--WEED MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 4. 6-Lead Lead Frame Chip Scale Package [LFP_WQ] 3 mm 3 mm Body, Very Very Thin Quad (CP-6-) Dimensions shown in millimeters 8-6--E BSC PIN.65 BSC.3.9 COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-AB Figure 4. 6-Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) Dimensions shown in millimeters Rev. A Page of 4

21 3. 3. SQ BSC 6 PIN INDEX AREA TOP VIEW EXPOSED PAD BOTTOM VIEW PIN INDICATOR (R.5) SEATING PLANE MAX. NOM. REF Figure 4. -Lead Lead Frame Chip Scale Package [LFP_WD] 3 mm 3 mm Body, Very Very Thin, Dual Lead (CP--9) Dimensions shown in millimeters FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 9-A ORDERING GUIDE Model INL DNL Power On Reset to Code Temperature Range Package Description Package Option Branding AD55AACPZ-REEL7 ± LSB ± LSB Midscale 4 C to +5 C 6-Lead LFP CP-6- DFQ AD55AACPZ-5RL7 ± LSB ± LSB Midscale 4 C to +5 C 6-Lead LFP CP-6- DFQ AD554ABRUZ ± LSB ± LSB Midscale 4 C to +85 C 6-Lead TSSOP RU-6 AD554ABRUZ-REEL7 ± LSB ± LSB Midscale 4 C to +85 C 6-Lead TSSOP RU-6 AD554AARUZ ± LSB ± LSB Midscale 4 C to +85 C 6-Lead TSSOP RU-6 AD554AARUZ-REEL7 ± LSB ± LSB Midscale 4 C to +85 C 6-Lead TSSOP RU-6 AD554ABCPZ-REEL7 ± LSB ± LSB Midscale 4 C to +85 C 6-Lead LFP_WQ CP-6- DFL AD554AACPZ-REEL7 ± LSB ± LSB Midscale 4 C to +85 C 6-Lead LFP_WQ CP-6- DFK AD544ABCPZ--RL7 ± LSB ± LSB Midscale 4 C to +85 C -Lead LFP_WQ CP--9 DFM AD554ABCPZ-5RL7 ± LSB ± LSB Midscale 4 C to +5 C 6-Lead LFP CP-6- DFL EVAL-AD554ASDZ AD554A Evaluation Board Z = RoHS Compliant Part. Rev. A Page of 4

22 NOTES Rev. A Page of 4

23 NOTES Rev. A Page 3 of 4

24 NOTES - Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D999--5/(A) Rev. A Page 4 of 4