Ultrafast 7 ns Single Supply Comparator AD8561

Transcription

1 a FEATURES 7 ns Propagation Delay at 5 V Single Supply Operation: 3 V to V Low Power Latch Function TSSOP Packages APPLICATIONS High Speed Timing Clock Recovery and Clock Distribution Line Receivers Digital Communications Phase Detectors High Speed Sampling Read Channel Detection PCMCIA Cards Upgrade for LT6 Designs Ultrafast 7 ns Single Supply Comparator AD856 8-Lead Narrow Body SOIC (R-8) V IN IN V AD856 PIN CONFIGURATIONS OUT OUT GND LATCH 8-Lead TSSOP (RU-8) 8-Lead Plastic DIP (N-8) V IN 2 IN 3 V 4 AD856 8 OUT 7 OUT 6 GND 5 LATCH GENERAL DESCRIPTION The AD856 is a single 7 ns comparator with separate input and output sections. Separate supplies enable the input stage to be operated from ± 5 V dual supplies and +5 V single supplies. Fast 7 ns propagation delay makes the AD856 a good choice for timing circuits and line receivers. Propagation delays for rising and falling signals are closely matched and track over temperature. This matched delay makes the AD856 a good choice for clock recovery, since the duty cycle of the output will match the duty cycle of the input. The AD856 has the same pinout as the LT6, with lower supply current and a wider common-mode input range, which includes the negative supply rail. The AD856 is specified over the industrial ( 4 C to +85 C) temperature range. The AD856 is available in the 8-lead plastic DIP, 8-lead TSSOP, and 8-lead narrow SOIC surfacemount packages. V IN IN V 8 AD OUT OUT GND LATCH Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 AD856 SPECIFICATIONS ELECTRICAL SPECIFICATIONS Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V OS mv 4 C T A +85 C 8 mv Offset Voltage Drift ΔV OS /ΔT 4 μv/ C Input Bias Current I B V CM = V 6 3 μa I B 4 C T A +85 C μa Input Offset Current I OS V CM = V ± 4 μa Input Common-Mode Voltage Range V CM. +3. V Common-Mode Rejection Ratio CMRR V V CM +3. V db Large Signal Voltage Gain A VO R L = kω 3 V/V Input Capacitance C IN 3. pf LATCH ENABLE INPUT Logic Voltage Threshold V IH V Logic Voltage Threshold V IL.6.8 V Logic Current I IH V LH = 3. V..3 μa Logic Current I IL V LL =.3 V 4 2 μa Latch Enable Pulsewidth t PW(E) 6 ns Setup Time t S ns Hold Time t H.2 ns DIGITAL OUTPUTS Logic Voltage V OH I OH = 5 μa, ΔV IN > 25 mv 3.5 V Logic Voltage V OH I OH = 3.2 ma, ΔV IN > 25 mv V Logic Voltage V OL I OL = 3.2 ma, ΔV IN > 25 mv.25.4 V DYNAMIC PERFORMANCE Propagation Delay t P 2 mv Step with mv Overdrive ns 4 C T A +85 C 8 3 ns Propagation Delay t P mv Step with 5 mv Overdrive 8 ns Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Δt P mv Step with mv Overdrive.5 2. ns Rise Time 2% to 8% 3.8 ns Fall Time 8% to 2%.5 ns POWER SUPPLY Power Supply Rejection Ratio PSRR +4.5 V V V 5 65 db Positive Supply Current I ma 4 C T A +85 C 7.5 ma Ground Supply Current I GND V O = V, R L = ma 4 C T A +85 C 3.8 ma Analog Supply Current I ma 4 C T A +85 C 5.5 ma NOTES Guaranteed by design. Specifications subject to change without notice. (@ V+ = +5. V, V = V GND = V, T A = +25 C unless otherwise noted) 2

3 ELECTRICAL SPECIFICATIONS AD856 Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V OS 7 mv 4 C T A +85 C 8 mv Offset Voltage Drift ΔV OS /ΔT 4 μv/ C Input Bias Current I B V CM = V 6 3 μa I B 4 C T A +85 C μa Input Offset Current I OS V CM = V ± 4 μa Input Common-Mode Voltage Range V CM V Common-Mode Rejection Ratio CMRR 5. V V CM +3. V db Large Signal Voltage Gain A VO R L = kω 3 V/V Input Capacitance C IN 3. pf LATCH ENABLE INPUT Logic Voltage Threshold V IH V Logic Voltage Threshold V IL.6.8 V Logic Current I IH V LH = 3. V.5 2 μa Logic Current I IL V LL =.3 V μa Latch Enable Pulsewidth t PW(E) 6 ns Setup Time t S. ns Hold Time t H.2 ns DIGITAL OUTPUTS Logic Voltage V OH I OH = 3.2 ma V Logic Voltage V OL I OL = 3.2 ma.2.3 V DYNAMIC PERFORMANCE Propagation Delay t P 2 mv Step with mv Overdrive ns 4 C T A +85 C 8 3 ns Propagation Delay t P mv Step with 5 mv Overdrive 7 ns Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Δt P mv Step with mv Overdrive.5 2 ns Rise Time 2% to 8% 3.8 ns Fall Time 8% to 2%.5 ns Dispersion ns POWER SUPPLY Power Supply Rejection Ratio PSRR ± 4.5 V V CC and V EE ± 5.5 V 55 7 db Supply Current V O = V, R L = Positive Supply Current I ma 4 C T A +85 C 7.5 ma Ground Supply Current I GND V O = V, R L = ma 4 C T A +85 C 3.8 ma Negative Supply Current I ma 4 C T A +85 C 5.5 ma NOTES Guaranteed by design. Specifications subject to change without notice. (@ V+ = +5. V, V = V GND = V, V = 5 V, T A = +25 C unless otherwise noted) 3

4 AD856 SPECIFICATIONS ELECTRICAL SPECIFICATIONS Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V OS 7 mv Input Bias Current I B V CM = V 6 3. μa I B 4 C T A +85 C 7 4 μa Input Common-Mode Voltage Range V CM +.5 V Common-Mode Rejection Ratio CMRR. V V CM.5 V 6 db OUTPUT CHARACTERISTICS Output High Voltage V OH I OH = 3.2 ma, V IN > 25 mv.2 V Output Low Voltage V OL I OL = +3.2 ma, V IN > 25 mv.3 V POWER SUPPLY Power Supply Rejection Ratio PSRR +2.7 V V CC, V EE +6 V 4 db Supply Currents V O = V, R L = V+ Supply Current I ma 4 C T A +85 C 5.5 ma Ground Supply Current I GND ma 4 C T A +85 C 3. ma V Supply Current I ma 4 C T A +85 C 3.8 ma DYNAMIC PERFORMANCE Propagation Delay t P mv Step with 2 mv Overdrive ns NOTES Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for 3 V operation. 2 Guaranteed by design. Specifications subject to change without notice. (@ V+ = +3. V, V = V GND = V, T A = +25 C unless otherwise noted) ABSOLUTE MAXIMUM RATINGS Total Supply Voltage from V to V V Input Voltage ±7 V Differential Input Voltage ±8 V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range N, R, RU Package C to +5 C Operating Temperature Range C to +85 C Junction Temperature Range N, R, RU Package C to +5 C Lead Temperature Range (Soldering, sec) C Package Type JA 2 JC Units 8-Lead Plastic DIP (N) 3 43 C/W 8-Lead SO (R) C/W 8-Lead TSSOP C/W NOTES The analog input voltage is equal to ±7 V or the analog supply voltage, whichever is less. 2 θ JA is specified for the worst case conditions, i.e., θ JA is specified for device in socket for P-DIP and θ JA is specified for device soldered in circuit board for SOIC and TSSOP packages. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD856 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 4 WARNING! ESD SENSITIVE DEVICE

5 AD856 Typical Performance Characteristics (V+ = +5 V, V = V, T A = +25 C unless otherwise noted) OUTPUT VOLTAGE Volts C V S = 5V, SINGLE SUPPLY +25 C 4 C NUMBER OF COMPARATORS PROPAGATION DELAY ns V S = 5V, SINGLE SUPPLY STEP SIZE = mv CAPACITANCE LOAD = pf T A = +25 C DIFFERENTIAL INPUT VOLTAGE mv Figure. Output Voltage vs. Differential Input Voltage INPUT VOLTAGE mv Figure 2. Typical Distribution of Input Offset Voltage OVERDRIVE mv Figure 3. Propagation Delay vs. Overdrive PROPAGATION DELAY ns V S = 5V, SINGLE SUPPLY STEP SIZE = mv OVERDRIVE LOAD = 5mV t PD FALLING EDGE t PD + FALLING EDGE PROPAGATION DELAY ns V S = 5V, SINGLE SUPPLY T OVERDRIVE = mv A = +25 C CAPACITANCE LOAD = pf STEP SIZE = 8mV 4mV 2mV mv PROPAGATION DELAY ns SINGLE SUPPLY, STEP SIZE = mv T A = +25 C OVERDRIVE = 5mV CAPACITANCE LOAD = pf LOAD CAPACITANCE pf Figure 4. Propagation Delay vs. Load Capacitance SOURCE RESISTANCE k Figure 5. Propagation Delay vs. Source Resistance SUPPLY VOLTAGE Volts Figure 6. Propagation Delay vs. Positive Supply Voltage PROPAGATION DELAY ns 5 5 V S = +5V, SINGLE SUPPLY STEP SIZE = mv OVERDRIVE = 5mV, LOAD CAPACITANCE = pf PROPAGATION DELAY ns 5 4 C +25 C 5 V S = 5V STEP SIZE = mv OVERDRIVE = 5mV LOAD CAPACITANCE = pf +25 C TIME ns 3 2 HOLD TIME SET-UP TIME TEMPERATURE C Figure 7. Propagation Delay vs. Temperature COMMON-MODE VOLTAGE Volts Figure 8. Propagation Delay vs. V CM TEMPERATURE C Figure 9. Latch Setup-and-Hold Time vs. Temperature 5

6 AD OUTPUT LOW VOLTAGE Volts T A = 4 C T A = +25 C T A = +25 C OUTPUT HIGH VOLTAGE Volts T A = +25 C T A = 4 C T A = +25 C I, ANALOG SUPPLY CURRENT ma V+ = 5V, V = 5V V+ = 5V, V = V SINK CURRENT ma Figure. Output Low Voltage, V OL vs. Sink Current SOURCE CURRENT ma Figure. Output High Voltage, V OH vs. Source Current TEMPERATURE C Figure 2. Analog Supply Current vs. Temperature for +5 V, 5 V Supplies I, ANALOG SUPPLY CURRENT ma T A = 4 C T A = +25 C T A = +25 C SUPPLY VOLTAGE Volts Figure 3. Analog Supply Current vs. Supply Voltage for +5 V, 5 V Supplies POSITIVE SUPPLY CURRENT ma C +25 C 4 C FREQUENCY MHz Figure 4. Positive Supply Current vs. Frequency INPUT BIAS CURRENT A INPUT COMMON-MODE VOLTAGE Volts Figure 5. Input Bias Current vs. Input Common-Mode Voltage for +5 V, 5 V Supplies INPUT BIAS CURRENT A TEMPERATURE C Figure 6. Input Bias Current vs. Temperature 6

7 AD856 APPLICATIONS OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator or amplifier, proper design and layout techniques should be used to ensure optimal performance from the AD856. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the AD856. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the AD856 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. A combination of 3 kω source resistance and 5 pf of input capacitance yields a time constant of 5 ns, which is slower than the 5 ns capability of the AD856. Source impedances should be less than kω for the best performance. It is also important to provide bypass capacitors for the power supply in a high speed application. A μf electrolytic bypass capacitor should be placed within.5 inches of each power supply pin, Pin and Pin 4, to ground. These capacitors will reduce any potential voltage ripples from the power supply. In addition, a nf ceramic capacitor should be placed as close as possible from the power supply pins to ground. These capacitors act as a charge reservoir for the device during high frequency switching. A ground plane is recommended for proper high speed performance. This can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks in the plane for necessary current paths. The ground plane provides a low inductive ground, eliminating any potential differences at different ground points throughout the circuit board caused from ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. REPLACING THE LT6 The AD856 is pin compatible with the LT6 comparator. While it is easy to replace the LT6 with the higher performance AD856, please note that there are differences, and it is useful to check these to ensure proper operation. There are five major differences between the AD856 and the LT6 input voltage range, input bias currents, speed, output swing and power consumption. When operated on a +5 V single supply, the LT6 has an input voltage range from +.25 V to +3.5 V. The AD856 has a wider input range from V to 3. V. Signals above 3. V may result in slower response times (see Figure 8). If both signals exceed 3. V, the signals may be shifted or attenuated to bring them into range, keeping in mind the note about source resistance in Optimizing High Speed Performance. If only one of the signals exceeds 3. V only slightly, and the other signal is always well within the V to 3 V range, the comparator may operate without changes to the circuit. Example: A comparator compares a fast moving signal to a fixed 2.5 V reference. Since the comparator only needs to operate when the signal is near 2.5 V, both signals will be within the input range (near 2.5 V and well under 3. V) when the comparator needs to change output. Note that signals much greater than 3. V will result increased input currents and may cause the device to operate more slowly. The input bias current of the AD856 is lower ( 3 μa typical) than the LT6 (+5 μa typical), and the current flows out of the AD856 and into LT6. If relatively low value resistors and/or low impedance sources are used on the inputs, the voltage shift due to bias current should be small. The AD856 (6.75 ns typical) is faster than the LT6 ( ns typical). While this is beneficial to many systems, timing may need to be adjusted to take advantage of the higher speed. The AD856 has slightly more output voltage swing, from.2 V above ground to within. V of the positive supply voltage. The AD856 uses less current (typically 5 ma) than the LT6 (typically 25 ma). INCREASING OUTPUT SWING Although not required for normal operation, the output voltage swing of the AD856 can be increased by connecting a 5 kω resistor from the output of the device to the V+ power supply. This configuration can be useful in low voltage power supply applications where maximizing output voltage swing is important. Adding a 5 kω pull-up resistor to the device s output will not adversely affect the specifications of the AD856. OUTPUT LOADING CONSIDERATIONS The AD856 output can deliver up to 4 ma of output current without any significant increase in propagation delay. The output of the device should not be connected to more than twenty (2) TTL input logic gates, or drive a load resistance less than Ω. To ensure the best performance from the AD856 it is important to minimize capacitive loading of the output of the device. Capacitive loads greater than 5 pf will cause ringing on the output waveform and will reduce the operating bandwidth of the comparator. SETUP AND HOLD TIMES FOR LATCHING THE OUTPUT The latch input, Pin 5, can be used to retain data at the output of the AD856. When the voltage at the latch input goes high, the output of the device will remain constant regardless of the input voltages. The setup time for the latch is 2 ns 3 ns and the hold time is 3 ns. This means that to ensure data retention at the output, the input signal must be valid at least 5 ns before the latch pin goes high and must remain valid at least 3 ns after the latch pin goes high. Once the latch input voltage goes low, new output data will appear in approximately 8 ns. A logic high for the latch input is a minimum of +2. V and a logic low is a maximum of +.8 V. This makes the latch input easily interface with TTL or CMOS logic gates. The latch circuitry in the AD856 has no built-in hysteresis. 7

8 AD856 INPUT STAGE AND BIAS CURRENTS The AD856 uses a PNP differential input stage that enables the input common-mode range to extend all the way from the negative supply rail to within 2.2 V of the positive supply rail. The input common-mode voltage can be found as the average of the voltage at the two inputs of the device. To ensure the fastest response time, care should be taken not to allow the input common-mode voltage to exceed either of these voltages. The input bias current for the AD856 is 3 μa. As with any PNP differential input stage, this bias current will go to zero on an input that is high and will double on an input that is low. Care should be taken in choosing resistor values to be connected to the inputs as large resistors could cause significant voltage drops due to the input bias current. The input capacitance for the AD856 is typically 3 pf. This is measured by inserting a 5 kω source resistance to the input and measuring the change in propagation delay. USING HYSTERESIS Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desirable for the output to toggle between states when the input signal is near the switching threshold. Figure 7 shows a method for configuring the AD856 with hysteresis. The input signal is connected directly to the noninverting input of the comparator. The output is fed back to the inverting input through R and R2. The ratio of R to R + R2 establishes the width of the hysteresis window with V REF setting the center of the window, or the average switching voltage. The Q output will switch high when the input voltage is greater than V HI and will not switch low again until the input voltage is less than V LO as given in Equation : ( ) V HI = V + V REF R V LO =V REF R+ R2 R R+ R2 +V REF Where V + is the positive supply voltage. The capacitor C F can also be added to introduce a pole into the feedback network. This has the effect of increasing the amount of hysteresis at high frequencies. This can be useful when comparing a relatively slow signal in a high frequency noise environment. At frequencies greater than f P =, the hysteresis 2π C F R2 window approaches V HI = V + V and V LO = V. At frequencies less than f P the threshold voltages remain as in Equation. () SIGNAL COMPARATOR V REF R R2 C F Figure 7. Configuring the AD856 with Hysteresis 8

9 SPICE Model AD856 SPICE Macro-Model Typical Values 4/98, Ver.. TAM / ADSC Node assignments non-inverting input inverting input positive supply negative supply Latch DGND Q QNOT.SUBCKT AD INPUT STAGE Q PIX Q PIX IBIAS E-6 RC 4 5 E3 RC2 6 5 E3 CL 4 6 E-2 CIN 2 3E-2 VCM 99 7 D 5 7 DX EOS 3 POLY() (3,98) E-3 Reference Voltage EREF 98 POLY(2) (99,) (5,).5.5 RREF 98 E3 CMRR=8dB, ZERO AT khz ECM 3 98 POLY(2) (,98) (2,98).5.5 RCM 3 3 E3 RCM CCM E-9 Latch Section RX 8 5 E3 E 98 (4,6) S (8,5) SLATCH R2 2 C E-2 E (2,98) R Power Supply Section AD856 9

10 AD856 GSY POLY() (99,5) 4E-3-2.6E-4 GSY POLY() (99,5) 3.7E-3 -.6E-3 RSY 52 5 Gain Stage Av=25 fp=mhz G (2,98).25 R 2 98 C 2 98 E-3 D2 2 2 DX D DX V 99 2 DC.8 V DC.8 Q Output Q NOX Q NOX RB RB E3 CB 99 4 E-2 CB E-2 RO E3 RO EO POLY() (2,98) EO POLY() (2,98) Q NOT Output Q NOX Q NOX RB RB E3 CB E-2 CB E-2 RO E3 RO EO POLY() (2,98) EO POLY() (2,98) MODELS.MODEL PIX PNP(BF=,IS=E-6).MODEL NOX NPN(BF=,VAF=3,IS=E-4).MODEL DX D(IS=E-6).MODEL SLATCH VSWITCH(ROFF=E6,RON=5,VOFF=2.,VON=.4).ENDS AD856

11 AD856 OUTLINE DIMENSIONS.4 (.6).365 (9.27).355 (9.2).2 (5.33) MAX.5 (3.8).3 (3.3).5 (2.92).22 (.56).8 (.46).4 (.36) 8. (2.54) BSC 5.28 (7.).25 (6.35) 4.24 (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.52) MAX.5 (.38) GAUGE PLANE.325 (8.26).3 (7.87).3 (7.62).43 (.92) MAX.95 (4.95).3 (3.3).5 (2.92).4 (.36). (.25).8 (.2).7 (.78).6 (.52).45 (.4) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 8. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 766-A 4. (.574) 3.8 (.497).25 (.98). (.4) COPLANARITY. SEATING PLANE 5. (.968) 4.8 (.89) (.5) BSC 6.2 (.244) 5.8 (.2284).75 (.688).35 (.532).5 (.2).3 (.22).25 (.98).7 (.67).5 (.96).25 (.99).27 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 9. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) PIN COPLANARITY BSC MAX SEATING PLANE 6.4 BSC COMPLIANT TO JEDEC STANDARDS MO-53-AA Figure 2. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters Page of 2

12 AD856 ORDERING GUIDE Model Temperature Range Package Description Package Option AD856ANZ 4 C to +85 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD856ARUZ 4 C to +85 C 8-Lead Thin Shrink Small Outline Package [TSSOP] RU-8 AD856ARUZ-REEL 4 C to +85 C 8-Lead Thin Shrink Small Outline Package [TSSOP] RU-8 AD856ARZ 4 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD856ARZ-REEL 4 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD856ARZ-REEL7 4 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 Z = RoHS Compliant Part. REVISION HISTORY 2/26 Rev. C to Changed SO-8 to R Throughout Changes to General Description Section... /26 Rev. B to Rev. C Changes to Absolute Maximum Ratings Section /23 Rev. A to Rev. B Changes to Figure 9 Caption and Figure 2 Caption... Changes to Ordering Guide /23 Rev. to Rev. A Change to Lead Temperature Range (Soldering, Sec) Parameter, Absolute Maximum Ratings Section... 4 Updated Outline Dimensions... Moved Ordering Guide and Added Revision History Section... 2 Changes to Ordering Guide /998 Revision : Initial Version Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D322--2/6(D) Page 2 of 2