ICL7660S. Super Voltage Converter. Features. Applications. Ordering Information. Pinouts. Data Sheet January 2004 FN3179.3

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1 Data Sheet January FN9. Super Voltage Converter The Super Voltage Converter is a monolithic CMOS voltage conversion IC that guarantees significant performance advantages over other similar devices. It is a direct replacement for the industry standard ICL offering an extended operating supply voltage range up to V, with lower supply current. No external diode is needed for the. In addition, a Frequency Boost pin has been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. All improvements are highlighted in the Electrical Specifications section. Critical parameters are guaranteed over the entire commercial, industrial and military temperature ranges. The performs supply voltage conversion from positive to negative for an input range of.v to V, resulting in complementary output voltages of.v to V. Only noncritical external capacitors are needed for the charge pump and charge reservoir functions. The can be connected to function as a voltage doubler and will generate up to.v with a V input. It can also be used as a voltage multiplier or voltage divider. The chip contains a series DC power supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. The oscillator, when unloaded, oscillates at a nominal frequency of khz for an input supply voltage of.v. This frequency can be lowered by the addition of an external capacitor to the OSC terminal, or the oscillator may be overdriven by an external clock. The LV terminal may be tied to GND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (.V to V), the LV pin is left floating to prevent device latchup. Pinouts BOOST CAP GND (PDIP, SOIC) TOP VIEW OSC LV V OUT BOOST CAP (CAN) TOP VIEW GND (AND CASE) CAP CAP OSC LV V OUT Features Guaranteed Lower Max Supply Current for All Temperature Ranges Wide Operating Voltage Range.V to V % Tested at V No External Diode Over Full Temperature and Voltage Range Boost Pin (Pin ) for Higher Switching Frequency Guaranteed Minimum Power Efficiency of 9% Improved Minimum Open Circuit Voltage Conversion Efficiency of 99% Improved SCR Latchup Protection Simple Conversion of V Logic Supply to ±V Supplies Simple Voltage Multiplication V OUT = ()nv IN Easy to Use Requires Only External NonCritical Passive Components Improved Direct Replacement for Industry Standard ICL and Other Second Source Devices Available in Lead Free Applications Simple Conversion of V to ±V Supplies Voltage Multiplication V OUT = ±nv IN Negative Supplies for Data Acquisition Systems and Instrumentation RS Power Supplies Supply Splitter, V OUT = ±V S / Ordering Information PART # TEMP. RANGE ( o C) PACKAGE PKG. DWG. # CBA to Ld SOIC (N) M. CPA to Ld PDIP E. IBA to Ld SOIC (N) M. IBAZ (Note ) IBAZT (Note ) to Ld SOIC (N) (leadfree) M. to Ld SOIC (N) M. (leadfree) Tape and Reel IPA to Ld PDIP E. MTV to Pin Metal Can T.C (Note ) NOTES:. Intersil Lead Free products employ special lead free material sets; molding compounds / die attach materials and % matte tin plate termination finish, which is compatible with both SnPb and lead free soldering operations. Intersil Lead Free products are MSL classified at lead free peak reflow temperatures that meet or exceed the lead free requirements of IPC/JEDEC J StdB.. Add /B to part number if B processing is required. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Absolute Maximum Ratings Supply Voltage V LV and OSC Input Voltage (Note ) <.V V to.v >.V V to.v Current into LV (Note ) >.V µA Output Short Duration V SUPPLY.V Continuous Storage Temperature Range o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIP N/A Plastic SOIC N/A Metal Can Maximum Lead Temperature (Soldering s) o C (SOIC Lead Tips Only) Operating Conditions Temperature Range M o C to o C I o C to o C C o C to o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Connecting any terminal to voltages greater than or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to power up of.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications = V, T A = o C, OSC = Free running, Test Circuit Figure, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Supply Current (Note ) I R L =, o C µa o C < T A < o C µa o C < T A < o C µa o C < T A < o C µa Supply Voltage Range High (Note ) H R L = K, LV Open, T MIN < T A < T MAX. V Supply Voltage Range Low L R L = K, LV to GND, T MIN < T A < T MAX.. V Output Source Resistance R OUT I OUT = ma Ω I OUT = ma, o C < T A < o C Ω I OUT = ma, o C < T A < o C Ω I OUT = ma, o C < T A < o C Ω I OUT = ma, = V, LV = GND, o C < T A < o C I OUT = ma, = V, LV = GND, o C < T A < o C I OUT = ma, = V, LV = GND, o C < T A < o C Ω Ω Ω Oscillator Frequency (Note ) f OSC C OSC =, Pin Open or GND khz C OSC =, Pin = khz Power Efficiency P EFF R L = kω 9 9 % T MIN < T A < T MAX R L = kω 9 9 Voltage Conversion Efficiency V OUT EFF R L = %

3 Electrical Specifications = V, T A = o C, OSC = Free running, Test Circuit Figure, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Oscillator Impedance Z OSC = V MΩ = V kω NOTES:. Derate linearly above o C by.mw/ o C. In the test circuit, there is no external capacitor applied to pin. However, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, of the order of pf.. The Intersil can operate without an external diode over the full temperature and voltage range. This device will function in existing designs which incorporate an external diode with no degradation in overall circuit performance.. All significant improvements over the industry standard ICL are highlighted. Typical Performance Curves (Test Circuit Figure ) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE RANGE (NO DIODE REQUIRED) TEMPERATURE ( o C) FIGURE. OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE OUTPUT SOURCE RESISTANCE (Ω) T A = o C T A = o C T A = o C SUPPLY VOLTAGE (V) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE OUTPUT SOURCE RESISTANCE (Ω) I OUT = ma, = V I OUT = ma, = V I OUT = ma, = V I OUT = ma, = V TEMPERATURE ( o C) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE POWER CONVERSION EFFICIENCY (%) = V T A = o C I OUT = ma k k k OSC FREQUENCY F OSC (Hz) FIGURE. POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSCILLATOR FREQUENCY

4 Typical Performance Curves (Test Circuit Figure ) (Continued) OSCILLATOR FREQUENCY f OSC (khz) 9 = V T A = o C OSCILLATOR FREQUENCY f OSC (khz) = V = V k C OSC (pf) TEMPERATURE ( o C) FIGURE. FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSCILLATOR CAPACITANCE FIGURE. UNLOADED OSCILLATOR FREQUENCY AS A FUNCTION OF TEMPERATURE OUTPUT VOLTAGE (V) = V T A = o C LOAD CURRENT (ma) FIGURE. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT POWER CONVERSION EFFICIENCY (%) 9 = V T A = o C LOAD CURRENT (ma) 9 FIGURE. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT SUPPLY CURRENT (ma) OUTPUT VOLTAGE (V) = V T A = o C 9 LOAD CURRENT (ma) FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT POWER CONVERSION EFFICIENCY (%) 9 = V T A = o C... 9 LOAD CURRENT (ma) FIGURE. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT SUPPLY CURRENT (ma) (NOTE 9)

5 Typical Performance Curves (Test Circuit Figure ) (Continued) OUTPUT RESISTANCE (Ω) = V T A = o C I = ma C = C = µf C = C = µf C = C = µf k k k OSCILLATOR FREQUENCY (Hz) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY NOTE: 9. These curves include in the supply current that current fed directly into the load R L from the (See Figure ). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the, to the negative side of the load. Ideally, V OUT V IN, I S I L, so V IN x I S V OUT x I L. Detailed Description The contains all the necessary circuitry to complete a negative voltage converter, with the exception of external capacitors which may be inexpensive µf polarized electrolytic types. The mode of operation of the device may be best understood by considering Figure, which shows an idealized negative voltage converter. Capacitor C is charged to a voltage,, for the half cycle when switches S and S are closed. (Note: Switches S and S are open during this half cycle.) During the second half cycle of operation, switches S and S are closed, with S and S open, thereby shifting capacitor C to C such that the voltage on C is exactly, assuming ideal switches and no load on C. The approaches this ideal situation more closely than existing nonmechanical circuits. C µf In the, the switches of Figure are MOS power switches; S is a PChannel devices and S, S and C µf I L I S (V) R L VOUT NOTE: For large values of C OSC (>pf) the values of C and C should be increased to µf. FIGURE. TEST CIRCUIT S are NChannel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S and S must always remain reverse biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit start up, and under output short circuit conditions (V OUT = ), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. This problem is eliminated in the by a logic network which senses the output voltage (V OUT ) together with the level translators, and switches the substrates of S and S to the correct level to maintain necessary reverse bias. The voltage regulator portion of the is an integral part of the antilatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation LV pin should be connected to GND, disabling the regulator. For supply voltages greater than.v the LV terminal must be left open to insure latchup proof operation, and prevent device damage. Theoretical Power Efficiency Considerations In theory a voltage converter can approach % efficiency if certain conditions are met:. The drive circuitry consumes minimal power.. The output switches have extremely low ON resistance and virtually no offset.. The impedance of the pump and reservoir capacitors are negligible at the pump frequency.

6 The approaches these conditions for negative voltage conversion if large values of C and C are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: E = / C (V V ) where V and V are the voltages on C during the pump and transfer cycles. If the impedances of C and C are relatively high at the pump frequency (refer to Figure ) compared to the value of R L, there will be substantial difference in the voltages V and V. Therefore it is not only desirable to make C as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C in order to achieve maximum efficiency of operation. S S V IN C S S V OUT = V IN FIGURE. IDEALIZED NEGATIVE VOLTAGE CONVERTER Do s and Don ts. Do not exceed maximum supply voltages.. Do not connect LV terminal to GND for supply voltage greater than.v.. Do not short circuit the output to V supply for supply voltages above.v for extended periods, however, transient conditions including startup are okay.. When using polarized capacitors, the terminal of C must be connected to pin of the and the terminal of C must be connected to GND.. If the voltage supply driving the has a large source impedance (Ω Ω), then a.µf capacitor from pin to ground may be required to limit rate of rise of input voltage to less than V/µs.. User should insure that the output (pin ) does not go more positive than GND (pin ). Device latch up will occur under these conditions. A N9 or similar diode placed in parallel with C will prevent the device from latching up under these conditions. (Anode pin, Cathode pin ). C Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the for generation of negative supply voltages. Figure shows typical connections to provide a negative supply where a positive supply of.v to V is available. Keep in mind that pin (LV) is tied to the supply negative (GND) for supply voltage below.v. µf The output characteristics of the circuit in Figure can be approximated by an ideal voltage source in series with a resistance as shown in Figure B. The voltage source has a value of (). The output impedance (R O ) is a function of the ON resistance of the internal MOS switches (shown in Figure ), the switching frequency, the value of C and C, and the ESR (equivalent series resistance) of C and C. A good first order approximation for R O is: R O (R SW R SW ESR C ) (R SW R SW ESR C ) fpump x ESR C C (f PUMP = f OSC, R SWX = MOSFET switch resistance) Combining the four R SWX terms as R SW, we see that: R O x R SW f PUMP x C µf V OUT = x ESR C ESR C Ω R SW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs), typically Ω at o C and V. Careful selection of C and C will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the /(f PUMP x C ) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the /(f PUMP x C ) term, but may have the side effect of a net R O A. B. FIGURE. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT EQUIVALENT VOUT

7 increase in output impedance when C > µf and is not long enough to fully charge the capacitors every cycle. In a typical application where f OSC = khz and C = C = C = µf: R O x Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of, a high value could potentially swamp out a low /f PUMP x C ) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as Ω. Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by voltages, A and B, as shown in Figure. Segment A is the voltage drop across the ESR of C at the instant it goes from being charged by C (current flowing into C ) to being discharged through the load (current flowing out of C ). The magnitude of this current change is x I OUT, hence the total drop is x I OUT x ESR C V. Segment B is the voltage change across C during time t, the half of the cycle when C supplies current the load. The drop at B is I OUT x t /C V. The peaktopeak ripple voltage is the sum of these voltage drops: Again, a low ESR capacitor will result in a higher performance output. Paralleling Devices Any number of voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C, serves all devices while each device requires its own pump capacitor, C. The resultant output resistance would be approximately: R OUT = Cascading Devices The may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is devices for light loads. The output voltage is defined by: V OUT = n(v IN ), x ESR C ( x x x ) ESR C R O x ESR C Ω V RIPPLE ESRC I f OUT PUMP C R OUT (of ) n (number of devices) where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual R OUT values. Changing the Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to alter the oscillator frequency. This can be achieved simply by one of several methods described below. By connecting the Boost Pin (Pin ) to, the oscillator charge and discharge current is increased and, hence, the oscillator frequency is increased by approximately / times. The result is a decrease in the output impedance and ripple. This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller capacitors, e.g..µf, can be used in conjunction with the Boost Pin in order to achieve similar output currents compared to the device free running with C = C = µf or µf. (Refer to graph of Output Source Resistance as a Function of Oscillator Frequency). Increasing the oscillator frequency can also be achieved by overdriving the oscillator from an external clock, as shown in Figure. In order to prevent device latchup, a kω resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a kω pullup resistor to supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be / of the clock frequency. Output transitions occur on the positive going edge of the clock. µf It is also possible to increase the conversion efficiency of the at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure 9. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C ) and reservoir (C ) capacitors; this is overcome by increasing the values of C and C by the same factor that the frequency has been reduced. For example, the addition of a pf capacitor between pin (OSC and will lower the oscillator frequency to khz from its nominal frequency of khz (a multiple of ), and thereby necessitate corresponding increase in the value of C and C (from µf to µf). kω µf FIGURE. EXTERNAL CLOCKING V OUT CMOS GATE

8 C C OSC C V OUT FIGURE. LOWERING OSCILLATOR FREQUENCY C C D D C C V OUT = V IN V OUT = () (V FD ) (V FD ) Positive Voltage Doubling The may be employed to achieve positive voltage doubling using the circuit shown in Figure. In this application, the pump inverter switches of the are used to charge C to a voltage level of V F (where is the supply voltage and V F is the forward voltage on C plus the supply voltage () is applied through diode D to capacitor C. The voltage thus created on C becomes () (V F ) or twice the supply voltage minus the combined forward voltage drops of diodes D and D. The source impedance of the output (V OUT ) will depend on the output current, but for = V and an output current of ma it will be approximately Ω. Combined Negative Voltage Conversion and Positive Supply Doubling Figure combines the functions shown in Figure and Figure to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating 9V and V from an existing V supply. In this instance capacitors C and C perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors C and C are pump and reservoir respectively for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin of the device. D D V OUT = () (V F ) C C NOTE: D and D can be any suitable diode. FIGURE. POSITIVE VOLTAGE DOUBLER FIGURE. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER Voltage Splitting The bidirectional characteristics can also be used to split a high supply in half, as shown in Figure. The combined load will be evenly shared between the two sides, and a high value resistor to the LV pin ensures startup. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure, V can be converted (via., and. to a nominal V, although with rather high series output resistance ( Ω). R L µf V OUT = V R L µf µf Regulated Negative Voltage Supply FIGURE 9. SPLITTING A SUPPLY IN HALF In Some cases, the output impedance of the can be a problem, particularly if the load current varies substantially. The circuit of Figure can be used to overcome this by controlling the input voltage, via an ICL lowpower CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the s output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than Ω to a load of ma. V

9 V k k k k V ICL Ω µf ICL9 µf V OUT k k VOLTAGE ADJUST µf FIGURE. REGULATING THE OUTPUT VOLTAGE V LOGIC SUPPLY TTL DATA INPUT RS DATA OUTPUT V V µf IH µf FIGURE. RS LEVELS FROM A SINGLE V SUPPLY Other Applications Further information on the operation and use of the may be found in AN Principles and Applications of the ICL CMOS Voltage Converter. 9

10 DualInLine Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B C A N N/ B D e D E B A. (.) M C A A L B S NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M9.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm).. E and e A are measured with the leads constrained to be perpendicular to datum C.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E., E., E., E., E. will have a B dimension of.. inch (..mm). A e C E C L e A C e B E. (JEDEC MSBA ISSUE D) LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.. A..9 A B.... B...., C.... D D.. E.... E.... e. BSC. BSC e A. BSC. BSC e B..9 L...9. N 9 Rev. /9

11 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B.(.) M C A M E B A C SEATING PLANE A B S H A µ.(.) M B α.(.) L M h x o NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M9.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M. (JEDEC MSAA ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.... A..9.. B C D E.9... e. BSC. BSC H.... h L.... N α o o o o Rev. /9

12 Metal Can Packages (Can) ØD ØD F Q A REFERENCE PLANE Øb A A L L L Øb Øb ØD NOTES:. (All leads) Øb applies between L and L. Øb applies between L and. from the reference plane. Diameter is uncontrolled in L and beyond. from the reference plane.. Measured from maximum diameter of the product.. α is the basic spacing from the centerline of the tab to terminal and β is the basic spacing of each lead or lead position (N places) from α, looking at the bottom of the package.. N is the maximum number of terminal positions.. Dimensioning and tolerancing per ANSI Y.M 9.. Controlling dimension: INCH. Øe BASE AND SEATING PLANE BASE METAL SECTION AA Øb β e LEAD FINISH N α k k C L T.C MILSTD MACYX (A) LEAD METAL CAN PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A...9. Øb..9.. Øb.... Øb.... ØD ØD.... ØD...9. e. BSC. BSC e. BSC. BSC F.. k...9. k...9. L L.. L.. Q.... α o BSC o BSC β o BSC o BSC N Rev. //9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see

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