DATASHEET ICL7660S, ICL7660A. Features. Applications. Pin Configurations. Super Voltage Converters. FN3179 Rev 7.00 Page 1 of 13.

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1 DATASHEET ICLS, ICLA Super Voltage Converters The ICLS and ICLA Super Voltage Converters are monolithic CMOS voltage conversion ICs that guarantee significant performance advantages over other similar devices. They are direct replacements for the industry standard ICL offering an extended operating supply voltage range up to V, with lower supply current. A Frequency Boost pin has been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. All improvements are highlighted in the Electrical Specifications section on page. Critical parameters are guaranteed over the entire commercial and industrial temperature ranges. The ICLS and ICLA perform supply voltage conversions from positive to negative for an input range of.v to V, resulting in complementary output voltages of.v to V. Only two noncritical external capacitors are needed, for the charge pump and charge reservoir functions. The ICLS and ICLA can be connected to function as a voltage doubler and will generate up to.v with a V input. They can also be used as a voltage multipliers or voltage dividers. Each chip contains a series DC power supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. The oscillator, when unloaded, oscillates at a nominal frequency of khz for an input supply voltage of.v. This frequency can be lowered by the addition of an external capacitor to the OSC terminal, or the oscillator may be overdriven by an external clock. The LV terminal may be tied to GND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (.V to V), the LV pin is left floating to prevent device latchup. Features Guaranteed Lower Max Supply Current for All Temperature Ranges Wide Operating Voltage Range:.V to V % Tested at V Boost Pin (Pin ) for Higher Switching Frequency Guaranteed Minimum Power Efficiency of 9% FN9 Rev. January, Improved Minimum Open Circuit Voltage Conversion Efficiency of 99% Improved SCR Latchup Protection Simple Conversion of V Logic Supply to ±V Supplies Simple Voltage Multiplication V OUT = ()nv IN Easy to Use; Requires Only Two External NonCritical Passive Components Improved Direct Replacement for Industry Standard ICL and Other Second Source Devices PbFree Available (RoHS Compliant) Applications Simple Conversion of V to ±V Supplies Voltage Multiplication V OUT = ±nv IN Negative Supplies for Data Acquisition Systems and Instrumentation RS Power Supplies Supply Splitter, V OUT = ±V S In some applications, an external Schottky diode from V OUT to CAP is needed to guarantee latchup free operation (see Do s and Dont s section on page ). Pin Configurations ICLS ( LD PDIP, SOIC) TOP VIEW ICLA ( LD PDIP, SOIC) TOP VIEW BOOST V NC V CAP OSC CAP OSC GND LV GND LV V OUT CAP CAP V OUT FN9 Rev. Page of January,

2 ICLS, ICLA Ordering Information PART NUMBER (NOTE ) PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # ICLSCBA (Note ) SCBA to Ld SOIC M. ICLSCBAZ SCBAZ to Ld SOIC (Pbfree) M. (Notes, ) ICLSCPA S CPA to Ld PDIP E. ICLSCPAZ (Note ) S CPAZ to Ld PDIP (Pbfree; Note ) E. ICLSIBA (Note ) SIBA to Ld SOIC M. ICLSIBAZ SIBAZ to Ld SOIC (Pbfree) M. (Notes, ) ICLSIPA SIPA to Ld PDIP E. ICLSIPAZ S IPAZ to Ld PDIP (Pbfree; Note ) E. (Note ) ICLACBA (Note ) ACBA to Ld SOIC (N) M. ICLACBAZA ACBAZ to Ld SOIC (N) (Pbfree) M. (Notes, ) ICLACPA ACPA to Ld PDIP E. ICLACPAZ (Note ) ACPAZ to Ld PDIP (Pbfree; Note ) E. ICLAIBA (Note ) AIBA to Ld SOIC (N) M. ICLAIBAZA AIBAZ to Ld SOIC (N) (Pbfree) M. (Notes, ) NOTES:. Add T* suffix for tape and reel. Please refer to TB for details on reel specifications.. These Intersil Pbfree plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations). Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD.. For Moisture Sensitivity Level (MSL), please see device information page for ICLS, ICLA. For more information on MSL, please see Tech Brief TB.. Pbfree PDIPs can be used for throughhole wave solder processing only. They are not intended for use in reflow solder processing applications. FN9 Rev. Page of January,

3 ICLS, ICLA Absolute Maximum Ratings Supply Voltage V LV and OSC Input Voltage (Note ) V <.V V to V.V V >.V V.V to V.V Current into LV (Note ) V >.V µA Output Short Duration V SUPPLY.V Continuous Operating Conditions Temperature Range ICLSI, ICLAI C to C ICLSC, ICLAC C to C Thermal Information Thermal Resistance (Typical, Notes, ) JA ( C/W) JC ( C/W) Ld PDIP* Ld Plastic SOIC Storage Temperature Range C to C Pbfree reflow profile see link below *Pbfree PDIPs can be used for throughhole wave solder processing only. They are not intended for use in reflow solder processing applications. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. Connecting any terminal to voltages greater than V or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to power up of ICLS and ICLA.. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB9 for details.. For JC, the case temp location is taken at the package top center.. Pbfree PDIPs can be used for throughhole wave solder processing only. They are not intended for use in reflow solder processing applications. Electrical Specifications ICLS and ICLA, V = V, T A = C, OSC = Free running (see Figure, ICLS Test Circuit on page and Figure ICLA Test Circuit on page ), unless otherwise specified. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS Supply Current (Note ) I R L =, C µa C < T A < C µa C < T A < C µa C < T A < C µa Supply Voltage Range High (Note ) V H R L = k, LV Open, T MIN < T A < T MAX. V Supply Voltage Range Low V L R L = k, LV to GND, T MIN < T A < T MAX.. V Output Source Resistance R OUT I OUT = ma I OUT = ma, C < T A < C I OUT = ma, C < T A < C I OUT = ma, C < T A < C I OUT = ma, V = V, LV = GND, C < T A < C I OUT = ma, V = V, LV = GND, C < T A < C I OUT = ma, V = V, LV = GND, C < T A < C Oscillator Frequency (Note ) f OSC C OSC =, Pin Open or GND khz C OSC =, Pin = V khz Power Efficiency P EFF R L = k 9 9 % T MIN < T A < T MAX R L = k 9 9 Voltage Conversion Efficiency V OUT EFF R L = % FN9 Rev. Page of January,

4 ICLS, ICLA Electrical Specifications ICLS and ICLA, V = V, T A = C, OSC = Free running (see Figure, ICLS Test Circuit on page and Figure ICLA Test Circuit on page ), unless otherwise specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS Oscillator Impedance Z OSC V = V M V = V k ICLA, V = V, T A = C, OSC = Free running, Test Circuit Figure, unless otherwise specified Supply Current (Note ) I V = V, R L =, C A C < T A < C A C < T A < C A Output Source Resistance R OUT V = V, I OUT = ma 9 C < T A < C C < T A < C Oscillator Frequency (Note ) f OSC V = V (same as V conditions). khz C < T A < C. khz C < T A < C. khz NOTES: 9. Parameters with MIN and/or MAX limits are % tested at C, unless otherwise specified. Temperature limits established by characterization and are not production tested.. In the test circuit, there is no external capacitor applied to pin. However, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, on the order of pf.. The Intersil ICLS and ICLA can operate without an external diode over the full temperature and voltage range. This device will function in existing designs that incorporate an external diode with no degradation in overall circuit performance.. All significant improvements over the industry standard ICL are highlighted.. Derate linearly above C by.mw/ C. FN9 Rev. Page of January,

5 ICLS, ICLA Functional Block Diagram V OSC LV OSCILLATOR AND DIVIDEBY COUNTER VOLTAGE LEVEL TRANSLATOR Q Q CAP GND INTERNAL SUPPLY REGULATOR Q Q SUBSTRATE LOGIC NETWORK CAP V OUT Typical Performance Curves See Figure, ICLS Test Circuit on page ) and Figure ICLA Test Circuit on page SUPPLY VOLTAGE (V) SUPPLY VOLTAGE RANGE (NO DIODE REQUIRED) TEMPERATURE ( C) FIGURE. OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE OUTPUT SOURCE RESISTANCE (Ω) T A = C T A = C T A = C SUPPLY VOLTAGE (V) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE OUTPUT SOURCE RESISTANCE (Ω) I OUT = ma, V = V I OUT = ma, V = V I OUT = ma, V = V I OUT = ma, V = V TEMPERATURE ( C) POWER CONVERSION EFFICIENCY (%) V = V T A = C I OUT = ma k k k OSC FREQUENCY f OSC (Hz) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE FIGURE. POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSCILLATOR FREQUENCY FN9 Rev. Page of January,

6 ICLS, ICLA Typical Performance Curves See Figure, ICLS Test Circuit on page ) and Figure ICLA Test Circuit on page (Continued) OSCILLATOR FREQUENCY f OSC (khz) 9 V = V T A = C OSCILLATOR FREQUENCY f OSC (khz) V = V V = V k C OSC (pf) TEMPERATURE ( C) FIGURE. FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSCILLATOR CAPACITANCE FIGURE. UNLOADED OSCILLATOR FREQUENCY AS A FUNCTION OF TEMPERATURE OUTPUT VOLTAGE (V) V = V T A = C LOAD CURRENT (ma) POWER CONVERSION EFFICIENCY (%) 9 V = V T A = C LOAD CURRENT (ma) 9 SUPPLY CURRENT (ma) FIGURE. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT FIGURE. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT OUTPUT VOLTAGE (V) V = V T A = C POWER CONVERSION EFFICIENCY (%) 9 V = V T A = C SUPPLY CURRENT (ma) (NOTE ) LOAD CURRENT (ma) LOAD CURRENT (ma) FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT FIGURE. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT FN9 Rev. Page of January,

7 ICLS, ICLA Typical Performance Curves See Figure, ICLS Test Circuit on page ) and Figure ICLA Test Circuit on page (Continued) OUTPUT RESISTANCE (Ω) V = V T A = C I = ma C = C = mf C = C = mf C = C = mf k k k OSCILLATOR FREQUENCY (Hz) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY NOTE:. These curves include, in the supply current, that current fed directly into the load R L from the V (see Figure ). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICLS and ICLA, goes to the negative side of the load. Ideally, V OUT V IN, I S I L, so V IN x I S V OUT x I L. C µf V ICLS C µf I L I S V (V) R L VOUT NOTE: For large values of C OSC (>pf), the values of C and C should be increased to µf. FIGURE. ICLS TEST CIRCUIT C µf ICLA NOTE: For large values of C OSC (>pf) the values of C and C should be increased to F. FIGURE. ICLA TEST CIRCUIT C OSC (NOTE) C µf I S V (V) I L R L V OUT FN9 Rev. Page of January,

8 ICLS, ICLA Detailed Description The ICLS and ICLA contain all the necessary circuitry to complete a negative voltage converter, with the exception of two external capacitors, which may be inexpensive µf polarized electrolytic types. The mode of operation of the device may best be understood by considering Figure, which shows an idealized negative voltage converter. Capacitor C is charged to a voltage, V, for the half cycle, when switches S and S are closed. (Note: Switches S and S are open during this half cycle). During the second half cycle of operation, switches S and S are closed, with S and S open, thereby shifting capacitor C to C such that the voltage on C is exactly V, assuming ideal switches and no load on C. The ICLS and ICLA approach this ideal situation more closely than existing nonmechanical circuits. S S V IN C S S V OUT = V IN FIGURE. IDEALIZED NEGATIVE VOLTAGE CONVERTER In the ICLS and ICLA, the four switches of Figure are MOS power switches; S is a PChannel device; and S, S and S are NChannel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S and S must always remain reverse biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit startup, and under output short circuit conditions (V OUT = V), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. This problem is eliminated in the ICLS and ICLA by a logic network that senses the output voltage (V OUT ) together with the level translators, and switches the substrates of S and S to the correct level to maintain necessary reverse bias. The voltage regulator portion of the ICLS and ICLA is an integral part of the antilatchup circuitry; however, its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation, the LV pin should be connected to GND, thus disabling the regulator. For supply voltages greater than.v, the LV terminal must be left open to ensure latchupproof operation and to prevent device damage. C Theoretical Power Efficiency Considerations In theory, a voltage converter can approach % efficiency if certain conditions are met:. The drive circuitry consumes minimal power.. The output switches have extremely low ON resistance and virtually no offset.. The impedance of the pump and reservoir capacitors are negligible at the pump frequency. The ICLS and ICLA approach these conditions for negative voltage conversion if large values of C and C are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined as shown in Equation : E = C V V (EQ. ) where V and V are the voltages on C during the pump and transfer cycles. If the impedances of C and C are relatively high at the pump frequency (see Figure ) compared to the value of R L, there will be a substantial difference in the voltages, V and V. Therefore it is not only desirable to make C as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C in order to achieve maximum efficiency of operation. Do s and Don ts. Do not exceed maximum supply voltages.. Do not connect LV terminal to GND for supply voltage greater than.v.. Do not short circuit the output to V supply for supply voltages above.v for extended periods; however, transient conditions including startup are okay.. When using polarized capacitors, the terminal of C must be connected to pin of the ICLS and ICLA, and the terminal of C must be connected to GND.. If the voltage supply driving the ICLS and ICLA has a large source impedance ( to ), then a.µf capacitor from pin to ground may be required to limit the rate of rise of input voltage to less than V/µs.. If the input voltage is higher than V and it has a rise rate more than V/µs, an external Schottky diode from V OUT to CAP is needed to prevent latchup (triggered by forward biasing Q s body diode) by keeping the output (pin ) from going more positive than CAP (pin ).. User should ensure that the output (pin ) does not go more positive than GND (pin ). Device latchup will occur under these conditions. To provide additional protection, a N9 or similar diode placed in parallel with C will prevent the device from latching up under these conditions, when the load on V OUT creates a path to pull up V OUT before the IC is active (anode pin, cathode pin ). FN9 Rev. Page of January,

9 ICLS, ICLA Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the ICLS and ICLA for generation of negative supply voltages. Figure shows typical connections to provide a negative supply where a positive supply of.v to V is available. Keep in mind that pin (LV) is tied to the supply negative (GND) for supply voltage below.v. µf ICLS ICLA The output characteristics of the circuit in Figure can be approximated by an ideal voltage source in series with a resistance as shown in Figure B. The voltage source has a value of (V). The output impedance (R O ) is a function of the ON resistance of the internal MOS switches (shown in Figure ), the switching frequency, the value of C and C, and the ESR (equivalent series resistance) of C and C. A good first order approximation for R O is shown in Equation : Combining the four R SWX terms as R SW, we see in Equation that: µf V OUT = V V R SW, the total switch resistance, is a function of supply voltage and temperature (see the output source resistance graphs, Figures,, and ), typically at C and V. Careful selection of C and C will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the /(f PUMP x C ) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the /(f PUMP x C ) term, but may have the side effect of a net increase in output impedance when C > µf and is not long enough to fully V R O A. B. FIGURE. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT EQUIVALENT VOUT R R SW R SW ESR C R SW R SW ESR C ESR f PUMP C C f OSC f PUMP = R SWX = MOSFET Switch Resistance (EQ. ) R xr SW xesr f PUMP C C ESR C (EQ. ) charge the capacitors every cycle. Equation shows a typical application where f OSC = khz and C = C = C = µf: R x xesr ESR C C R ESR C Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of, a high value could potentially swamp out a low /f PUMP x C term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as. Output Ripple ESR also affects the ripple voltage seen at the output. The peaktopeak output ripple voltage is given by Equation : A low ESR capacitor will result in a higher performance output. (EQ. ) V RIPPLE ESR f PUMP C C I OUT (EQ. ) Paralleling Devices Any number of ICLS and ICLA voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C, serves all devices, while each device requires its own pump capacitor, C. The resultant output resistance is approximated in Equation : R OUT of ICLS R OUT = n number of devices (EQ. ) Cascading Devices The ICLS and ICLA may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is devices for light loads. The output voltage is defined as shown in Equation : V OUT = nv IN (EQ. ) where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICLS and ICLA R OUT values. Changing the ICLS and ICLA Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to alter the oscillator frequency. This can be achieved simply by one of several methods. By connecting the Boost Pin (Pin ) to V, the oscillator charge and discharge current is increased and, hence, the oscillator frequency is increased by approximately. times. The result is a decrease in the output impedance and ripple. FN9 Rev. Page 9 of January,

10 ICLS, ICLA This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller capacitors, such as.µf, can be used in conjunction with the Boost Pin to achieve similar output currents compared to the device free running with C = C = µf or µf. (see Figure ). Increasing the oscillator frequency can also be achieved by overdriving the oscillator from an external clock, as shown in Figure. In order to prevent device latchup, a k resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a k pullup resistor to V supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be onehalf of the clock frequency. Output transitions occur on the positive going edge of the clock. Positive Voltage Doubling The ICLS and ICLA may be employed to achieve positive voltage doubling using the circuit shown in Figure. In this application, the pump inverter switches of the ICLS and ICLA are used to charge C to a voltage level of V V F, where V is the supply voltage and V F is the forward voltage on C, plus the supply voltage (V) is applied through diode D to capacitor C. The voltage thus created on C becomes (V) (V F ) or twice the supply voltage minus the combined forward voltage drops of diodes D and D. The source impedance of the output (V OUT ) will depend on the output current, but for V = V and an output current of ma, it will be approximately. V V V µf ICLS ICLA kω µf V OUT CMOS GATE ICLS ICLA D D V OUT = (V) (V F ) C C NOTE: D AND D CAN BE ANY SUITABLE DIODE. FIGURE. EXTERNAL CLOCKING It is also possible to increase the conversion efficiency of the ICLS and ICLA at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C ) and reservoir (C ) capacitors; this is overcome by increasing the values of C and C by the same factor by which the frequency has been reduced. For example, the addition of a pf capacitor between pin (OSC and V) will lower the oscillator frequency to khz from its nominal frequency of khz (a multiple of ), and thereby necessitate a corresponding increase in the value of C and C (from µf to µf). V FIGURE. POSITIVE VOLTAGE DOUBLER Combined Negative Voltage Conversion and Positive Supply Doubling Figure 9 combines the functions shown in Figure and Figure to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be suitable, for example, for generating 9V and V from an existing V supply. In this instance, capacitors C and C perform the pump and reservoir functions, respectively, for negative voltage generation, while capacitors C and C are pump and reservoir, respectively, for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher, due to the finite impedance of the common charge pump driver at pin of the device. C ICLS ICLA C OSC C V OUT FIGURE. LOWERING OSCILLATOR FREQUENCY FN9 Rev. Page of January,

11 ICLS, ICLA C ICLS ICLA C V D D C C V OUT = V IN V OUT = (V) (V FD ) (V FD ) R L µf V OUT = V V ICLS ICLA µf R L µf V V D FIGURE 9. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER Voltage Splitting The bidirectional characteristics can also be used to split a high supply in half, as shown in Figure. The combined load will be evenly shared between the two sides, and a high value resistor to the LV pin ensures startup. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure, V can be converted, via. and., to a nominal V, although with rather high series output resistance ( ). FIGURE. SPLITTING A SUPPLY IN HALF Regulated Negative Voltage Supply In some cases, the output impedance of the ICLS and ICLA can be a problem, particularly if the load current varies substantially. The circuit of Figure can be used to overcome this by controlling the input voltage, via an ICL lowpower CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICLS s and ICLA s output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICLS and ICLA, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provide an output impedance of less than to a load of ma. Other Applications Further information on the operation and use of the ICLS and ICLA may be found in application note AN, Principles and Applications of the ICL CMOS Voltage Converter. V k k k k V ICL µf ICL9 µf ICLS ICLA V OUT k k VOLTAGE ADJUST µf FIGURE. REGULATING THE OUTPUT VOLTAGE FN9 Rev. Page of January,

12 ICLS, ICLA DualInLine Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B C A N N/ B D e D E B A. (.) M C A A L B S NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M9.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm).. E and e A are measured with the leads constrained to be perpendicular to datum C.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E., E., E., E., E. will have a B dimension of.. inch (..mm). A e C E C L e A C e B E. (JEDEC MSBA ISSUE D) LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.. A..9 A B.... B...., C.... D D.. E.... E.... e. BSC. BSC e A. BSC. BSC e B..9 L...9. N 9 Rev. /9 Copyright Intersil Americas LLC 999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN9 Rev. Page of January,

13 ICLS, ICLA Package Outline Drawing M. LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, / DETAIL "A". (.). (.) INDEX AREA. (.). (.). (.). (.). (.). (.) x TOP VIEW SIDE VIEW B. (.).9 (.). (.) SEATING PLANE. (.9). (.9). (.9). (.). (.). (.) C. (.).(.).(.).(.).(.).(.) SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES:. Dimensioning and tolerancing per ANSI Y.M99.. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (. inch) per side.. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. Terminal numbers are shown for reference only.. The lead width as measured.mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.. This outline conforms to JEDEC publication MSAA ISSUE C. FN9 Rev. Page of January,