DATASHEET HI-303. Features. Functional Diagram. Applications Pinout Switch States Shown For A Logic 1 Input. Ordering Information

Transcription

1 TSHEET HI-33 ual, SPT CMOS nalog Switch The HI-33 switch is a monolithic device fabricated using CMOS technology and the Intersil dielectric isolation process. This switch features break-before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation. The HI-33 is TTL compatible and has a logic condition with an input less than.8v and a logic 1 condition with an input greater than V. (See pinouts for switch conditions with a logic 1 input.) Functional iagram IN N P S Features FN312 Rev 1. Oct 1, 21 nalog Signal Range ( 1V Supplies) V Low Leakage at 2 o C p Low Leakage at 12 o C n Low On Resistance at 2 o C Break-Before-Make elay ns Charge Injection pC TTL, CMOS Compatible Symmetrical Switch Elements Low Operating Power (Typ) mW Pb-Free vailable (RoHS Compliant) pplications Pinout Switch States Shown For Logic 1 Input HI-33 (PIP, CERIP, SOIC) TOP VIEW NC S V+ 13 S 12 Sample and Hold (i.e., Low Leakage Switching) Op mp Gain Switching (i.e., Low On Resistance) Portable, Battery Operated Circuits Low Level Switching Circuits ual or Single Supply Systems 1 S 1 IN 1 GN S 2 9 IN 2 8 V- Ordering Information PRT NUMBER TEMP. RNGE ( o C) PCKGE HI to 12 1 Ld CERIP F1.3 PKG. WG. # LOGIC SW1, SW2 SW3, SW HI3-33-Z (See Note) to 7 1 Ld PIP (Pb-free) E1.3 OFF ON 1 ON OFF HI9P33-9Z (See Note) - to 8 1 Ld SOIC (Pb-free) M1.1 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEEC J ST-2C. FN312 Rev 1. Page 1 of 12 Oct 1, 21

2 HI-33 Schematic iagrams V+ MN1B MPB MN2B MN3B IN MPB MNB OUT MN6B MP3B MP2B MP1B SWITCH CELL V- V+ 2 MP1 MP2 MP3 MP MP MP6 MP7 MP8 LOGIC IN 2 1 MN1 MN2 MN3 MN MN MN6 MN7 MN8 GN V- IGITL INPUT BUFFER N LEVEL SHIFTER SWITCH CELL RIVER (ONE PER SWITCH CELL) FN312 Rev 1. Page 2 of 12 Oct 1, 21

3 HI-33 bsolute Maximum Ratings Voltage Between Supplies (V+ to V-) V ( 22V) igital Input Voltage (V+) +V to (V-) -V nalog Input Voltage (V+) +1.V to (V-) -1.V Typical erating Factor m/MHz Increase in ICCOP ES Classification Class 1 Operating Conditions Temperature Range HI o C to 12 o C HI o C to 7 o C HI o C to 8 o C Thermal Information Thermal Resistance (Typical, Note 1) J ( o C/W) JC ( o C/W) CERIP Package PIP Package N/ SOIC Package N/ Maximum Junction Temperature Ceramic Packages o C Plastic Packages o C Maximum Storage Temperature Range o C to 1 o C Maximum Lead Temperature (Soldering 1s) o C (SOIC - Lead Tips Only) CUTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. J is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Supplies = +1V, -1V; V IN = Logic Input. V IN - for Logic 1 = V, for Logic =.8V. Unless Otherwise Specified PRMETER TEMP ( o C) -2 -, -9 MIN TYP MX MIN TYP MX UNITS YNMIC CHRCTERISTICS Switch ON Time, t ON ns Switch OFF Time, t OFF ns Break-Before-Make elay, t OPEN ns Charge Injection Voltage, V (Note 7) mv OFF Isolation (Note 6) db Input Switch Capacitance, C S(OFF) pf Output Switch Capacitance, C (OFF) pf Output Switch Capacitance, C (ON) pf igital Input Capacitance, C IN pf IGITL INPUT CHRCTERISTICS Input Low Level, V INL Full V Input High Level, V INH (Note 1) Full V Input Leakage Current (Low), I INL (Note ) Full Input Leakage Current (High), I INH (Note ) Full NLOG SWITCH CHRCTERISTICS nalog Signal Range Full V ON Resistance, r ON (Note 2) Full OFF Input Leakage Current, I S(OFF) (Note 3) n Full n OFF Output Leakage Current, I (OFF) (Note 3) n Full n ON Leakage Current, I (ON) (Note ) n Full n FN312 Rev 1. Page 3 of 12 Oct 1, 21

4 HI-33 Electrical Specifications Supplies = +1V, -1V; V IN = Logic Input. V IN - for Logic 1 = V, for Logic =.8V. Unless Otherwise Specified (Continued) PRMETER TEMP ( o C) -2 -, -9 MIN TYP MX MIN TYP MX UNITS POWER SUPPLY CHRCTERISTICS Current, I+ (Note 8) m Full m Current, I- (Note 8) Full Current, I+ (Note 9) Full Current, I- (Note 9) Full NOTES: 2. V S = 1V, I OUT = 1m. On resistance derived from the voltage measured across the switch under these conditions. 3. V S = 1V, V = 1V.. V S = V = 1V.. The digital inputs are diode protected MOS gates and typical leakages of 1n or less can be expected. 6. V S = 1V RMS, f = khz, C L = 1pF, R L = 1K. 7. V S = V, C L = 1nF, Logic rive = V pulse. Switches are symmetrical; S and may be interchanged. Charge Injection = Q = C L x V. 8. V IN = V (one input, all other inputs = V). 9. V IN =.8V (all inputs). 1. To drive from TL/TTL circuits, pullup resistors to +V supply are recommended. Test Circuits and Waveforms 1V V+ LOGIC 1 = SWITCH ON S V S = +3V R L 3 V O SWITCH OUTPUT C L 33pF LOGIC INPUT V V S V INH % % LOGIC INPUT GN SWITCH TYPE V- -1V V INH V SWITCH OUTPUT t ON 9% t OFF 1% HI-33 V FIGURE 1. TEST CIRCUIT FIGURE 1B. MESUREMENT POINTS FIGURE 1. SWITCH t ON N t OFF FN312 Rev 1. Page of 12 Oct 1, 21

5 HI-33 Test Circuits and Waveforms (Continued) R GEN = V GEN S IN +1V V+ R L 1k C L 1pF LOGIC INPUT (V) 6 2 LOGIC INPUT V LOGIC GN V- -1V TIME ( s) FIGURE 2. TEST CIRCUIT FIGURE 2B. TTL LOGIC INPUT OUTPUT VOLTGE (V) 1 V GEN = 1V (NOTE 11) OUTPUT VOLTGE (V) V GEN = V TIME ( s) FIGURE 2C. V NLOG = 1V TIME ( s) FIGURE 2. V NLOG = V OUTPUT VOLTGE (V) - V GEN = V OUTPUT VOLTGE (V) - V GEN = -V TIME ( s) TIME ( s) FIGURE 2E. V NLOG = V FIGURE 2F. V NLOG = -V FN312 Rev 1. Page of 12 Oct 1, 21

6 HI-33 Test Circuits and Waveforms (Continued) OUTPUT VOLTGE (V) - -1 V GEN = -1V TIME ( s) FIGURE 2G. V NLOG = -1V NOTE: 11. If R GEN, R L or C L is increased, there will be proportional increases in rise and/or fall RC times. FIGURE 2. SWITCHING WVEFORMS FOR VRIOUS NLOG INPUT VOLTGES S 1 V S1 = +3V V S2 = +3V S 2 1V V+ 1 2 OUT 1 OUT 2 LOGIC INPUT V LOGIC 1 = SWITCH ON V INH R L1 = R L2 = 3 C L1 = C L2 = 33pF LOGIC INPUT GN SWITCH TYPE V- -1V R L2 C L2 R L1 V INH C L1 V SWITCH OUTPUTS t OPEN % % OUT 1 OUT 2 % % V t OPEN HI-33 V FIGURE 3. TEST CIRCUIT FIGURE 3B. MESUREMENT POINTS FIGURE 3. BREK-BEFORE-MKE ELY (t OPEN ) Typical Performance Curves RIN TO SOURCE ON RESISTNCE ( ) V+ = +1V, V- = -1V 12 o C 2 o C - o C RIN VOLTGE (V) RIN TO SOURCE ON RESISTNCE ( ) 8 6 T = 2 o C 2 V+ = +1V, V- = -1V B V+ = +1V, V- = -1V C V+ = +7.V, V- = -7.V V+ = +V, V- = -V RIN VOLTGE (V) C B FIGURE. r S(ON) vs V FIGURE. r S(ON) vs V FN312 Rev 1. Page 6 of 12 Oct 1, 21

7 HI-33 Typical Performance Curves (Continued) 1 V+ = +1V, V- = -1V 1 V+ = +1V, V- = -1V POWER ISSIPTION (mw) 1 1. T = 2 o C, V S = 1V, R L = 2K OFF ISOLTION (db) R L = 1k R L = 1 C LO = 3pF, V S = 1V RMS K 1K 1K 1M LOGIC SWITCHING FREQUENCY (% UTY CYCLE) (Hz) FIGURE 6. EVICE POWER ISSIPTION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT) FREQUENCY (Hz) FIGURE 7. OFF ISOLTION vs FREQUENCY 1. V+ = +1V, V- = -1V 1. V+ = +1V, V- = -1V V = V S = 1V SOURCE OR RIN OFF LEKGE CURRENT (n) 1..1 I (ON) (n) TEMPERTURE ( o C) TEMPERTURE ( o C) FIGURE 8. I S(OFF) OR I (OFF) vs TEMPERTURE* FIGURE 9. I (ON) vs TEMPERTURE* * The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit OUTPUT ON CPCITNCE (pf) 3 INPUT CPCITNCE (pf) 12 8 TRNSITION (INETERMINTE UE TO CTIVE INPUT) RIN VOLTGE (V) FIGURE 1. OUTPUT ON CPCITNCE vs RIN VOLTGE INPUT VOLTGE (V) FIGURE 11. IGITL INPUT CPCITNCE vs INPUT VOLTGE FN312 Rev 1. Page 7 of 12 Oct 1, 21

8 HI-33 Typical Performance Curves (Continued) 3 V+ = +1V, V- = -1V V INH =.V, V INL = V 3 t ON V+ = +1V, T = 2 o C V INH = V, V INL = V SWITCHING TIME (ns) 2 1 t ON t OFF SWITCHING TIME (ns) 2 1 t OFF TEMPERTURE ( o C) 1 1 NEGTIVE SUPPLY (V) FIGURE 12. SWITCHING TIME vs TEMPERTURE FIGURE 13. SWITCHING TIME vs NEGTIVE SUPPLY VOLTGE SWITCHING TIME/BREK-BEFORE-MKE TIME ( s) t OPEN ONLY t OFF V- = -1V, T = 2 o C V INH =.V, V INL = V t ON 1 1 INPUT SWITCHING THRESHOL (V) V- = -1V, T = 2 o C 1 1 POSITIVE SUPPLY VOLTGE (V) POSITIVE SUPPLY VOLTGE (V) FIGURE 1. SWITCHING TIME N BREK-BEFORE-MKE TIME vs POSITIVE SUPPLY VOLTGE FIGURE 1. INPUT SWITCHING THRESHOL vs POSITIVE SUPPLY VOLTGE FN312 Rev 1. Page 8 of 12 Oct 1, 21

9 HI-33 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. TE REVISION CHNGE October 1, 21 FN Updated Ordering Information Table on page 1. - dded Revision History. - dded bout Intersil Verbiage. - Updated PO M1.1 to latest revision changes are as follow: dded land pattern and moved dimensions from table onto drawing. bout Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil mericas LLC ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN312 Rev 1. Page 9 of 12 Oct 1, 21

10 HI-33 ual-in-line Plastic Packages (PIP) INEX RE BSE PLNE SETING PLNE 1 B1 -C- -- N N/2 B e 1 E1 NOTES: 1. Controlling imensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. imensioning and tolerancing per NSI Y1.M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 9.. imensions, 1 and L are measured with the package seated in JEEC seating plane gauge GS-3.., 1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 inch (.2mm). 6. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. ambar protrusions shall not exceed.1 inch (.2mm). 9. N is the maximum number of terminal positions. 1. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E2.6 will have a B1 dimension of.3 -. inch ( mm). -B- 1.1 (.2) M C 2 L B S e C E C L e C e B E1.3 (JEEC MS-1- ISSUE ) 1 LE UL-IN-LINE PLSTIC PCKGE INCHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES B B C E E e.1 BSC 2. BSC - e.3 BSC 7.62 BSC 6 e B L N Rev. 12/93 FN312 Rev 1. Page 1 of 12 Oct 1, 21

11 HI-33 Ceramic ual-in-line Frit Seal Packages (CERIP) BSE PLNE SETING PLNE S1 b2 ccc M bbb S b C - B Q -C- -B- C - B S e S NOTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. imensions b1 and c1 apply to lead base metal only. imension M applies to lead plating and finish thickness.. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.. This dimension allows for off-center lid, meniscus, and glass overrun. 6. imension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. imensioning and tolerancing per NSI Y1.M Controlling dimension: INCH. E L M c1 e/2 S S aaa M C - B LE FINISH BSE METL b1 M (b) SECTION - S e c S (c) F1.3 MIL-ST-183 GIP1-T1 (-1, CONFIGURTION ) 1 LE CERMIC UL-IN-LINE FRIT SEL PCKGE INCHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES b b b b c c E e.1 BSC 2. BSC - e.3 BSC 7.62 BSC - e/2.1 BSC 3.81 BSC - L Q S o 1 o 9 o 1 o - aaa bbb ccc M , 3 N Rev. /9 FN312 Rev 1. Page 11 of 12 Oct 1, 21

12 HI-33 Package Outline rawing M1.1 1 LE NRROW BOY SMLL OUTLINE PLSTIC PCKGE Rev 1, 1/ C -B 2X ETIL"".22± C 2X PIN NO.1 I MRK B.2MC-B C 2X (.3) x ± TOP VIEW.1 C 1.7 MX 1.2 MIN H GUGE PLNE C SETING PLNE.1 C SIE VIEW ETIL "" (1.27) (.6) (.) (1.) NOTES: 1. imensions are in millimeters. imensions in ( ) for Reference Only. 2. imensioning and tolerancing conform to MSEY1.m atums and B to be determined at atum H.. imension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.2mm per side.. The pin #1 indentifier may be either a mold or mark feature. 6. oes not include dambar protrusion. llowable dambar protrusion shall be.1mm total in excess of lead width at maximum condition. 7. Reference to JEEC MS-12-B. TYPICL RECOMMENE LN PTTERN FN312 Rev 1. Page 12 of 12 Oct 1, 21