DATASHEET CD4013BMS. Pinout. Features. Functional Diagram. Applications. Description. CMOS Dual D -Type Flip-Flop. FN3080 Rev 0.

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1 DATASHEET CD013BMS CMOS Dual D -Type Flip-Flop FN300 Rev 0.00 Features High-Voltage Type (0V Rating) Set-Reset Capability Static Flip-Flop Operation - Retains State Indefinitely With Clock Level Either High Or Low Medium-Speed Operation - 1 MHz (typ.) Clock Toggle Rate at Standardized Symmetrical Output Characteristics 100% Tested for Quiescent Current at 0V Maximum Input Current of 1 A at 1V Over Full Package Temperature Range; 100nA at 1V and +5 o C Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - V at VDD = -.5V at VDD = 15V 5V, and 15V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices Pinout Q1 1 Q1 OCK 1 3 RESET 1 D1 5 SET 1 VSS 7 Functional Diagram SET 1 5 D1 3 OCK VDD Q Q OCK RESET D SET VDD 1 Q1 F/F1 1 Q1 Applications Registers Counters Control Circuits Description CD013BMS consists of two identical, independent data type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively. RESET 1 SET 9 D 11 OCK RESET 10 F/F 7 VSS 1 13 Q Q The CD013BMS is supplied in these 1 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack HQ H1B H3W FN300 Rev 0.00 Page 1 of 9

2 Absolute Maximum Ratings DC Supply Voltage Range, (VDD) V to +0V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to VDD +0.5V DC Input Current, Any One Input 10mA Operating Temperature Range to +15 o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to +150 o C Lead Temperature (During Soldering) o C At Distance 1/1 1/3 Inch (1.59mm 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance ja jc Ceramic DIP and FRIT Package o C/W 0 o C/W Flatpack Package o C/W 0 o C/W Maximum Package Power Dissipation (PD) at +15 o C For TA = - to +100 o C (Package Type D, F, K) mW For TA = +100 o C to +15 o C (Package Type D, F, K)..... Derate Linearity at 1mW/ o C to 00mW Device Dissipation per Output Transistor mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 0V, VIN = VDD or GND 1 +5 o C - A +15 o C - 00 A VDD = 1V, VIN = VDD or GND A Input Leakage Current IIL VIN = VDD or GND VDD = o C na +15 o C na VDD = 1V na Input Leakage Current IIH VIN = VDD or GND VDD = o C na +15 o C na VDD = 1V na Output Voltage VOL15 VDD = 15V, No Load 1,, 3 +5 o C, +15 o C, mv Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1,, 3 +5 o C, +15 o C, V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.V 1 +5 o C ma Output Current (Sink) IOL10 VDD =, VOUT = 0.5V 1 +5 o C 1. - ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +5 o C ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V 1 +5 o C ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1 +5 o C ma Output Current (Source) IOH10 VDD =, VOUT = 9.5V 1 +5 o C ma Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +5 o C ma N Threshold Voltage VNTH VDD =, ISS = -10 A 1 +5 o C V P Threshold Voltage VPTH VSS = 0V, IDD = 10 A 1 +5 o C 0.7. V Functional F VDD =.V, VIN = VDD or GND 7 +5 o C VOH > VOL < V VDD = 0V, VIN = VDD or GND 7 +5 o C VDD/ VDD/ VDD = 1V, VIN = VDD or GND A +15 o C VDD = 3V, VIN = VDD or GND B - Input Voltage Low (Note ) VIL VDD = 5V, VOH >.5V, VOL < 0.5V 1,, 3 +5 o C, +15 o C, V Input Voltage High (Note ) VIH VDD = 5V, VOH >.5V, VOL < 0.5V 1,, 3 +5 o C, +15 o C, V Input Voltage Low (Note ) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1,, 3 +5 o C, +15 o C, - - V Input Voltage High (Note ) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented.. Go/No Go test with limits applied to inputs 1,, 3 +5 o C, +15 o C, V 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. FN300 Rev 0.00 Page of 9

3 TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1, ) SUBGROUPS TEMPERATURE MIN MAX UNITS TPHL1 VDD = 5V, VIN = VDD or GND 9 +5 o C ns Clock to Q, Q TPLH1 10, o C, ns TPHL VDD = 5V, VIN = VDD or GND 9 +5 o C - 00 ns Set to Q, Reset to Q 10, o C, ns TPLH VDD = 5V, VIN = VDD or GND 9 +5 o C ns Set to Q, Reset to Q 10, o C, ns Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +5 o C - 00 ns Clock to Q, Q TTLH 10, o C, ns Maximum Clock Input Frequency F VDD = 5V, VIN = VDD or GND 9 +5 o C MHz 10, o C, - 3.5/ MHz NOTES: 1. VDD = 5V, = 50pF, RL = 00K. - and +15 o C limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND 1, -, +5 o C A +15 o C - 30 A VDD =, VIN = VDD or GND 1, -, +5 o C -.0 A +15 o C - 0 A VDD = 15V, VIN = VDD or GND 1, -, +5 o C -.0 A +15 o C - 10 A Output Voltage VOL VDD = 5V, No Load 1, +5 o C, +15 o C, - Output Voltage VOL VDD =, No Load 1, +5 o C, +15 o C, - Output Voltage VOH VDD = 5V, No Load 1, +5 o C, +15 o C, - Output Voltage VOH VDD =, No Load 1, +5 o C, +15 o C, mv - 50 mv.95 - V V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.V 1, +15 o C ma ma Output Current (Sink) IOL10 VDD =, VOUT = 0.5V 1, +15 o C ma ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, +15 o C. - ma -. - ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V 1, +15 o C ma ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1, +15 o C ma ma FN300 Rev 0.00 Page 3 of 9

4 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Output Current (Source) IOH10 VDD =, VOUT = 9.5V 1, +15 o C ma ma Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, +15 o C - -. ma ma Input Voltage Low VIL VDD =, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, - Input Voltage High VIH VDD =, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, V +7 - V Clock to Q, Q TPHL1 TPLH1 VDD = 1,, 3 +5 o C ns VDD = 15V 1,, 3 +5 o C - 90 ns Set to Q Reset to Q Set to Q Reset to Q TPHL VDD = 1,, 3 +5 o C ns VDD = 15V 1,, 3 +5 o C - 10 ns TPLH VDD = 1,, 3 +5 o C ns VDD = 15V 1,, 3 +5 o C - 90 ns Transition Time Clock to Q, Q TTHL TTLH VDD = 1,, 3 +5 o C ns VDD = 15V 1,, 3 +5 o C - 0 ns Maximum Clock Input Frequency F VDD = 1,, 3 +5 o C - MHz VDD = 15V 1,, 3 +5 o C 1 - MHz Minimum Data Setup Time TS VDD = 5V 1,, 3 +5 o C - 0 ns VDD = 1,, 3 +5 o C - 0 ns VDD = 15V 1,, 3 +5 o C - 15 ns Minimum Clock Pulse Width TW VDD = 5V 1,, 3 +5 o C - 10 ns VDD = 1,, 3 +5 o C - 0 ns VDD = 15V 1,, 3 +5 o C - 0 ns Minimum Set or Reset Pulse Width TW VDD = 5V, 3 +5 o C - 10 ns VDD =, 3 +5 o C - 0 ns VDD = 15V, 3 +5 o C - 50 ns Input Capacitance CIN Any Input 1, +5 o C pf NOTES: 1. All voltages referenced to device GND.. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. = 50pF, RL = 00K, Input TR, TF < 0ns. TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 0V, VIN = VDD or GND 1, +5 o C A N Threshold Voltage VNTH VDD =, ISS = -10 A 1, +5 o C V N Threshold Voltage VNTH VDD =, ISS = -10 A 1, +5 o C - 1 V Delta P Threshold Voltage VPTH VSS = 0V, IDD = 10 A 1, +5 o C 0.. V FN300 Rev 0.00 Page of 9

5 TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS P Threshold Voltage Delta VPTH VSS = 0V, IDD = 10 A 1, +5 o C - 1 V Functional F VDD = 1V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND 1 +5 o C VOH > VDD/ Time TPHL TPLH NOTES: PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE 1. All voltages referenced to device GND.. = 50pF, RL = 00K, Input TR, TF < 0ns. VOL < VDD/ VDD = 5V 1,, 3, +5 o C x +5 o C Limit 3. See Table for +5 o C limit.. Read and Record MIN MAX UNITS V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +5 O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD 0. A Output Current (Sink) IOL5 0% x Pre-Test Reading Output Current (Source) IOH5A 0% x Pre-Test Reading TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-3 METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 100% 500 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 500 1, 7, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) 100% 500 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 100% 500 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 500 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 100% 500 1, 7, 9, Deltas Final Test 100% 500, 3, A, B, 10, 11 Group A Sample ,, 3, 7, A, B, 9, 10, 11 Group B Subgroup B-5 Sample ,, 3, 7, A, B, 9, 10, 11, Deltas Subgroups 1,, 3, 9, 10, 11 Subgroup B- Sample , 7, 9 Group D Sample ,, 3, A, B, 9 Subgroups 1, 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-3 TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup , 7, 9 Table 1, 9 Table TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V -0.5V Static Burn-In 1 1,, 1, (Note 1) Static Burn-In (Note 1) 1,, 1, , -11, 1 50kHz 5kHz FN300 Rev 0.00 Page 5 of 9

6 TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 5kHz Dynamic Burn- In (Note 1) Irradiation (Note ) -, -, ,, 1, 13 3, 11 5, 9 1,, 1, , -11, 1 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 1V 0.5V. Each pin except VDD and GND will have a series resistor of 7K 5%; Group E, Subgroup, sample size is dice/wafer, 0 failures, VDD = 0.5V Logic Diagram *(10) RESET MASTER SECTION p SLAVE SECTION *5(9) DATA p TG n p TG n p TG n TG n *() SET *3(11) Q 1(13) BUFFERED OUTPUTS Q (1) 1 7 VDD VSS * All inputs are protected by CMOS protection network FIGURE 1. ONE OF TWO IDENTICAL FLIP-FLOPS TRUTH TABLE * D R S Q Q X 0 0 Q Q X X No Change X X X X Logic 0 = Low Logic 1 = High * = Level change X = Don t care N(N) = FF1/FF terminal assignments FN300 Rev 0.00 Page of 9

7 Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 5V OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V - -15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V - -15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHAR- ACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHAR- ACTERISTICS FN300 Rev 0.00 Page 7 of 9

8 Typical Performance Characteristics (Continued) PROPAGATION DELAY TIME (tphl, tplh) (ns) SUPPLY VOLTAGE (VDD) = 5V 15V PROPAGATION DELAY TIME (tphl, tplh) (ns) SUPPLY VOLTAGE (VDD) = 5V 15V LOAD CAPACITANCE () (pf) LOAD CAPACITANCE () (pf) FIGURE. TYPICAL PROPAGATION DELAY TIME vs LOAD CA- PACITANCE (OCK OR SET TO Q, OCK OR RE- SET TO Q) FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CA- PACITANCE (SET TO Q OR RESET TO Q) OCK FREQUENCY (f) (MHz) tr, tf = 5ns = 50pF SUPPLY VOLTAGE (VDD) (V) DISSIPATION PER DEVICE (PD) ( W) SUPPLY VOLTAGE (VDD) = 15V 5V INPUT tr = tf = 0ns INPUT FREQUENCY (ft) (HZ) = 50pF = 15pF FIGURE. TYPICAL MAXIMUM OCK FREQUENCY vs SUPPLY VOLTAGE FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY FN300 Rev 0.00 Page of 9

9 Chip Dimensions and Pad Layout CONTACT YOUR LOCAL SALES OFFICE FOR Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ 1kÅ, AL. PASSIVATION: 10.kÅ - 15.kÅ, Silane BOND PADS: 0.00 inches X 0.00 inches MIN DIE THICKNESS: inches inches Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN300 Rev 0.00 Page 9 of 9