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1 SCLS107E DECEMBER 1982 REVISED SEPTEMBER 2003 Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max I CC Typical t pd = 15 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µa Max Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception description/ordering information SN54HC138...J OR W PACKAGE SN74HC D, DB, N, NS, OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND V CC Y0 Y1 Y2 Y3 Y4 Y5 Y6 SN54HC FK PACKAGE (TOP VIEW) The HC138 devices are designed to be used in high-performance memory-decoding or datarouting applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. C G2A NC G2B G1 B A NC V CC Y Y7 GND NC Y6 Y5 NC No internal connection Y1 Y2 NC Y3 Y4 TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube of 25 SN74HC138N SN74HC138N Tube of 40 SN74HC138D SOIC D Reel of 2500 SN74HC138DR HC138 Reel of 250 SN74HC138DT 40 C to 85 C SOP NS Reel of 2000 SN74HC138NSR HC138 SSOP DB Reel of 2000 SN74HC138DBR HC138 Tube of 90 SN74HC138PW TSSOP PW Reel of 2000 SN74HC138PWR HC138 Reel of 250 SN74HC138PWT CDIP J Tube of 25 SNJ54HC138J SNJ54HC138J 55 C to 125 C CFP W Tube of 150 SNJ54HC138W SNJ54HC138W LCCC FK Tube of 55 SNJ54HC138FK SNJ54HC138FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 SCLS107E DECEMBER 1982 REVISED SEPTEMBER 2003 description/ordering information (continued) The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. FUNCTION TABLE INPUTS ENABLE SELECT OUTPUTS G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 SCLS107E DECEMBER 1982 REVISED SEPTEMBER 2003 logic diagram (positive logic) 15 Y0 A 1 14 Y1 B 2 13 Y2 C 3 12 Y3 11 Y4 G Y5 G2A Y6 Y7 G2B 5 Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note 1) ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note 1) ±20 ma Continuous output current, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 2): D package C/W DB package C/W N package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS

4 SCLS107E DECEMBER 1982 REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC138 SN74HC138 MIN NOM MAX MIN NOM MAX VCC Supply voltage V VCC = 2 V VIH High-level input voltage VCC = 4.5 V V VCC = 6 V VCC = 2 V VIL Low-level input voltage VCC = 4.5 V V VCC = 6 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V t/ v Input transition rise/fall time VCC = 4.5 V ns VCC = 6 V TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VOL VI = VIH or VIL VI = VIH or VIL TA = 25 C SN54HC138 SN74HC138 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa 4.5 V UNIT UNIT 6 V V IOH = 4 ma 4.5 V IOH = 5.2 ma 6 V V IOL = 20 µa 4.5 V V V IOL = 4 ma 4.5 V IOL = 5.2 ma 6 V II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 na ICC VI = VCC or 0, IO = 0 6 V µa Ci 2 V to 6 V pf 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 SCLS107E DECEMBER 1982 REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC TA = 25 C SN54HC138 SN74HC138 MIN TYP MAX MIN MAX MIN MAX 2 V A, B, or C Any Y 4.5 V V V Enable Any Y 4.5 V V V tt Any 4.5 V ns 6 V UNIT ns operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 85 pf PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pf (see Note A) Input 50% tplh 50% tphl VCC 0 V LOAD CIRCUIT In-Phase Output 50% 10% 90% 90% tr VOH 50% 10% VOL tf Input 50% 10% 90% 90% tr VCC 50% 10% 0 V tf Out-of-Phase Output tphl 90% 50% 50% 10% 10% tf tplh VOH 90% VOL tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tplh and tphl are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS

6 PACKAGE OPTION ADDENDUM 8-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) VEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC VFA ACTIVE CFP W 16 1 None Call TI Level-NC-NC-NC A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC EA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC FA ACTIVE CFP W 16 1 None Call TI Level-NC-NC-NC JM38510/65802B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/65802BEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC JM38510/65802BFA ACTIVE CFP W 16 1 None Call TI Level-NC-NC-NC SN54HC138J ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SN74HC138D ACTIVE SOIC D Green (RoHS & no Sb/Br) SN74HC138DBR ACTIVE SSOP DB Pb-Free (RoHS) SN74HC138DR ACTIVE SOIC D Green (RoHS & no Sb/Br) SN74HC138DT ACTIVE SOIC D Pb-Free (RoHS) SN74HC138N ACTIVE PDIP N Pb-Free (RoHS) SN74HC138N3 OBSOLETE PDIP N 16 None Call TI Call TI SN74HC138NSR ACTIVE SO NS Pb-Free (RoHS) SN74HC138PW ACTIVE TSSOP PW Pb-Free (RoHS) SN74HC138PWLE OBSOLETE TSSOP PW 16 None Call TI Call TI SN74HC138PWR ACTIVE TSSOP PW Pb-Free (RoHS) SN74HC138PWT ACTIVE TSSOP PW Pb-Free (RoHS) Level-1-260C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM SNJ54HC138FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54HC138J ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SNJ54HC138W ACTIVE CFP W 16 1 None Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. Addendum-Page 1

7 PACKAGE OPTION ADDENDUM 8-Mar-2005 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

10 MECHANICAL DATA MLCC006B OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) (9,09) (7,80) (9,09) A SQ B SQ (11,23) (16,26) (18,78) (23,83) (28,99) (11,63) (16,76) (19,32) (24,43) (29,59) (10,31) (12,58) (12,58) (21,6) (26,6) (11,63) (14,22) (14,22) (21,8) (27,0) (0,51) (0,25) (2,03) (1,63) (0,51) (0,25) (1,40) (1,14) (1,14) (0,89) (0,71) (0,54) (1,27) (1,14) (0,89) / D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX DALLAS, TEXAS 75265

14 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

15 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

16 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2005, Texas Instruments Incorporated

17 This datasheet has been download from: Datasheets for electronics components.

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E DECEMBER 1982 REVISED AUGUST 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption,