SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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1 Wide Operating Voltage Range of 2 V to 6 V Outputs an Drive Up To 10 LSTTL Loads Low Power onsumption, 40-µA Max I Typical t pd = 15 ns ±4-mA Output Drive at 5 V Low Input urrent of 1 µa Max description/ordering information The H74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (LK) pulse. lock triggering occurs at a voltage level and is not directly related to the rise time of LK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 1982 REVISED JULY 2003 SN54H74...J OR W PAKAGE SN74H74... D, DB, N, NS, OR PW PAKAGE (TOP VIEW) 1LK N 1PRE N 1Q 1LR 1D 1LK 1PRE 1Q 1Q GND V 2LR 2D 2LK 2PRE 2Q 2Q SN54H74... FK PAKAGE (TOP VIEW) 1D 1LR N V 2LR D N 2LK N 2PRE 1Q GND N 2Q 2Q TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube of 25 SN74H74N SN74H74N Tube of 50 SN74H74D SOI D Reel of 2500 SN74H74DR H74 Reel of 250 SN74H74DT 40 to 85 SOP NS Reel of 2000 SN74H74NSR H74 SSOP DB Reel of 2000 SN74H74DBR H74 Tube of 90 SN74H74PW TSSOP PW Reel of 2000 SN74H74PWR H74 Reel of 250 SN74H74PWT N No internal connection DIP J Tube of 25 SNJ54H74J SNJ54H74J 55 to 125 FP W Tube of 150 SNJ54H74W SNJ54H74W L FK Tube of 55 SNJ54H74FK SNJ54H74FK Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFIE BOX DALLAS, TEXAS

2 SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 1982 REVISED JULY 2003 logic diagram (positive logic) PRE FUNTION TABLE INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or LR returns to its inactive (high) level. LK TG Q D TG TG TG LR Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V V to 7 V Input clamp current, I IK (V I < 0 or V I > V ) (see Note 1) ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note 1) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±25 ma ontinuous current through V or GND ±50 ma Package thermal impedance, θ JA (see Note 2): D package /W DB package /W N package /W NS package /W PW package /W Storage temperature range, T stg to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD POST OFFIE BOX DALLAS, TEXAS 75265

3 recommended operating conditions (see Note 3) SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 1982 REVISED JULY 2003 SN54H74 SN74H74 MIN NOM MAX MIN NOM MAX V Supply voltage V V = 2 V VIH High-level input voltage V = 4.5 V V V = 6 V V = 2 V VIL Low-level input voltage V = 4.5 V V V = 6 V VI Input voltage 0 V 0 V V VO Output voltage 0 V 0 V V V = 2 V t/ v Input transition rise/fall time V = 4.5 V ns V = 6 V TA Operating free-air temperature NOTE 3: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating MOS Inputs, literature number SBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V TA = 25 SN54H74 SN74H74 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa 4.5 V VOH VI = VIH or VIL 6 V V IOH = 4 ma 4.5 V IOH = 5.2 ma 6 V V IOL = 20 µa 4.5 V VOL VI = VIH or VIL 6 V V IOL = 4 ma 4.5 V IOL = 5.2 ma 6 V II VI = V or 0 6 V ±0.1 ±100 ±1000 ±1000 na I VI = V or 0, IO = 0 6 V µa i 2 V to 6 V pf UNIT UNIT POST OFFIE BOX DALLAS, TEXAS

4 SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 1982 REVISED JULY 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) V TA = 25 SN54H74 SN74H74 MIN MAX MIN MAX MIN MAX 2 V fclock lock frequency 4.5 V MHz tw tsu Pulse duration Setup time before LK 6 V V PRE or LR low 4.5 V V V LK high or low 4.5 V V V Data 4.5 V V V PRE or LR inactive 4.5 V V V th Hold time, data after LK 4.5 V ns 6 V UNIT ns ns switching characteristics over recommended operating free-air temperature range, L = 50 pf (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) V TA = 25 SN54H74 SN74H74 MIN TYP MAX MIN MAX MIN MAX 2 V fmax 4.5 V MHz tpd 6 V V PRE or LR Q or Q 4.5 V V V LK Q or Q 4.5 V V V tt Q or Q 4.5 V ns 6 V UNIT ns operating characteristics, T A = 25 PARAMETER TEST ONDITIONS TYP UNIT pd Power dissipation capacitance per flip-flop No load 35 pf 4 POST OFFIE BOX DALLAS, TEXAS 75265

5 SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 1982 REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test LOAD IRUIT Test Point L = 50 pf (see Note A) High-Level Pulse Low-Level Pulse tw V 0 V V 0 V VOLTAGE WAVEFORMS PULSE DURATIONS Reference Input tsu th V 0 V Input tplh tphl V 0 V Data Input 10% 90% 90% tr V 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tf In-Phase Output Out-of-Phase Output 10% tphl 90% 90% 90% tr 10% 10% tf tplh VOH 10% VOL tf VOH 90% VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. L includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.. For clock inputs, fmax is measured when the input duty cycle is. D. The outputs are measured one at a time with one input transition per measurement. E. tplh and tphl are the same as tpd. Figure 1. Load ircuit and Voltage Waveforms POST OFFIE BOX DALLAS, TEXAS

6 PAKAGE OPTION ADDENDUM 8-Jun-2005 PAKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) VA ATIVE DIP J 14 1 TBD all TI Level-N-N-N VDA ATIVE FP W 14 1 TBD all TI Level-N-N-N A ATIVE L FK 20 1 TBD all TI Level-N-N-N A ATIVE DIP J 14 1 TBD all TI Level-N-N-N DA ATIVE FP W 14 1 TBD all TI Level-N-N-N JM38510/65302B2A ATIVE L FK 20 1 TBD all TI Level-N-N-N JM38510/65302BA ATIVE DIP J 14 1 TBD all TI Level-N-N-N JM38510/65302BDA ATIVE FP W 14 1 TBD all TI Level-N-N-N SN54H74J ATIVE DIP J 14 1 TBD all TI Level-N-N-N SN74H74ADBLE OBSOLETE SSOP DB 14 TBD all TI all TI SN74H74D ATIVE SOI D Pb-Free SN74H74DBLE OBSOLETE SSOP DB 14 TBD all TI all TI SN74H74DBR ATIVE SSOP DB Pb-Free SN74H74DBRG4 ATIVE SSOP DB Green (RoHS & no Sb/Br) SN74H74DE4 ATIVE SOI D Pb-Free SN74H74DR ATIVE SOI D Pb-Free SN74H74DRE4 ATIVE SOI D Pb-Free SN74H74DRG4 ATIVE SOI D Green (RoHS & no Sb/Br) SN74H74DT ATIVE SOI D Pb-Free SN74H74DTE4 ATIVE SOI D Pb-Free SN74H74N ATIVE PDIP N Pb-Free SN74H74N3 OBSOLETE PDIP N 14 TBD all TI all TI SN74H74NSR ATIVE SO NS Pb-Free SN74H74NSRE4 ATIVE SO NS Pb-Free SN74H74NSRG4 ATIVE SO NS Green (RoHS & no Sb/Br) SN74H74PW ATIVE TSSOP PW Pb-Free SN74H74PWG4 ATIVE TSSOP PW Green (RoHS & no Sb/Br) SN74H74PWLE OBSOLETE TSSOP PW 14 TBD all TI all TI SN74H74PWR ATIVE TSSOP PW Pb-Free SN74H74PWRG4 ATIVE TSSOP PW Green (RoHS & no Sb/Br) Level YEAR/ Level UNLIM Level YEAR/ Level UNLIM Level UNLIM Level YEAR/ Level UNLIM Level YEAR/ Level UNLIM Level YEAR/ Level UNLIM Level UNLIM Level YEAR/ Level UNLIM Level YEAR/ Level UNLIM Level-N-N-N Level YEAR/ Level UNLIM Level YEAR/ Level UNLIM Level UNLIM Level UNLIM Level UNLIM Level UNLIM Level UNLIM Addendum-Page 1

7 PAKAGE OPTION ADDENDUM 8-Jun-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty SN74H74PWT ATIVE TSSOP PW Pb-Free SN74H74PWTG4 ATIVE TSSOP PW Green (RoHS & no Sb/Br) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Level UNLIM Level UNLIM SNJ54H74FK ATIVE L FK 20 1 TBD all TI Level-N-N-N SNJ54H74J ATIVE DIP J 14 1 TBD all TI Level-N-N-N SNJ54H74W ATIVE FP W 14 1 TBD all TI Level-N-N-N (1) The marketing status values are defined as follows: ATIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free : TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDE industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus AS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to ustomer on an annual basis. Addendum-Page 2

10 MEHANIAL DATA ML006B OTOBER 1996 FK (S-Q-N**) 28 TERMINAL SHOWN LEADLESS ERAMI HIP ARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) (9,09) (7,80) (9,09) A SQ B SQ (11,23) (16,26) (18,78) (23,83) (28,99) (11,63) (16,76) (19,32) (24,43) (29,59) (10,31) (12,58) (12,58) (21,6) (26,6) (11,63) (14,22) (14,22) (21,8) (27,0) (0,51) (0,25) (2,03) (1,63) (0,51) (0,25) (1,40) (1,14) (1,14) (0,89) (0,71) (0,54) (1,27) (1,14) (0,89) / D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDE MS-004 POST OFFIE BOX DALLAS, TEXAS 75265

14 MEHANIAL DATA MSSO002E JANUARY 1995 REVISED DEEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTI SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDE MO-150 POST OFFIE BOX DALLAS, TEXAS 75265

15 MEHANIAL DATA MTSS001 JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTI SMALL-OUTLINE PAKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDE MO-153 POST OFFIE BOX DALLAS, TEXAS 75265

16 IMPORTANT NOTIE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. ustomers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. ustomers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data onverters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital ontrol Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas opyright 2005, Texas Instruments Incorporated

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET Wide Operating Voltage Range of 2 V to 6 V Outputs an Drive Up To 0 LSTTL Loads Low Power onsumption, 40-µA Max I Typical t pd = 5 ns ±4-mA Output Drive at 5 V Low Input urrent of µa Max description/ordering