- PDF Free Download

Size: px

Start display at page:

Download ""

Felix Parker
5 years ago
Views:

1 Distributed by: The content and copyrights of the attached material are the property of its owner.

2 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS Power-On Reset Generator Automatic Reset Generation After Voltage Drop Wide Supply-Voltage Range Precision Voltage Sensor Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration SLVS0H APRIL 9 REVISED MAY 00 TL0A, TL09A, TLA, TLA...D OR P PACKAGE TL0A... D, P, OR PS PACKAGE, (TOP VIEW) REF RESIN V CC SENSE description/ordering information TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (P) Tube of 0 TL0ACP TL0ACP SOIC (D) Tube of TL0ACD Reel of 00 TL0ACDR 0AC PDIP (P) Tube of 0 TL0ACP TL0ACP SOIC (D) Tube of TL0ACD Reel of 00 TL0ACDR 0AC SOP (PS) Reel of 000 TL0ACPSR T0A 0 C to 0 C PDIP (P) Tube of 0 TL09ACP TL09ACP 0 C to C SOIC (D) Tube of Reel of 00 TL09ACD TL09ACDR 09AC PDIP (P) Tube of 0 TLACP TL09ACP SOIC (D) Tube of Reel of 00 TLACD TLACDR AC PDIP (P) Tube of 0 TLACP TLACP SOIC (D) Tube of TLACD AC PDIP (P) Tube of 0 TL0AIP TL0AIP SOIC (D) Tube of Reel of 00 TL0AID TL0AIDR 0AI PDIP (P) Tube of 0 TL0AIP TL0AIP SOIC (D) Tube of TL0AID 0AI Reel of 00 TL0AIDR Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 00, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS

3 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS SLVS0H APRIL 9 REVISED MAY 00 description/ordering information (continued) The TLxxA family of integrated-circuit supply-voltage supervisors is designed specifically for use as reset controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for undervoltage conditions at the SENSE input. During power up, the output becomes active (low) when V CC attains a value approaching. V. At this point (assuming that SENSE is above V IT+ ), the delay timer function activates a time delay, after which outputs and go inactive (high and low, respectively). When an undervoltage condition occurs during normal operation, and go active. To ensure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the SENSE input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor C T : t d =. 0 C T, where C T is in farads (F) and t d is in seconds (s). During power down and when SENSE is below V IT, the outputs remain active until V CC falls below V. After this, the outputs are undefined. An external capacitor (typically 0. µf) must be connected to REF to reduce the influence of fast transients in the supply voltage. functional block diagram The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming network to adjust the reference voltage and sense-comparator trip point. VCC Reference Voltage 00 µa SENSE R (see Note A) RESIN R (see Note A) REF NOTES: A. TL0A: R = 0 Ω, R = open TL0A: R =. kω, R = 0 kω TL09A: R = 9. kω, R = 0 kω TLA: R =. kω, R = 0 kω TLA: R =. kω, R = 0 kω B. Resistor values shown are nominal. POST OFFICE BOX 0 DALLAS, TEXAS

4 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS SLVS0H APRIL 9 REVISED MAY 00 timing diagram VCC and SENSE Threshold Voltage VCC. V VCC V Îtd td Output Undefined Output Undefined absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Input voltage range, V I, RESIN V to 0 V Input voltage range, V I, SENSE:TL0A (see Note ) V to V TL0A V to 0 V TL09A V to 0 V TLA, TLA V to 0 V High-level output current, I OH, ma Low-level output current, I OL, ma Package thermal impedance, θ JA (see Notes and ): D package C/W P package C/W PS package C/W Operating virtual junction temperature, T J C Lead temperature, mm (/ inch) from case for 0 seconds C Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values are with respect to.. For proper operation of the TL0A, the voltage applied to the SENSE terminal should not exceed VCC V or V, whichever is less.. Maximum power dissipation is a function of TJ(max), θ JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/θ JA. Operating at the absolute maximum TJ of 0 C can affect reliability.. The package thermal impedance is calculated in accordance with JESD -. POST OFFICE BOX 0 DALLAS, TEXAS

5 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS SLVS0H APRIL 9 REVISED MAY 00 recommended operating conditions MIN MAX UNIT VCC Supply voltage. V VIH High-level input voltage at RESIN V VIL Low-level input voltage at RESIN 0. V TL0A 0 See Note TL0A 0 0 VI Input voltage, SENSE TL09A 0 V TLA 0 0 TLA 0 0 IOH High-level output current, ma IOL Low-level output current, ma TA NOTE : Operating free-air temperature range TLxxAC 0 0 TLxxAI 0 For proper operation of the TL0A, the voltage applied to the SENSE terminal should not exceed VCC V or V, whichever is less. electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TLxxAC TLxxAI UNIT MIN TYP MAX VOH High-level output voltage, IOH = ma VCC. V VOL Low-level output voltage, IOL = ma 0. V Vref Reference voltage TA = C... V VIT Negative-going i input threshold h voltage, SENSE TL0A... TL0A... TL09A TA = C... V TLA TLA... TL0A 0 TL0A Vhys Hysteresis, SENSE (VIT+ VIT ) TL09A TA = C 0 mv TLA II Input current RESIN TLA VI =. V to VCC 0 VI = 0. V 00 µa SENSE TL0A Vref < VI < VCC. V 0. IOH High-level output current, VO = V 0 µa IOL Low-level output current, VO = 0 0 µa ICC Supply current All inputs and outputs open. ma All electrical characteristics are measured with 0.-µF capacitors connected at REF,, and VCC to. C POST OFFICE BOX 0 DALLAS, TEXAS

6 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS SLVS0H APRIL 9 REVISED MAY 00 switching characteristics over recommended operating conditions (unless otherwise noted) tw(s) PARAMETER TEST CONDITIONS TLxxAC TLxxAI UNIT MIN TYP MAX Output pulse duration = 0. µf 0... msec Input pulse duration at RESIN 0. µs Pulse duration at SENSE input to switch outputs VIH = VIT + 00 mv, VIL = VIT 00 mv µs tpd Propagation delay time, RESIN to VCC = V µs tr tf Rise time Fall time VCC =V V, See Note VCC =V V, See Note All switching characteristics are measured with 0.-µF capacitors connected at REF and VCC to. NOTE : The rise and fall times are measured with a.-kω load resistor at and µs µs PARAMETER MEASUREMENT INFORMATION Voltage Drop tw(s) SENSE VIT+ VIT VIT+ 0 V VIH RESIN Undefined tf 90% td 0% tr tf td 0. V tpd 90% 0% V td 90% VIL VOH() 0% 90% 0% 0% 0% 0% VOL() tr Figure. Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS

7 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS SLVS0H APRIL 9 REVISED MAY 00 TYPICAL CHARAERISTICS ASSERTION TIME vs LOAD RESISTANCE VCC = V = 0. µf CL = 0 pf TA = C DEASSERTION TIME vs LOAD RESISTANCE VCC = V = 0. µf CL = 0 pf TA = C t Assertion Time ns 0 tr µs t Deassertion Time tf tf tr 0 0 RL Load Resistance kω Figure RL Load Resistance kω Figure t Assertion Time ns 0 VCC = V = 0. µf RL =. kω TA = C tr ASSERTION TIME vs LOAD CAPACITANCE t Deassertion Time µ s..... VCC = V = 0. µf RL =. kω TA = C DEASSERTION TIME vs LOAD CAPACITANCE tf tr tf CL Load Capacitance pf Figure CL Load Capacitance pf Figure For proper operation, both and should be terminated with resistors of similar value. Failure to do so may cause unwanted plateauing in either output waveform during switching. POST OFFICE BOX 0 DALLAS, TEXAS

8 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS APPLICATION INFORMATION SLVS0H APRIL 9 REVISED MAY 00 V V VCC SENSE RESIN TLA REF 0. µf 0 kω 0 kω kω VCC SENSE RESIN TL0A REF 0. µf 0 kω System Reset 0 kω VCC SENSE RESIN TLA REF 0. µf 0 kω C T (F) t d(s). 0 V Figure. Multiple Power-Supply System Reset Generation V C T (F) t d(s). 0 VCC SENSE RESIN TL0A REF 0 kω 0 kω 0. µf VCC TMS000 VSS Figure. Reset Controller for TMS000 System POST OFFICE BOX 0 DALLAS, TEXAS

9 TL0A, TL0A, TL09A, TLA, TLA SUPPLY-VOLTAGE SUPERVISORS SLVS0H APRIL 9 REVISED MAY 00 APPLICATION INFORMATION V Input µa0 INPUT OUTPUT COMMON CI CO VCC SENSE TL0A REF 0. µf. kω G. kω kω S D Q N99 System Figure. Eliminating Undefined States Using a P-Channel JFET VCC 0 kω 0 Ω SENSE Input VCC SENSE TLxxA RESIN. kω Q N0 System REF 0 kω kω 0. µf Figure 9. Eliminating Undefined States Using a pnp Transistor POST OFFICE BOX 0 DALLAS, TEXAS

10 PACKAGE OPTION ADDENDUM -Sep-00 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp () 9-0A OBSOLETE LCCC FK 0 TBD Call TI Call TI TL0ACD AIVE SOIC D Green (RoHS & TL0ACDE AIVE SOIC D Green (RoHS & TL0ACDG AIVE SOIC D Green (RoHS & TL0ACDR AIVE SOIC D 00 Green (RoHS & TL0ACDRE AIVE SOIC D 00 Green (RoHS & TL0ACDRG AIVE SOIC D 00 Green (RoHS & TL0ACP AIVE PDIP P 0 Pb-Free TL0ACPE AIVE PDIP P 0 Pb-Free TL0AID AIVE SOIC D Green (RoHS & TL0AIDE AIVE SOIC D Green (RoHS & TL0AIDG AIVE SOIC D Green (RoHS & TL0AIDR AIVE SOIC D 00 Green (RoHS & TL0AIDRE AIVE SOIC D 00 Green (RoHS & TL0AIDRG AIVE SOIC D 00 Green (RoHS & TL0AIP AIVE PDIP P 0 Pb-Free TL0AIPE AIVE PDIP P 0 Pb-Free TL0AMFKB OBSOLETE LCCC FK 0 TBD Call TI Call TI TL0AMJG OBSOLETE CDIP JG TBD Call TI Call TI TL0AMJGB OBSOLETE CDIP JG TBD Call TI Call TI TL0ACD AIVE SOIC D Green (RoHS & TL0ACDE AIVE SOIC D Green (RoHS & TL0ACDG AIVE SOIC D Green (RoHS & TL0ACDR AIVE SOIC D 00 Green (RoHS & TL0ACDRE AIVE SOIC D 00 Green (RoHS & TL0ACDRG AIVE SOIC D 00 Green (RoHS & Level--0C-YEAR TL0ACP AIVE PDIP P 0 Pb-Free Addendum-Page

11 PACKAGE OPTION ADDENDUM -Sep-00 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp () TL0ACPE AIVE PDIP P 0 Pb-Free TL0ACPSLE OBSOLETE SO PS TBD Call TI Call TI TL0ACPSR AIVE SO PS 000 Green (RoHS & TL0ACPSRE AIVE SO PS 000 Green (RoHS & TL0AID AIVE SOIC D Green (RoHS & TL0AIDE AIVE SOIC D Green (RoHS & TL0AIDG AIVE SOIC D Green (RoHS & TL0AIDR AIVE SOIC D 00 Green (RoHS & TL0AIDRE AIVE SOIC D 00 Green (RoHS & TL0AIDRG AIVE SOIC D 00 Green (RoHS & TL0AIP AIVE PDIP P 0 Pb-Free TL0AIPE AIVE PDIP P 0 Pb-Free TL0AMFKB OBSOLETE LCCC FK 0 TBD Call TI Call TI TL0AMJG OBSOLETE CDIP JG TBD Call TI Call TI TL0AMJGB OBSOLETE CDIP JG TBD Call TI Call TI TL09ACD AIVE SOIC D Green (RoHS & TL09ACDE AIVE SOIC D Green (RoHS & TL09ACDR AIVE SOIC D 00 Green (RoHS & TL09ACDRE AIVE SOIC D 00 Green (RoHS & TL09ACP AIVE PDIP P 0 Pb-Free TL09ACPE AIVE PDIP P 0 Pb-Free TL09AID OBSOLETE SOIC D TBD Call TI Call TI TL09AIP OBSOLETE PDIP P TBD Call TI Call TI TLACD AIVE SOIC D Green (RoHS & TLACDE AIVE SOIC D Green (RoHS & TLACDR AIVE SOIC D 00 Green (RoHS & TLACDRE AIVE SOIC D 00 Green (RoHS & Level--0C-YEAR Level--0C-YEAR Level--0C-YEAR Level--0C-YEAR Level--0C-YEAR Level--0C-YEAR TLACP AIVE PDIP P 0 Pb-Free Addendum-Page

12 PACKAGE OPTION ADDENDUM -Sep-00 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp () TLACPE AIVE PDIP P 0 Pb-Free TLAID OBSOLETE SOIC D TBD Call TI Call TI TLAIP OBSOLETE PDIP P TBD Call TI Call TI TLACD AIVE SOIC D Green (RoHS & TLACDE AIVE SOIC D Green (RoHS & TLACP AIVE PDIP P 0 Pb-Free TLACPE AIVE PDIP P 0 Pb-Free TLAID OBSOLETE SOIC D TBD Call TI Call TI TLAIP OBSOLETE PDIP P TBD Call TI Call TI () The marketing status values are defined as follows: AIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free, Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free : TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) () MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

13 MECHANICAL DATA MCER00A JANUARY 99 REVISED JANUARY 99 JG (R-GDIP-T) CERAMIC DUAL-IN-LINE 0.00 (0,) 0. (9,00) 0.0 (,) 0. (,) 0.0 (,) 0.0 (,) 0.0 (,0) 0.0 (0,) 0.00 (0,) MIN 0.0 (,) 0.90 (,) 0.00 (,0) MAX Seating Plane 0.0 (,0) MIN 0.00 (,) 0.0 (0,) 0.0 (0,) 0.0 (0,) 0.00 (0,0) 0 000/C 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD GDIP-T POST OFFICE BOX 0 DALLAS, TEXAS

14 MECHANICAL DATA MLCC00B OOBER 99 FK (S-CQCC-N**) TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (,9) 0. (9,09) 0.0 (,0) 0. (9,09) A SQ B SQ (,) 0.0 (,) 0.9 (,) 0.9 (,). (,99) 0. (,) 0.0 (,) 0. (9,) 0.9 (,). (9,9) 0.0 (0,) 0.9 (,) 0.9 (,) 0.0 (,).0 (,) 0. (,) 0.0 (,) 0.0 (,) 0. (,).0 (,0) 0.00 (0,) 0.00 (0,) 0.00 (,0) 0.0 (,) 0.00 (0,) 0.00 (0,) 0.0 (,0) 0.0 (,) 0.0 (,) 0.0 (0,9) 0.0 (0,) 0.0 (0,) 0.00 (,) 0.0 (,) 0.0 (0,9) 000/ D 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-00 POST OFFICE BOX 0 DALLAS, TEXAS

15 MECHANICAL DATA MPDI00A JANUARY 99 REVISED JUNE 999 P (R-PDIP-T) PLASTIC DUAL-IN-LINE 0.00 (0,0) 0. (9,0) 0.0 (,0) 0.0 (,0) 0.00 (,) MAX 0.00 (0,) MIN 0. (,) 0.00 (,) 0.0 (0,) 0.00 (,0) MAX Gage Plane Seating Plane 0. (,) MIN 0.00 (0,) NOM 0.0 (0,) 0.0 (0,) 0.00 (,) 0.00 (0,) M 0.0 (0,9) MAX 000/D 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 For the latest package information, go to POST OFFICE BOX 0 DALLAS, TEXAS

18 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Low Power Wireless Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 0 Dallas, Texas Copyright 00, Texas Instruments Incorporated

ua9636ac DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE

ua9636ac DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE SLLSB OCTOBER 9 REVISED MAY 995 Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-3-B and -3-E and ITU Recommendations V. and V. Output Slew Rate Control Output Short-Circuit-Current Limiting