TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH

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1 POWER LOGIC OCTAL -TYPE LATCH Low r S(on)...5 Ω Typical Avalanche Energy...30 mj Eight Power MOS-Transistor Outputs of 50-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage... 5 Low Power Consumption description The TPIC6B273 is a monolithic, high-voltage, medium-current, power logic octal -type latch with MOS-transistor outputs designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. The TPIC6B273 contains eight positive-edgetriggered -type flip-flops with a direct clear input. Each flip-flop features an open-drain power MOS-transistor output. When clear () is high, information at the inputs meeting the setup time requirements is transferred to the RAIN outputs on the positivegoing edge of the clock () pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input () is at either the high or low level, the input signal has no effect at the output. An asynchronous is provided to turn all eight MOS-transistor outputs off. When data is low for a given output, the MOS-transistor output is off. When data is high, the MOS-transistor output has sink-current capability. Outputs are low-side, open-drain MOS transistors with output ratings of 5 and 50-mA continuous sink-current capability. Each output provides a 500-mA typical current limit at T C = 25 C. The current limit decreases as the junction temperature increases for additional device protection. 2 RAIN RAIN2 RAIN3 RAIN4 3 4 GN logic symbol W OR N PACKAGE (TOP VIEW) The TPIC6B273 is characterized for operation over the operating case temperature range of 40 C to 25 C R V CC 8 7 RAIN8 RAIN7 RAIN6 RAIN RAIN RAIN2 RAIN3 RAIN4 RAIN5 RAIN6 RAIN7 RAIN8 This symbol is in accordance with ANSI/IEEE Standard and IEC Publication L H H H FUNCTION TABLE (each channel) INPUTS OUTPUT RAIN X L X H L X H L H Latched H = high level, L = low level, X = irrelevant PROUCTION ATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 997, Texas Instruments Incorporated POST OFFICE BOX ALLAS, TEXAS 75265

2 POWER LOGIC OCTAL -TYPE LATCH logic diagram (positive logic) 4 RAIN 2 5 RAIN RAIN RAIN RAIN RAIN RAIN RAIN GN 2 POST OFFICE BOX ALLAS, TEXAS 75265

3 POWER LOGIC OCTAL -TYPE LATCH schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL RAIN OUTPUTS VCC RAIN 5 Input 2 2 V 2 GN GN absolute maximum ratings over recommended operating case temperature range (unless otherwise noted) Logic supply voltage, V CC (see Note ) V Logic input voltage range, V I V to 7 V Power MOS drain-to-source voltage, V S (see Note 2) Continuous source-to-drain diode anode current ma Pulsed source-to-drain diode anode current (see Note 3) A Pulsed drain current, each output, all outputs on, I, T C = 25 C (see Note 3) ma Continuous drain current, each output, all outputs on, I, T C = 25 C ma Peak drain current single output, I M,T C = 25 C (see Note 3) ma Single-pulse avalanche energy, E AS (see Figure 4) mj Avalanche current, I AS (see Note 4) ma Continuous total dissipation See issipation Rating Table Operating virtual junction temperature range, T J C to 50 C Operating case temperature range, T C C to 25 C Storage temperature range C to 50 C Lead temperature,6 mm (/6 inch) from case for 0 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values are with respect to GN. 2. Each power MOS source is internally connected to GN. 3. Pulse duration 00 µs and duty cycle 2%. 4. RAIN supply voltage =, starting junction temperature (TJS) = 25 C, L = 200 mh, IAS = 0.5 A (see Figure 4). PACKAGE ISSIPATION RATING TABLE TC 25 C POWER RATING ERATING FACTOR ABOVE TC = 25 C TC = 25 C POWER RATING W 389 mw. mw/ C 278 mw N 050 mw 0.5 mw/ C 263 mw POST OFFICE BOX ALLAS, TEXAS

4 POWER LOGIC OCTAL -TYPE LATCH recommended operating conditions MIN MAX UNIT Logic supply voltage, VCC High-level input voltage, VIH 0.8CC V Low-level input voltage, VIL 0.CC V Pulsed drain output current, TC = 25 C, VCC = (see Notes 3 and 5) ma Setup time, high before, tsu (see Figure 2) 20 ns Hold time, high after, th (see Figure 2) 20 ns Pulse duration, tw (see Figure 2) 40 ns Operating case temperature, TC C electrical characteristics, V CC =, T C = 25 C (unless otherwise noted) V(BR)SX VS PARAMETER TEST CONITIONS MIN TYP MAX UNIT rain-to-source breakdown voltage Source-to-drain diode forward voltage I = ma 5 IF = 00 ma 0.85 V IIH High-level input current VCC = 5., VI = VCC µa IIL Low-level input current VCC = 5., VI = 0 µa ICC Logic supply current VCC = 5.5 IN ISX rs(on) Nominal current Off-state drain current Static drain-to-source on-state resistance All outputs off All outputs on VS(on) = 0., IN = I, TC = 85 C, 90 ma See Notes 5, 6, and 7 VS = 4, VCC = µa VS = 4, VCC = 5., TC = 25 C I = 00 ma, VCC = I = 00 ma, TC = 25 C VCC = 4., See Notes 5 and 6 and Figures 6 and 7 µa Ω I = 350 ma, VCC = switching characteristics, V CC =, T C = 25 C PARAMETER TEST CONITIONS MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output from 50 ns tphl Propagation delay time, high-to-low-level output from CL = 30 pf, I = 00 ma, 90 ns tr Rise time, drain output See Figures, 2, and ns tf Fall time, drain output 200 ns ta Reverse-recovery-current rise time IF = 00 ma, di/dt = 20 A/µs, 00 trr Reverse-recovery time See Notes 5 and 6 and Figure ns NOTES: 3. Pulse duration 00 µs and duty cycle 2%. 5. Technique should limit TJ TC to 0 C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0. at TC = 85 C. 4 POST OFFICE BOX ALLAS, TEXAS 75265

5 POWER LOGIC OCTAL -TYPE LATCH thermal resistance PARAMETER TEST CONITIONS MIN MAX UNIT RθJA Thermal resistance, junction-to-ambient to W package N package All 8 outputs with equal power C/W PARAMETER MEASUREMENT INFORMATION 20 VCC I 24 V 235 Ω Word Generator (see Note A) UT RAIN 4 7, 4 7 Output CL = 30 pf (see Note B) GN 0 Output 24 V 0. TEST CIRCUIT VOLTAGE WAVEFORMS Figure. Resistive-Load Test Circuit and Voltage Waveforms Word Generator (see Note A) Word Generator (see Note A) VCC 20 UT GN TEST CIRCUIT RAIN 0 I 4 7, V 235 Ω Output Output CL = 30 pf (see Note B) 0% 50% tsu tplh 90% tr SWITCHING TIMES 50% th 50% 50% 90% tw INPUT SETUP AN HOL WAVEFORMS 50% tphl 24 V 0% 0. tf Figure 2. Test Circuit, Switching Times, and Voltage Waveforms NOTES: A. The word generator has the following characteristics: tr 0 ns, tf 0 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 KHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. POST OFFICE BOX ALLAS, TEXAS

6 POWER LOGIC OCTAL -TYPE LATCH PARAMETER MEASUREMENT INFORMATION RAIN TP K Circuit Under Test IF (see Note A) L = mh 2500 µf TP A 0. A IF 0 di/dt = 20 A/µs 25% of IRM t t2 t3 RG river IRM VGG (see Note B) 50 Ω ta trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The RAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0. A, where t = 0 µs, t2 = 7 µs, and t3 = 3 µs. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-rain iode Word Generator (see Note A) 20 VCC UT RAIN GN 0 I 4 7, Ω 200 mh VS Input I VS tw See Note B tav IAS = 0.5 A V(BR)SX = 5 MIN TEST CIRCUIT VOLTAGE AN CURRENT WAVEFORMS NOTES: A. The word generator has the following characteristics: tr 0 ns, tf 0 ns, ZO = 50 Ω. B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A. Energy test is defined as EAS = IAS x V(BR)SX x tav/2 = 30 mj. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms 6 POST OFFICE BOX ALLAS, TEXAS 75265

7 POWER LOGIC OCTAL -TYPE LATCH TYPICAL CHARACTERISTICS I AS Peak Avalanche Current A PEAK AVALANCHE CURRENT vs TIME URATION OF AVALANCHE TC = 25 C tav Time uration of Avalanche ms Ω rain-to-source On-State Resistance r S(on) RAIN-TO-SOURCE ON-STATE RESISTANCE vs RAIN CURRENT VCC = See Note A TC = 25 C TC = 25 C TC = 40 C I rain Current ma Figure 5 Figure 6 Ω Static rain-to-source On-State Resistance r S(on) STATIC RAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE TC = 40 C TC = 25 C TC = 25 C VCC Logic Supply Voltage V I = 00 ma See Note A Switching Time ns I = 00 ma See Note A SWITCHING TIME vs CASE TEMPERATURE tf tr tplh tphl TC Case Temperature C Figure 7 Figure 8 NOTE C: Technique should limit TJ TC to 0 C maximum. POST OFFICE BOX ALLAS, TEXAS

8 POWER LOGIC OCTAL -TYPE LATCH THERMAL INFORMATION Maximum Continuous rain Current of Each Output A I MAXIMUM CONTINUOUS RAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONUCTING SIMULTANEOUSLY TC = 25 C TC = 25 C TC = 00 C VCC = N Number of Outputs Conducting Simultaneously Maximum Peak rain Current of Each Output A I MAXIMUM PEAK RAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONUCTING SIMULTANEOUSLY d = 80% d = 50% 0. VCC = TC = 25 C d = 0.05 tw/tperiod = ms/tperiod d = 20% d = 0% N Number of Outputs Conducting Simultaneously Figure 9 Figure 0 8 POST OFFICE BOX ALLAS, TEXAS 75265

9 PACKAGE OPTION AENUM 8-Jul-2006 PACKAGING INFORMATION Orderable evice Status () Package Type Package rawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TPIC6B273W ACTIVE SOIC W TB CU NIPAU Level--220C-UNLIM TPIC6B273WG4 ACTIVE SOIC W Green (RoHS & no Sb/Br) CU NIPAU Level--260C-UNLIM TPIC6B273WR ACTIVE SOIC W TB CU NIPAU Level--220C-UNLIM TPIC6B273WRG4 ACTIVE SOIC W Green (RoHS & no Sb/Br) TPIC6B273N ACTIVE PIP N Pb-Free (RoHS) CU NIPAU CU NIPAU Level--260C-UNLIM N / A for Pkg Type () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRN: Not recommended for new designs. evice is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: evice has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TB: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEEC industry standard classifications, and peak solder temperature. Important Information and isclaimer:the information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio ata Converters dataconverter.ti.com Automotive SP dsp.ti.com Broadband Interface interface.ti.com igital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Low Power Wireless Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box allas, Texas Copyright 2006, Texas Instruments Incorporated

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH POWER LOGIC OCTAL -TYPE LATC Low r S(on)... Ω Typical Avalanche Energy...3 mj Eight Power MOS-Transistor Outputs of -ma Continuous Current -ma Typical Current-Limiting Capability Output Clamp Voltage...