description logic symbol

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1 Low r S(on)...5 Ω Typical Avalanche Energy... 0 mj Eight Power MOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage...5 evices Are Cascadable Low Power Consumption description The TPIC6B55 is a monolithic, high-voltage, medium-current power -bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads. This device contains an -bit serial-in, parallel-out shift register that feeds an -bit -type storage register. ata transfers through both the shift and storage registers on the rising edge of the shift-register clock () and the register clock (), respectively. The storage register transfers data to the output buffer when shiftregister clear (SR) is high. When SR is low, the input shift register is cleared. When output enable () is held high, all data in the output buffers is held low and all drain outputs are off. When is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the MOS-transistor outputs are off. When data is high, the MOStransistor outputs have sink-current capability. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. logic symbol NC V CC RAIN0 RAIN1 RAIN RAIN SR N SLIS0A JULY 15 REVISE MAY 005 W OR N PACKAE (TOP VIEW) Outputs are low-side, open-drain MOS transistors with output ratings of 5 and 150-mA continuous sinkcurrent capability. Each output provides a 500-mA typical current limit at T C = 5 C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B55 is characterized for operation over the operating case temperature range of 40 C to 15 C. SR EN C SR R NC No internal connection NC N SER OUT RAIN7 RAIN6 RAIN5 RAIN4 N 4 RAIN0 5 RAIN1 6 RAIN 7 RAIN 14 RAIN4 15 RAIN5 16 RAIN6 17 RAIN7 1 SER OUT This symbol is in accordance with ANSI/IEEE Std 1-14 and IEC Publication Copyright , Texas Instruments Incorporated POST OFFICE BOX 6550 ALLAS, TEXAS

2 SLIS0A JULY 15 REVISE MAY 005 logic diagram (positive logic) SR 1 1 C 4 RAIN0 5 RAIN1 C 6 RAIN C 7 RAIN C 14 RAIN4 C 15 RAIN5 C 16 RAIN6 C 17 RAIN7 C 10, 11, 1 N 1 SER OUT POST OFFICE BOX 6550 ALLAS, TEXAS 7565

3 SLIS0A JULY 15 REVISE MAY 005 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL RAIN OUTPUTS VCC RAIN 5 Input 1 V N N absolute maximum ratings over recommended operating case temperature range (unless otherwise noted) Logic supply voltage, V CC (see Note 1) V Logic input voltage range, V I V to 7 V Power MOS drain-to-source voltage, V S (see Note ) Continuous source-to-drain diode anode current ma Pulsed source-to-drain diode anode current (see Note ) A Pulsed drain current, each output, all outputs on, I, T C = 5 C (see Note ) ma Continuous drain current, each output, all outputs on, I, T C = 5 C ma Peak drain current single output, I M,T C = 5 C (see Note ) ma Single-pulse avalanche energy, E AS (see Figure 4) mj Avalanche current, I AS (see Note 4) ma Continuous total dissipation See issipation Rating Table Operating virtual junction temperature range, T J C to 150 C Operating case temperature range, T C C to 15 C Storage temperature range C to 150 C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to N.. Each power MOS source is internally connected to N.. Pulse duration 100 µs and duty cycle %. 4. RAIN supply voltage = 1, starting junction temperature (TJS) = 5 C, L = 00 mh, IAS = 0.5 A (see Figure 4). PACKAE ISSIPATION RATIN TABLE TC 5 C POWER RATIN ERATIN FACTOR ABOVE TC = 5 C TC = 15 C POWER RATIN W 1 mw 11.1 mw/ C 7 mw N 1050 mw 10.5 mw/ C 6 mw POST OFFICE BOX 6550 ALLAS, TEXAS 7565

4 SLIS0A JULY 15 REVISE MAY 005 recommended operating conditions MIN MAX UNIT Logic supply voltage, VCC High-level input voltage, VIH 0.CC V Low-level input voltage, VIL 0.1CC V Pulsed drain output current, TC = 5 C, VCC = (see Notes and 5) ma Setup time, high before, tsu (see Figure ) 0 ns Hold time, high after, th (see Figure ) 0 ns Pulse duration, tw (see Figure ) 40 ns Operating case temperature, TC C electrical characteristics, V CC =, T C = 5 C (unless otherwise noted) PARAMETER TEST CONITIONS MIN TYP MAX UNIT V(BR)SX rain-to-source breakdown voltage I = 1 ma 5 VS VOH VOL Source-to-drain diode forward voltage IF = 100 ma V High-level output voltage, IOH = 0 µa, VCC = SER OUT IOH = 4 ma, VCC = Low-level output voltage, IOL = 0 µa, VCC = SER OUT IOL = 4 ma, VCC = IIH High-level input current VCC = 5., VI = VCC 1 µa IIL Low-level input current VCC = 5., VI = 0 1 µa ICC Logic supply current VCC = 5. ICC(FRQ) IN ISX rs(on) Logic supply current at frequency Nominal current Off-state drain current Static drain-source on-state resistance f = 5 MHz,CL = 0 pf, All outputs off, See Figures and 6 VS(on) = 0., IN = I, TC = 5 C All outputs off All outputs on V V µaa ma See Notes 5, 6, and 7 0 ma VS = 4, VCC = VS = 4, VCC = 5., TC = 15 C 0.15 I = 100 ma, VCC = I = 100 ma, VCC = 4. I = 50 ma, TC = 15 C, VCC = 4. See Notes 5 and 6 and Figures 7 and µaa 6..5 Ω 5.5 NOTES:. Pulse duration 100 µs and duty cycle %. 5. Technique should limit TJ TC to 10 C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0. at TC = 5 C. 4 POST OFFICE BOX 6550 ALLAS, TEXAS 7565

5 SLIS0A JULY 15 REVISE MAY 005 switching characteristics, V CC =, T C = 5 C PARAMETER TEST CONITIONS MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output from 150 ns tphl Propagation delay time, high-to-low-level output from CL = 0 pf, I = 100 ma, 0 ns tr Rise time, drain output See Figures 1,, and 00 ns tf Fall time, drain output 00 ns ta Reverse-recovery-current rise time IF = 100 ma, di/dt = 0 A/µs, 100 trr Reverse-recovery time See Notes 5 and 6 and Figure 00 NOTES: 5. Technique should limit TJ TC to 10 C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. thermal resistance ns RθJA PARAMETER TEST CONITIONS MIN MAX UNIT W package 0 Thermal resistance, junction-to-ambient All outputs with equal power C/W N package 5 PARAMETER MEASUREMENT INFORMATION Word enerator (see Note A) 1 1 VCC SR UT RAIN N 10, 11, 1 TEST CIRCUIT I 4 7, V RL = 5 Ω Output CL = 0 pf (see Note B) SR RAIN VOLTAE WAVEFORMS 4 V 0. NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 00 ns, pulsed repetition rate (PRR) = 5 khz, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Resistive-Load Test Circuit and Voltage Waveforms POST OFFICE BOX 6550 ALLAS, TEXAS

6 SLIS0A JULY 15 REVISE MAY 005 PARAMETER MEASUREMENT INFORMATION Word enerator (see Note A) 1 1 SR VCC TEST CIRCUIT 4 V UT N RAIN 10, 11, 1 I 4 7, RL = 5 Ω Output CL = 0 pf (see Note B) Output 50% 50% tplh tphl 4 V 0% 0% 10% 10% 0. tr tf SWITCHIN TIMES 50% tsu th 50% 50% tw INPUT SETUP AN HOL WAVEFORMS NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 00 ns, pulsed repetition rate (PRR) = 5 khz, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure. Test Circuit, Switching Times, and Voltage Waveforms RAIN TP K Circuit Under Test IF (see Note A) L = 1 mh 500 µf 5 + TP A 0.1 A IF 0 di/dt = 0 A/µs 5% of IRM t1 t t R river IRM V (see Note B) 50 Ω ta trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The RAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The V amplitude and R are adjusted for di/dt = 0 A/µs. A V double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs, t = 7 µs, and t = µs. Figure. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-rain iode 6 POST OFFICE BOX 6550 ALLAS, TEXAS 7565

7 PARAMETER MEASUREMENT INFORMATION SLIS0A JULY 15 REVISE MAY Word enerator (see Note A) 1 1 SR VCC UT RAIN N 10, 11, 1 I 4 7, Ω 00 mh VS Input I VS tw See Note B tav IAS = 0.5 A V(BR)SX = 5 MIN SINLE-PULSE AVALANCHE ENERY TEST CIRCUIT VOLTAE AN CURRENT WAVEFORMS NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 Ω. B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A. Energy test level is defined as EAS = IAS V(BR)SX tav/ = 0 mj. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS I AS Peak Avalanche Current A PEAK AVALANCHE CURRENT TIME URATION OF AVALANCHE TC = 5 C I CC Supply Current ma VCC = TC = 40 C to 15 C SUPPLY CURRENT FREQUENCY tav Time uration of Avalanche ms Figure f Frequency MHz Figure POST OFFICE BOX 6550 ALLAS, TEXAS

8 SLIS0A JULY 15 REVISE MAY 005 TYPICAL CHARACTERISTICS Ω rain-to-source On-State Resistance r S(on) RAIN-TO-SOURCE ON-STATE RESISTANCE RAIN CURRENT VCC = See Note A TC = 15 C TC = 5 C TC = 40 C I rain Current ma Figure 7 Ω Static rain-to-source On-State Resistance r S(on) STATIC RAIN-TO-SOURCE ON-STATE RESISTANCE LOIC SUPPLY VOLTAE TC = 40 C TC = 15 C TC = 5 C VCC Logic Supply Voltage V Figure I = 100 ma See Note A I = 100 ma See Note A SWITCHIN TIME CASE TEMPERATURE tf Switching Time ns tr tplh 100 tphl TC Case Temperature C Figure NOTE C: Technique should limit TJ TC to 10 C maximum. POST OFFICE BOX 6550 ALLAS, TEXAS 7565

9 THERMAL INFORMATION SLIS0A JULY 15 REVISE MAY 005 Maximum Continuous rain Current of Each Output A I MAXIMUM CONTINUOUS RAIN CURRENT OF EACH OUTPUT NUMBER OF OUTPUTS CONUCTIN SIMULTANEOUSLY TC = 15 C N Number of Outputs Conducting Simultaneously Figure 10 TC = 5 C TC = 100 C VCC = Maximum Peak rain Current of Each Output A I MAXIMUM PEAK RAIN CURRENT OF EACH OUTPUT NUMBER OF OUTPUTS CONUCTIN SIMULTANEOUSLY d = 0% d = 50% 0.1 VCC = TC = 5 C d = 0.05 tw/tperiod = 1 ms/tperiod N Number of Outputs Conducting Simultaneously Figure 11 d = 0% d = 10% 6 7 Revision History ATE REV PAE SECTION ESCRIPTION 5/1/05 A 5 Figure 1 Changed SR timing diagram 7/15 * Original reversion NOTE: Page numbers for previous revisions may differ from page numbers in the current version. POST OFFICE BOX 6550 ALLAS, TEXAS 7565

10 PACKAE OPTION AENUM -Mar-006 PACKAIN INFORMATION Orderable evice Status (1) Package Type Package rawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp () TPIC6B55W ACTIVE SOIC W 0 5 TB CU NIPAU Level-1-0C-UNLIM TPIC6B55W4 ACTIVE SOIC W 0 5 reen (RoHS & no Sb/Br) CU NIPAU Level-1-60C-UNLIM TPIC6B55WR ACTIVE SOIC W TB CU NIPAU Level-1-0C-UNLIM TPIC6B55N ACTIVE PIP N 0 0 Pb-Free (RoHS) CU NIPAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRN: Not recommended for new designs. evice is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: evice has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or reen (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TB: The Pb-Free/reen conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. reen (RoHS & no Sb/Br): TI defines "reen" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) () MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEEC industry standard classifications, and peak solder temperature. Important Information and isclaimer:the information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

13 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio ata Converters dataconverter.ti.com Automotive SP dsp.ti.com Broadband Interface interface.ti.com igital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 6550 allas, Texas 7565 Copyright 006, Texas Instruments Incorporated

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH POWER LOGIC OCTAL -TYPE LATCH Low r S(on)...5 Ω Typical Avalanche Energy...30 mj Eight Power MOS-Transistor Outputs of 50-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage...