TPIC6A595 POWER LOGIC 8-BIT SHIFT REGISTER

Size: px
Start display at page:

Download "TPIC6A595 POWER LOGIC 8-BIT SHIFT REGISTER"

Transcription

1 Low r S(on)... Ω Typ Output Short-Circuit Protection Avalanche Energy...75 mj Eight 35-mA MOS Outputs 5-V Switching Capability evices Are Cascadable Low Power Consumption description The TPIC6A595 is a monolithic, high-voltage, high-current power logic 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. Each open-drain MOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit, -type storage register. ata transfers through both the shift and storage registers on the rising edge of the shiftregister clock () and the register clock (), respectively. The storage register transfers data to the output buffer when shiftregister clear () is high. When is low, the input shift register is cleared. When output SLIS5A APRIL 993 REVISE JANUARY 995 RAIN RAIN3 RAIN4 RAIN5 RAIN RAIN3 RAIN4 RAIN5 NE PACKAE (TOP VIEW) enable () is held high, all data in the output buffers is held low and all drain outputs are off. When is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. Outputs are low-side, open-drain MOS transistors with output ratings of 5 V and a 35-mA continuous sink current capability. When data in the output buffers is low, the MOS-transistor outputs are off. When data is high, the MOS-transistor outputs have sink current capability. Separate power ground () and logic ground (LN) terminals are provided to facilitate maximum system flexibility. All terminals are internally connected, and each terminal must be externally connected to the power system ground in order to minimize parasitic impedance. A single-point connection between LN and must be made externally in a manner that reduces crosstalk between the logic and load circuits. The TPIC6A595 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount (W) package. The TPIC6A595 is characterized for operation over the operating case temperature range of 4 C to 5 C W PACKAE (TOP VIEW) RAIN RAN V CC LN SER OUT RAIN7 RAIN6 RAIN RAIN V CC LN SER OUT RAIN7 RAIN6 PROUCTION ATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 995, Texas Instruments Incorporated POST OFFICE BOX ALLAS, TEXAS 7565

2 SLIS5A APRIL 993 REVISE JANUARY 995 logic symbol EN3 SR8 R 3 RAIN RAIN RAIN RAIN3 RAIN4 RAIN5 RAIN6 3 RAIN7 SER OUT This symbol is in accordance with ANSI/IEEE Std and IEC Publication 67-. POST OFFICE BOX ALLAS, TEXAS 7565

3 SLIS5A APRIL 993 REVISE JANUARY 995 logic diagram (positive logic) RAIN RAIN RAIN Current Limit and Charge Pump RAIN3 RAIN4 RAIN5 RAIN6 RAIN7 SER OUT POST OFFICE BOX ALLAS, TEXAS

4 SLIS5A APRIL 993 REVISE JANUARY 995 schematic of inputs and outputs TYPICAL OF SERIAL OUT EQUIVALENT OF EACH INPUT TYPICAL OF ALL RAIN OUTPUTS VCC VCC RAIN SER OUT Input V LN LN LN RSENSE absolute maximum ratings over recommended operating case temperature range (unless otherwise noted) Logic supply voltage, V CC (see Note ) V Logic input voltage range, V I V to 7 V Power MOS drain-to-source voltage, V S (see Note ) V Continuous source-drain diode anode current A Pulsed source-drain diode anode current (see Note 3) A Pulsed drain current, each output, all outputs on, I n, T A = 5 C (see Note 3) A Continuous drain current, each output, all outputs on, I n, T A = 5 C ma Peak drain current, single output, T A = 5 C (see Note 3) A Single-pulse avalanche energy, E AS (see Figure 6) mj Avalanche current, I AS (see Note 4) ma Continuous total dissipation See issipation Rating Table Operating case temperature range, T C C to 5 C Operating virtual junction temperature range, T J C to 5 C Storage temperature range, T stg C to 5 C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values are with respect to LN and.. Each power MOS source is internally connected to. 3. Pulse duration µs and duty cycle %. 4. RAIN supply voltage =, starting junction temperature (TJS) = 5 C, L = mh, IAS = 6 ma (see Figure 6). PACKAE ISSIPATION RATIN TABLE TC 5 C POWER RATIN ERATIN FACTOR ABOVE TC = 5 C TC = 5 C POWER RATIN W 75 mw 4 mw/ C 35 mw NE 5 mw mw/ C 5 mw 4 POST OFFICE BOX ALLAS, TEXAS 7565

5 SLIS5A APRIL 993 REVISE JANUARY 995 recommended operating conditions MIN MAX UNIT Logic supply voltage, VCC High-level input voltage, VIH.8CC VCC V Low-level input voltage, VIL.CC V Pulsed drain output current, TC = 5 C, VCC = (see Notes 3 and 5).8.6 A Setup time, high before, tsu (see Figure ) ns Hold time, high after, th (see Figure ) ns Pulse duration, tw (see Figure ) ns Operating case temperature, TC 4 5 C electrical characteristics, V CC =, T C = 5 C (unless otherwise noted) V(BR)SX VS PARAMETER TEST CONITIONS MIN TYP MAX UNIT rain-to-source breakdown voltage Source-to-drain diode forward voltage I = ma 5 V IF = 35 ma, See Note 3.8. V VOH VOL High-level output voltage, IOH = µa VCC. VCC SER OUT IOH = 4 ma VCC.CC. Low-level output voltage, IOL = µa. SER OUT IOL = 4 ma..5 IIH High-level input current VI = VCC µa IIL Low-level input current VI = µa IO(chop) Output current at which chopping starts TC = 5 C, See Note 5 and Figures 3 and 4 V V.6.8. A ICC Logic supply current IO =, VI = VCC or.5 5 ma ICC(FRQ) I(nom) I Logic supply current at frequency Nominal current rain current, off-state Static drain-source on-state rs(on) ( resistance f = 5 MHz, IO =, CL = 3 pf, VI = VCC or, VCC =, See Figure 7 VS(on) =., I(nom) = I, TC = 85 C, VCC =, See Notes 5, 6, and 7.3 ma 35 ma VS = 4 V, TC = 5 C. VS = 4 V, TC = 5 C. 5 I = 35 ma, TC = 5 C I = 35 ma, TC = 5 C I = 35 ma, TC = 4 C See Notes 5 and 6 and Figures and.5 µa.7.5 Ω NOTES: 3. Pulse duration µs and duty cycle %. 5. Technique should limit TJ TC to C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of. at TC = 85 C. POST OFFICE BOX ALLAS, TEXAS

6 SLIS5A APRIL 993 REVISE JANUARY 995 switching characteristics, V CC =, T C = 5 C PARAMETER TEST CONITIONS MIN TYP MAX UNIT tphl Propagation delay time, high-to-low-level output from 3 ns tplh Propagation delay time, low-to-high-level output from CL = 3 pf, I = 35 ma, 5 ns tr Rise time, drain output See Figures,, and 6 ns tf Fall time, drain output 3 ns ta Reverse-recovery-current rise time IF = 35 ma, di/dt = A/µs, ns trr Reverse-recovery time See Notes 5 and 6 and Figure 5 3 ns NOTES: 5. Technique should limit TJ TC to C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. thermal resistance RθJC RθJA PARAMETER TEST CONITIONS MIN MAX UNIT W Thermal resistance, junction-to-case to case All eight outputs with equal power C/W NE W 5 Thermal resistance, junction-to-ambient to All eight outputs with equal power C/W NE 5 6 POST OFFICE BOX ALLAS, TEXAS 7565

7 PARAMETER MEASUREMENT INFORMATION SLIS5A APRIL 993 REVISE JANUARY 995 Word enerator (see Note A) VCC UT LN TEST CIRCUIT RAIN I 4 V RL = 68 Ω Output CL = 3 pf (see Note B) RAIN,, 4, 5 RAIN, 3, 6, V V V V V 4 V. 4 V. VOLTAE WAVEFORMS NOTES: A. The word generator has the following characteristics: tr ns, tf ns, tw = 3 ns, pulsed repetition rate (PRR) = 5 khz, ZO = 5 Ω. B. CL includes probe and jig capacitance. Figure. Resistive Load Operation Word enerator (see Note A) VCC LN TEST CIRCUIT 4 V UT RAIN I RL = 68 Ω Output CL = 3 pf (see Note B) Output 5% 5% V tplh tphl 4 V 9% 9% % %. tr tf SWITCHIN TIMES 5% V tsu th 5% 5% V tw INPUT SETUP AN HOL WAVEFORMS NOTES: A. The word generator has the following characteristics: tr ns, tf ns, tw = 3 ns, pulsed repetition rate (PRR) = 5 khz, ZO = 5 Ω. B. CL includes probe and jig capacitance. Figure. Test Circuit, Switching Times, and Voltage Waveforms POST OFFICE BOX ALLAS, TEXAS

8 SLIS5A APRIL 993 REVISE JANUARY 995 PARAMETER MEASUREMENT INFORMATION.5 OUTPUT CURRENT TIME FOR INCREASIN LOA RESISTANCE REION CURRENT WAVEFORM I O Output Current A Region Region Time IOK (see Notes A and B) IOK I O Output Current t t t 4 µs t.5 ms t t t Time First output current pulses after turn-on in chopping mode with resistive load. NOTES: A. Figure 3 illustrates the output current characteristics of the device energizing a load having initially low, increasing resistance, e.g., an incandescent lamp. In region, chopping occurs and the peak current is limited to IOK. In region, output current is continuous. The same characteristics occur in reverse order when the device energizes a load having an initially high, decreasing resistance. B. Region duty cycle is approximately %. Figure 3. Chopping-Mode Characteristics.5 OUTPUT CURRENT LIMIT CASE TEMPERATURE I O Output Current Limit A VCC = 5. VCC = TC Case Temperature C Figure POST OFFICE BOX ALLAS, TEXAS 7565

9 PARAMETER MEASUREMENT INFORMATION SLIS5A APRIL 993 REVISE JANUARY 995 RAIN TP K Circuit Under Test IF (see Note B) L = mh 5 µf 5 V + 4 V TP A.35 A IF di/dt = A/µs t 5% of IRM t t3 R river IRM (see Note C) V (see Note A) 5 Ω ta trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The V amplitude and R are adjusted for di/dt = A/µs. A V double-pulse train is used to set IF =.35 A, where t = µs, t = 7 µs, and t3 = 3 µs. B. The RAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. C. IRM = maximum recovery current Figure 5. Reverse-Recovery-Current Test Circuit and Waveforms of Source-rain iode Word enerator (see Note A) VCC UT RAIN I Ω mh VS Input I tw See Note B tav V IAS = 6 ma LN VS V(BR)SX = 5 V MIN SINLE-PULSE AVALANCHE ENERY TEST CIRCUIT VOLTAE AN CURRENT WAVEFORMS Non JEEC symbol for avalanche time. NOTES: A. The word generator has the following characteristics: tr ns, tf ns, ZO = 5 Ω. B. Input pulse duration, tw, is increased until peak current IAS = 6 ma. Energy test level is defined as EAS = (IAS V(BR)SX tav)/ = 75 mj. Figure 6. Single-Pulse Avalanche Energy Test Circuit and Waveforms POST OFFICE BOX ALLAS, TEXAS

10 SLIS5A APRIL 993 REVISE JANUARY 995 TYPICAL CHARACTERISTICS I CC Supply Current ma VCC = SUPPLY CURRENT FREQUENCY TJS = 4 C to 5 C Maximum Continuous rain Current of Each Output A I MAXIMUM CONTINUOUS RAIN CURRENT OF EACH OUTPUT NUMBER OF OUTPUTS CONUCTIN SIMULTANEOUSLY TA = 5 C TA = C TA = 5 C VCC =. f Frequency MHz Figure N Number of Outputs Conducting Simultaneously Figure 8 Maximum Peak rain Current of Each Output A M I MAXIMUM PEAK RAIN CURRENT OF EACH OUTPUT NUMBER OF OUTPUTS CONUCTIN SIMULTANEOUSLY d = 5% d = 8% VCC = TA = 5 C d = tw/tperiod d = ms/tperiod d = % N Number of Outputs Conducting Simultaneously Figure 9 Static rain-source On-State Resistance Ω r S(on) STATIC RAIN-SOURCE ON-STATE RESISTANCE RAIN CURRENT TC = 5 C TC = 5 C TC = 4 C Current Limit VCC = See Note A I rain Current A NOTE A: Technique should limit TJ TC to C maximum. Figure POST OFFICE BOX ALLAS, TEXAS 7565

11 TYPICAL CHARACTERISTICS SLIS5A APRIL 993 REVISE JANUARY 995 Static rain-source On-State Resistance Ω r S(on) STATIC RAIN-SOURCE ON-STATE RESISTANCE LOIC SUPPLY VOLTAE I = 35 ma See Note A TC = 5 C TC = 5 C TC = 4 C VCC Logic Supply Voltage V Figure NOTE A: Technique should limit TJ TC to C maximum. Switching Time ns I = 35 ma See Note A SWITCHIN TIME CASE TEMPERATURE tplh tr tf TC Case Temperature C Figure tphl THERMAL INFORMATION Z θ JA Transient Thermal Impedance C /W NE PACKAE TRANSIENT THERMAL IMPEANCE ON TIME d = 5% d = % d = % d = 5% d = % Single Pulse.... t On Time s Where: The single-pulse curve represents measured data. The curves for various pulse durations are based on the following equation: Z JA # t w tc # R JA # t w tc # Z. tw t c. Z. tw. Z. tc. Z. tw t c. Z. tw. Z. tc. = the single-pulse thermal impedance for t = tw seconds = the single-pulse thermal impedance for t = tc seconds = the single-pulse thermal impedance for t = tw + tc seconds d = tw/tc tw tc I Figure 3 POST OFFICE BOX ALLAS, TEXAS 7565

12 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USIN SEMICONUCTOR PROUCTS MAY INVOLVE POTENTIAL RISKS OF EATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL AMAE ( CRITICAL APPLICATIONS ). TI SEMICONUCTOR PROUCTS ARE NOT ESINE, AUTHORIZE, OR WARRANTE TO BE SUITABLE FOR USE IN LIFE-SUPPORT EVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PROUCTS IN SUCH APPLICATIONS IS UNERSTOO TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright, Texas Instruments Incorporated

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH POWER LOGIC OCTAL -TYPE LATC Low r S(on)... Ω Typical Avalanche Energy...3 mj Eight Power MOS-Transistor Outputs of -ma Continuous Current -ma Typical Current-Limiting Capability Output Clamp Voltage...

More information

TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH

TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH POWER OIC 8-BIT ARESSABE ATC ow r S(on).... Ω Typical Avalanche Energy...75 mj Eight Power MOS Transistor Outputs of 5-mA Continuous Current.5-A Pulsed Current Per Output Output Clamp Voltage at Four istinct

More information

TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH

TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH POWER OIC -BIT ARESSABE ATC ow r S(on)...5 Ω Typical Avalanche Energy... mj Eight Power MOS-Transistor Outputs of 15-mA Continuous Current 5-mA Typical Current-imiting Capability Output Clamp Voltage...

More information

description logic symbol

description logic symbol Low r S(on)...5 Ω Typical Avalanche Energy... 0 mj Eight Power MOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage...5 evices Are Cascadable

More information

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits

More information

SN75150 DUAL LINE DRIVER

SN75150 DUAL LINE DRIVER Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through

More information

SN QUADRUPLE HALF-H DRIVER

SN QUADRUPLE HALF-H DRIVER -A -Current Capability Per Driver Applications Include Half-H and Full-H Solenoid Drivers and Motor Drivers Designed for Positive-Supply Applications Wide Supply-Voltage Range of 4.5 V to 6 V TTL- and

More information

SN75158 DUAL DIFFERENTIAL LINE DRIVER

SN75158 DUAL DIFFERENTIAL LINE DRIVER SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup

More information

MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER

MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed

More information

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997 Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits

More information

SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic

More information

TPIC3322L 3-CHANNEL COMMON-DRAIN LOGIC-LEVEL POWER DMOS ARRAY

TPIC3322L 3-CHANNEL COMMON-DRAIN LOGIC-LEVEL POWER DMOS ARRAY Low r DS(on)....6 Ω Typ High-Voltage Outputs...6 V Pulsed Current...5 A Per Channel Fast Commutation Speed Direct Logic-Level Interface description SOURCE GATE SOURCE SOURCE3 D PACKAGE (TOP VIEW) 3 4 8

More information

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline

More information

ua9637ac DUAL DIFFERENTIAL LINE RECEIVER

ua9637ac DUAL DIFFERENTIAL LINE RECEIVER ua967ac Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and EIA/TIA--B and ITU Recommendations V. and V. Operates From Single -V Power Supply Wide Common-Mode Voltage Range High Input Impedance

More information

SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS

SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility

More information

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline

More information

ULN2804A DARLINGTON TRANSISTOR ARRAY

ULN2804A DARLINGTON TRANSISTOR ARRAY HIGH-VOLTAGE, HIGH-CURRENT 500-mA-Rated Collector Current (Single ) High-Voltage s...50 V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications Compatible With ULN2800A-Series

More information

SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT

SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT and Open-Drain Accept Voltages up to 5.5 V Supports 5-V V CC Operation description This single inverter buffer/driver is designed for 1.65-V to 5.5-V V CC operation. DBV OR DCK PACKAGE (TOP VIEW) NC A

More information

SN75468, SN75469 DARLINGTON TRANSISTOR ARRAYS

SN75468, SN75469 DARLINGTON TRANSISTOR ARRAYS SLRSB DECEMBER REVISED SEPTEMBER HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications

More information

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency

More information

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH

TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH POWER LOGIC OCTAL -TYPE LATCH Low r S(on)...5 Ω Typical Avalanche Energy...30 mj Eight Power MOS-Transistor Outputs of 50-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage...

More information

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and

More information

SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers

More information

SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS

SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption... 5 mw Typ Wide Driver Supply Voltage Range... ±4.5 V to ±15 V Driver Output Slew Rate Limited to

More information

SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =

More information

L293, L293D QUADRUPLE HALF-H DRIVERS

L293, L293D QUADRUPLE HALF-H DRIVERS Featuring Unitrode L and LD Products Now From Texas Instruments Wide Supply-Voltage Range:.5 V to V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional

More information

SN75150 DUAL LINE DRIVER

SN75150 DUAL LINE DRIVER Meets or Exceeds the Requirement of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Max Transition Time

More information

54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES

54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)

More information

TPIC CHANNEL COMMON-SOURCE POWER DMOS ARRAY

TPIC CHANNEL COMMON-SOURCE POWER DMOS ARRAY TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 Seven.-A Independent Output Channels Integrated Clamp Diode With Each Output Low r DS(on).... Ω Typical Output Voltage... 6 V Pulsed Current... A Per Channel

More information

SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES

SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain

More information

SN75374 QUADRUPLE MOSFET DRIVER

SN75374 QUADRUPLE MOSFET DRIVER SLRS28 SEPTEMBER 1988 Quadruple Circuits Capable of Driving High-Capacitance Loads at High Speeds Output Supply Voltage Range From 5 V to 24 V Low Standby Power Dissipation V CC3 Supply Maximizes Output

More information

SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS

SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)

More information

SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =

More information

SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages,

More information

description DRAIN2 DRAIN3 SRCLR G PGND PGND RCK SRCK DRAIN4 DRAIN5 DRAIN1 DRAN0 SER IN V CC PGND PGND LGND SER OUT DRAIN7 DRAIN6 DRAIN2 DRAIN3 SRCLR G

description DRAIN2 DRAIN3 SRCLR G PGND PGND RCK SRCK DRAIN4 DRAIN5 DRAIN1 DRAN0 SER IN V CC PGND PGND LGND SER OUT DRAIN7 DRAIN6 DRAIN2 DRAIN3 SRCLR G Low r S(on)...1 Ω Typ Output Short-Circuit Protection Avalanche Energy... 75 mj Eight 35-mA MOS Outputs 5-V Switching Capability evices Are Cascadable Low Power Consumption description The TPIC6A595 is

More information

ULN2001A, ULN2002A, ULN2003A, ULN2004A DARLINGTON TRANSISTOR ARRAYS

ULN2001A, ULN2002A, ULN2003A, ULN2004A DARLINGTON TRANSISTOR ARRAYS ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver

More information

SN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS

SN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial-Port Connector Less Than 9-mW Power Consumption Wide Driver Supply

More information

PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description

PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink

More information

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description

More information

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997 High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and

More information

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

More information

ULN2001A THRU ULN2004A DARLINGTON TRANSISTOR ARRAYS

ULN2001A THRU ULN2004A DARLINGTON TRANSISTOR ARRAYS ULNA THRU ULNA SLRS D, DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver

More information

SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS

SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SN, SN7 Choice of Open-Collector or Active Pullup (Totem-Pole) Outputs Single -V Supply Differential Line Operation Dual-Channel Operation TTL Compatible ± -V Common-Mode Input Voltage Range Optional-Use

More information

SN75174 QUADRUPLE DIFFERENTIAL LINE DRIVER

SN75174 QUADRUPLE DIFFERENTIAL LINE DRIVER SN Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and RS-8 and ITU Recommendation V.. Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments -State s Common-Mode Voltage

More information

AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER

AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data

More information

SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin

More information

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997 Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline

More information

SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995

SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995 Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance

More information

SN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS

SN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial Port Connector Less Than 9-mW Power Consumption Wide Driver Supply

More information

SN74S ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS

SN74S ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped

More information

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at   ore.hu. EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping

More information

SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand

More information

SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline

More information

MAX232, MAX232I DUAL EIA-232 DRIVER/RECEIVER

MAX232, MAX232I DUAL EIA-232 DRIVER/RECEIVER Operates With Single -V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 0-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-22-F and ITU Recommendation

More information

L293D QUADRUPLE HALF-H DRIVER

L293D QUADRUPLE HALF-H DRIVER 00-m Current Capability Per Driver Pulsed Current.- Per Driver Clamp Diodes for Inductive Transient Suppression Wide Supply Voltage Range 4.5 V to V Separate -ogic Supply Thermal Shutdown Internal ESD

More information

74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio

More information

SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as HC00 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB),

More information

MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A QUADRUPLE LINE RECEIVERS

MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A QUADRUPLE LINE RECEIVERS MC89, MC89A, SN89, SN89A, SN789, SN789A SLLS9B SEPTEMPER 97 REVISED MAY 99 Input Resistance... kω to 7 kω Input Signal Range...± V Operate From Single -V Supply Built-In Input Hysteresis (Double Thresholds)

More information

PCA8550 NONVOLATILE 5-BIT REGISTER WITH I 2 C INTERFACE

PCA8550 NONVOLATILE 5-BIT REGISTER WITH I 2 C INTERFACE EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V Signals are 2.5-V Outputs Signal is a 3.3-V Output Minimum

More information

SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS

SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS Meet or Exceed the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Very Low Power Consumption 5 mw Typ Wide Driver Supply Voltage Range ±4.5 V to ±15 V Driver Output Slew Rate Limited to

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry

More information

SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER

More information

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

More information

SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS -State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,

More information

SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS

SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD

More information

MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS

MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11 3-State, TTL-Compatible s Fast Transition Times Operates From Single 5-V Supply

More information

TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER

TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER 8-Bit Resolution Linearity... ±1/2 LSB Maximum Differential Nonlinearity...±1/2 LSB Maximum Conversion Rate...60 MHz Min Nominal Output Signal Operating Range V CC to V CC 1 V TTL Digital Input Voltage

More information

SN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and

More information

SN54HC04, SN74HC04 HEX INVERTERS

SN54HC04, SN74HC04 HEX INVERTERS SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),

More information

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic

More information

SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in

More information

SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)

More information

CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES

CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES 4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and

More information

SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input exclusive-or

More information

description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND

description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER

More information

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators

More information

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE

More information

SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical

More information

54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm

More information

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage

More information

SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS

SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SN676B, SN776B Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus

More information

TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS

TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS Low r DS(on)... 0.18 Ω at V GS = 10 V 3-V Compatible Requires No External V CC TTL and CMOS Compatible Inputs V GS(th) = 1.5 V Max ESD Protection Up to 2 kv per MIL-STD-883C, Method 3015 1SOURCE 1GATE

More information

SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline

More information

54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture

More information

74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 74ACT62 Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching

More information

54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS

54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS032A JUL 187 REVISED APRIL 13 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed

More information

description 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1

description 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1 SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These

More information

SN74ACT STROBED FIRST-IN, FIRST-OUT MEMORY

SN74ACT STROBED FIRST-IN, FIRST-OUT MEMORY Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable

More information

ULN2001A, ULN2002A, ULN2003A, ULN2004A, ULQ2003A, ULQ2004A, HIGH-VOLTAGE HIGH-CURRENT DARLINGTON TRANSISTOR ARRAY

ULN2001A, ULN2002A, ULN2003A, ULN2004A, ULQ2003A, ULQ2004A, HIGH-VOLTAGE HIGH-CURRENT DARLINGTON TRANSISTOR ARRAY The ULNA is obsolete -ma Rated Collector Current (Single ) High-oltage s... Clamp Diodes ULNA, ULNA, ULNA, ULNA, ULQA, ULQA, SLRSC DECEMBER REISED MAY Inputs Compatible With arious Types of Logic Relay

More information

SN75446, SN75447 DUAL PERIPHERAL DRIVERS

SN75446, SN75447 DUAL PERIPHERAL DRIVERS , DUA PERIPERA DRIVER R00A DECEMBER 98 REVIED NOVEMBER 99 Very ow Power Requirements Very ow Input Current Characterized for Use to 0 ma No atch-up at (After Conducting 00 ma) igh-voltage s ( Min) Clamp

More information

MAX232, MAX232I DUAL EIA-232 DRIVER/RECEIVER

MAX232, MAX232I DUAL EIA-232 DRIVER/RECEIVER Operates With Single 5-V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 30-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-232-F and ITU Recommendation

More information

SN65LVDM31 HIGH-SPEED DIFFERENTIAL LINE DRIVER

SN65LVDM31 HIGH-SPEED DIFFERENTIAL LINE DRIVER HIH-SPEED DIFFERENTIAL LINE DRIVER Designed for Signaling Rates Up to 5 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 7 mv and a -Ω Load Propagation Delay Time of. ns, Typical

More information

TL780 SERIES POSITIVE-VOLTAGE REGULATORS

TL780 SERIES POSITIVE-VOLTAGE REGULATORS ±1% Output Tolerance at ±2% Output Tolerance Over Full Operating Range Thermal Shutdown description Internal Short-Circuit Current Limiting Pinout Identical to µa7800 Series Improved Version of µa7800

More information

6N135, 6N136, HCPL4502 OPTOCOUPLERS/OPTOISOLATORS

6N135, 6N136, HCPL4502 OPTOCOUPLERS/OPTOISOLATORS Compatible with TTL Inputs High-Speed Switching... Mbit/s Typ Bandwidth...2 MHz Typ High Common-Mode Transient Immunity... 000 V/µs Typ High-Voltage Electrical Insulation... 3000 Vdc Min Open-Collector

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has

More information

SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS

SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS N TRU N8 DUA PERIPERA DRIVER R0 DECEMBER 9 REVIED NOVEMBER 99 Characterized for Use to 00 ma No atch-up at V (After Conducting 00 ma) igh-voltage s (0 Typ) Clamp Diodes for Transient uppression (00 ma,

More information

NE5532, NE5532A DUAL LOW-NOISE OPERATIONAL AMPLIFIERS

NE5532, NE5532A DUAL LOW-NOISE OPERATIONAL AMPLIFIERS Equivalent Input Noise Voltage 5 nv/ Hz Typ at 1 khz Unity-Gain Bandwidth... 10 MHz Typ Common-Mode Rejection Ratio... 100 db Typ High dc Voltage Gain... 100 V/mV Typ Peak-to-Peak Output Voltage Swing

More information

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994 WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage

More information

74AC11873 DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS095 JANUARY 1990 REVISED APRIL 1993

74AC11873 DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS095 JANUARY 1990 REVISED APRIL 1993 3-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance

More information