TPIC CHANNEL COMMON-SOURCE POWER DMOS ARRAY
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1 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 Seven.-A Independent Output Channels Integrated Clamp Diode With Each Output Low r DS(on).... Ω Typical Output Voltage... 6 V Pulsed Current... A Per Channel Avalanche Energy... mj description The TPIC7 is a monolithic power DMOS transistor array that consists of seven independent N-channel enhancement-mode DMOS transistors connected in a common-source configuration with open drains. The TPIC7 is pin-for-pin functionally compatible with the Texas Instruments ULNA through ULNA. The TPIC7 is characterized for operation over a temperature range of C to C.The TPIC7M is characterized for operation over the full military temperature range of C to C. logic diagram GATE GATE 9 6 CLAMP DRAIN DRAIN GATE GATE GATE GATE GATE GATE6 GATE7 SOURCE GATE GATE GATE NC NC GATE GATE NC GATE6 GATE7 SOURCE SOURCE TPIC7 N PACKAGE (TOP VIEW) TPIC7M J PACKAGE (TOP VIEW) DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN6 DRAIN7 CLAMP DRAIN DRAIN DRAIN NC NC DRAIN DRAIN NC DRAIN6 DRAIN7 CLAMP SOURCE GATE DRAIN NC No internal connection Refer to the mechanical data for the JW package. GATE DRAIN GATE DRAIN GATE6 6 DRAIN6 GATE7 7 DRAIN7 8 SOURCE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 996, Texas Instruments Incorporated POST OFFICE BOX 6 DALLAS, TEXAS 76
2 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-source voltage, V DS V Gate-source voltage, V GS ± V Clamp-drain voltage, V CD V Continuous source-drain diode current A Pulsed drain current, each output, I D (see Note and Figure 7) A Pulsed clamp current, I CL (see Note and Figure 8) A Continuous drain current, each output, all outputs on A Single-pulse avalanche energy, E AS (see Figure ) mj Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, T J :TPIC C to C TPIC7M C to C Operating case temperature range, T C: TPIC C to C TPIC7M C to C Storage temperature range, T stg C to C Lead temperature,6 mm (/6 inch) from case for seconds: N Package C Lead temperature,6 mm (/6 inch) from case for seconds: J Package C NOTE : Pulse duration = ms, duty cycle = 6%. PACKAGE TA C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = C TA = 7 C POWER RATING TA = 8 C POWER RATING TA = C POWER RATING J 66 mw. mw/ C 7 mw 8 mw mw N mw. mw/ C 9 mw 7 mw mw electrical characteristics, T C = C (unless otherwise noted) PARAMETER TEST CONDITIONS TPIC7 MIN TYP MAX V(BR)DS Drain-source breakdown voltage ID = µa, VGS = 6 V VTGS Gate-source threshold voltage ID = ma, VDS = VGS..7. V VDS(on) Drain-source on-state voltage ID =. A, VGS = V,.. V See Notes and TC = C. IDSS Zero-gate-voltage drain current VDS =8V V, VGS = µa TC = C. IGSSF IGSSR Forward gate current, drain short circuited to source Reverse gate current, drain short circuited to source VGS = V, VDS = na VGS = V, VDS = na VGS = V, ID =. A, TC = C..8 rds(on) Forward drain-source on-state resistance See Notes and and Figures and 6 TC = C.8. g fs Forward transconductance VDS = V, ID =. A,..8 S See Notes and Ciss Short-circuit input capacitance, common source Coss Short-circuit output capacitance, common source 6 VDS =V V, VGS =, f = khz pf Short-circuit reverse transfer capacitance, Crss common source NOTES:. Technique should limit TJ TC to C maximum.. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts with a single output transistor conducting. Ω POST OFFICE BOX 6 DALLAS, TEXAS 76
3 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 electrical characteristics over case temperature operating range (unless otherwise noted) (see Note ) TPIC7M PARAMETER TEST CONDITIONS TC MIN TYP MAX V(BR)DS Drain-to-source breakdown voltage ID = µa, VGS = C ID = ma, VGS = Full range 6 V VTGS Gate-to-source input threshold voltage ID = ma, VDS = VGS Full range..7. V VDS(on) Drain-to-source on-state voltage ID =. A, VGS = V IDSS Zero-gate-voltage drain current VDS =8V V, VGS = IGSSF IGSSR Forward gate current, drain short-circuited to source Reverse gate current, drain short-circuited to source VGS =V V, VDS = VGS = V, VDS = rds(on) Forward drain-source on-state resistance VGS =V V, ID=A. C.. Full range.6 C. Full range V µa C na Full range µa C na Full range µa C..9 Full range. g fs Forward transconductance VDS = V, ID =. A C.8 S Ciss Short-circuit input capacitance, common source Coss Short-circuit output capacitance, common source VDS = V, VGS =, 6 Full range pf Short-circuit reverse transfer capacitance, f = khz Crss common source Full range is C to C. NOTE : Pulse testing techniques are used to maintain the virtual junction temperature as close to the case temperature as possible. Thermal effects must be taken into account separately. source-drain diode characteristics, T C = C PARAMETER TEST CONDITIONS TPIC7 MIN TYP MAX VSD Forward On voltage IS =. A, VGS =.9. V trr(sd) Reverse-recovery time IS S =. A, VGS =, VDS = 8 V, 6 ns QRR Total source-drain diode charge di/dt = A/µs, See Figure nc Ω source-to-drain diode characteristics over operating case temperature range (unless otherwise noted) (see Note ) TPIC7M PARAMETER TEST CONDITIONS MIN TYP MAX VSD Forward On voltage IS =. A, VGS =.9. V trr Reverse recovery time IS S =. A, VGS =, VDS = 8 V, 6 ns QRR Total source-to-drain diode charge di/dt = A /µs, TC = C, See Figure nc NOTE : Pulse testing techniques are used to maintain the virtual junction temperature as close to the case temperature as possible. Thermal effects must be taken into account separately. POST OFFICE BOX 6 DALLAS, TEXAS 76
4 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 clamp diode characteristics, T C = C TPIC7 PARAMETER TEST CONDITIONS MIN TYP MAX VF Forward on-voltage IF =. A. V VBR Breakdown voltage IR = µa 6 V IR Reverse leakage current VR = 8 V. µa trr(cd) Reverse-recovery time IF F =. A, di/dt = A/µs, 9 ns QRR Total source-drain diode charge VCD = 8 V, See Figure nc clamp diode characteristics over operating case temperature range (unless otherwise noted) (see Note ) PARAMETER TEST CONDITIONS TPIC7M MIN TYP MAX VF Forward voltage IF =. A. V V(BR) Breakdown voltage IR = µa, TC = C IR = ma IR Reverse leakage current VR = 8 V 6 V TC = C. trr(sd) Reverse recovery time, source-to-drain IF F =. A, di/dt = A /µs, TC = C 9 ns QRR Total source-to-drain diode charge VCD = 8 V, See Figure nc NOTE : Pulse testing techniques are used to maintain the virtual junction temperature as close to the case temperature as possible. Thermal effects must be taken into account separately. resistive-load switching characteristics, T C = C PARAMETER TEST CONDITIONS TPIC7 MIN TYP MAX td(on) Turn-on delay time td(off) Turn-off delay time VDD = V, RL = Ω,, ten = ns, tr Rise time tdis = ns, See Figure tf Fall time Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDS = 8 V, ID =. A, VGS = V, See Figure.8.6 µa ns.6 nc..6 POST OFFICE BOX 6 DALLAS, TEXAS 76
5 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 resistive-load switching characteristics over operating case temperature range (unless otherwise noted) (see Note ) PARAMETER TEST CONDITIONS TPIC7M MIN TYP MAX td(on) Turn-on delay time td(off) Turn-off delay time VDD = V, RL = Ω,, ten = ns, tr Rise time tdis = ns, See Figure tf Fall time Qg Qgs Qgd NOTE : Total gate charge Gate-to-source charge Gate-to-drain charge VDS = 8 V, ID =. A, VGS = V, See Figure.8 ns.6 nc Pulse testing techniques are used to maintain the virtual junction temperature as close to the case temperature as possible. Thermal effects must be taken into account separately. thermal resistance RθJA PARAMETER TEST CONDITIONS MIN TYP MAX N package with all outputs at equal power 9 Junction-to-ambient thermal resistance C/W J package with all outputs at equal power 66. PARAMETER MEASUREMENT INFORMATION. A IF/IS di/dt = A/µs QRR = Shaded Area % of IRM IRM (see Note A) trr NOTE A: IRM = maximum recovery current Figure. Reverse-Recovery-Current Waveforms of Source-Drain and Clamp Diodes POST OFFICE BOX 6 DALLAS, TEXAS 76
6 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 PARAMETER MEASUREMENT INFORMATION V Pulse Generator VGS RL VDS VGS ten 9% % 9% tdis V DUT Rgen Ω Ω td(on) VDS % td(off) VDD 9% VDS(on) tf tr VOLTAGE WAVEFORM TEST CIRCUIT Figure. Resistive Switching Current Regulator Qg -V Battery. µf kω. µf Same Type as DUT VDD = 8 V V VGS Qgd IG = µa DUT Gate Voltage Time IG Current- Sampling Resistor ID Current- Sampling Resistor Qgs = Qg Qgd WAVEFORM TEST CIRCUIT Figure. Gate Charge Test Circuit and Waveform 6 POST OFFICE BOX 6 DALLAS, TEXAS 76
7 TPIC7 PARAMETER MEASUREMENT INFORMATION V SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 mh tw tav V Pulse Generator (see Note A) Rgen Ω VGS Ω ID VDS DUT VGS ID VDS IAS (see Note B) V(BR)DSX = 6 V Min VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr ns, tf ns, ZO = Ω. B. Input pulse duration (tw) is increased until peak current IAS =. A. Energy test level is defined as E AS I AS V (BR)DSX t av mj min. Figure. Single-Pulse Avalanche Energy Test Circuit and Waveforms POST OFFICE BOX 6 DALLAS, TEXAS 76 7
8 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 STATIC DRAIN-SOURCE ON-STATE RESISTANCE FREE-AIR TEMPERATURE.9.8 TYPICAL CHARACTERISTICS ID =. A TA = C.9 STATIC DRAIN-SOURCE ON-STATE RESISTANCE DRAIN CURRENT r DS(on) Static Drain-Source On-State Resistance Ω VGS = V VGS = V r DS(on) Static Drain-Source On-State Resistance Ω VGS = 6 V VGS = V VGS = V.. 7 TA Free-Air Temperature C.. ID Drain Current A. Figure Figure 6 Percentage of Units % DISTRIBUTION OF FORWARD TRANSCONDUCTANCE TA = C ID =. A VDS = V gfs Forward Transconductance S I D Drain-to-Source Current A... DRAIN-TO-SOURCE CURRENT DRAIN-TO-SOURCE VOLTAGE TA = C VGS = V VGS =. V VGS = V. VGS =. V. VGS = V VGS =. V VDS Drain-to-Source Voltage V Figure 7 Figure 8 8 POST OFFICE BOX 6 DALLAS, TEXAS 76
9 TPIC7 TYPICAL CHARACTERISTICS SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 Gate-Source Threshold Voltage V V TGS... GATE-SOURCE THRESHOLD VOLTAGE FREE-AIR TEMPERATURE ID = ma ID = ma V GS Gate-Source Voltage V ID =. A TA = C GATE-SOURCE VOLTAGE GATE CHARGE VDS = V VDS = 8 V VDS = V 7 TA Free-Air Temperature C Q Gate Charge nc Figure 9 Figure Source-to-Drain Diode Current A ISD SOURCE-TO-DRAIN DIODE CURRENT SOURCE-TO-DRAIN DIODE VOLTAGE TA = C TA = C Source-to-Drain Diode Current A I SD... SOURCE-TO-DRAIN DIODE CURRENT SOURCE-TO-DRAIN DIODE VOLTAGE TA = C VSD Source-to-Drain Diode Voltage V VSD Source-to-Drain Diode Voltage V Figure Figure POST OFFICE BOX 6 DALLAS, TEXAS 76 9
10 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 TYPICAL CHARACTERISTICS Clamp-Diode Current A... TA = C CLAMP-DIODE CURRENT CLAMP-DIODE VOLTAGE Clamp-Diode Voltage V Clamp-Diode Reverse Recovery Time ns t rr CLAMP-DIODE REVERSE RECOVERY TIME REVERSE di/dt IF =. A VR = 8 V TA = C Reverse di/dt A/µs Figure Figure 6 TA = C REVERSE di/dt FORWARD CURRENT VCD = V µ s Reverse di/dt A/ 6 6 VCD = V.. IF Forward Current A NOTE A: VCD = Vclamp Vdrain Figure POST OFFICE BOX 6 DALLAS, TEXAS 76
11 TPIC7 TYPICAL CHARACTERISTICS SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 VDS = 7. V RL =. Ω IG = µa TA = C 6 VDS Drain-Source Voltage V VDS = V VDS = V VDS =. V Gate-Source Voltage VDS = 7. V 8 6 V GS Gate-Source Voltage V Drain-Source Voltage t Time µs Figure 6. Resistive Switching Waveforms POST OFFICE BOX 6 DALLAS, TEXAS 76
12 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 THERMAL INFORMATION I D Maximum Drain Current A N = N = MAXIMUM DRAIN CURRENT DUTY CYCLE TA = C N = Number of Outputs Conducting Simultaneously See Note A N =.8.6 N =. N =. N = Duty Cycle % I CL Maximum Clamp-Diode Current A MAXIMUM CLAMP-DIODE CURRENT DUTY CYCLE N =.8 TA = C N = Number of Outputs.6 Conducting Simultaneously. See Note A..8.6 N =.. N = N = N = N = Duty Cycle % Figure 7 Figure 8 NOTE A: For Figures 7 and 8, d = tw/tc = ms / tc, where tw and tc are defined by the following: tw tc IAS Peak Avalanche Current A PEAK AVALANCHE CURRENT TIME DURATION OF AVALANCHE TA = C TA = C Maximum Drain-Diode DCurrent A I D MAXIMUM DRAIN CURRENT DRAIN-SOURCE VOLTAGE rds(on) Limit DC ms Thermal Limit... tav Time Duration of Avalanche ms. TA = C.. VDS Drain-To-Source Voltage V Figure 9 Figure POST OFFICE BOX 6 DALLAS, TEXAS 76
13 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 JW (R-GDIP-T) MECHANICAL INFORMATION CERAMIC DUAL-IN-LINE PACKAGE.9 (,8). (,).6 (,). (,).7 (,78) MAX. (,).6 (,).7 (,78). (,). (,7). (,8).6 (,).9 (,99) Seating Plane. (,). (,).6 (,6).6 (,). (,7). (,).8 (,) / B /9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only E. Falls within MIL-STD-8 GDIP-T POST OFFICE BOX 6 DALLAS, TEXAS 76
14 TPIC7 SLIS9A SEPTEMBER 99 REVISED SEPTEMBER 996 N (R-PDIP-T**) 6 PIN SHOWN MECHANICAL INFORMATION PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** 6 8 A A MAX.77 (9,69).77 (9,69).9 (.7).97 (,77) 6 9 A MIN.7 (8,9).7 (8,9).8 (.9).9 (,88).6 (6,6). (6,) 8.7 (,78) MAX. (,89) MAX. (,) MIN. (7,87).9 (7,7). (,8) MAX. (,8) MIN Seating Plane. (,). (,). (,8). (,) M. (,) NOM /8 PIN ONLY 9/C 8/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS- ( pin package is shorter then MS-.) POST OFFICE BOX 6 DALLAS, TEXAS 76
15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Instruments Incorporated
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N-channel 600 V, 0.045 Ω typ., 52 A MDmesh M2 Power MOSFET in a TO247-4 package Datasheet - production data Features Order code VDS @ TJmax RDS(on) max ID STW56N60M2-4 650 V 0.055 Ω 52 A Excellent switching
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N-channel 800 V, 1.50 Ω typ., 4 A MDmesh K5 Power MOSFET in a TO-220 package Datasheet - production data Features Order code VDS RDS(on) max. ID STP5N80K5 800 V 1.75 Ω 4 A Industry s lowest RDS(on) x area
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N-channel 30 V, 2.15 mω typ., 120 A Power MOSFET in a TO-220 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STP200N3LL 30 V 2.4 mω 120 A 176.5 W Very low on-resistance
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P-channel 20 V, 0.087 Ω typ., 3 A STripFET H7 Power MOSFET in a SOT23-6L package Datasheet - production data Features Order code VDS RDS(on) max ID STT3P2UH7 20 V 0.1 Ω @ 4.5 3 A SOT23-6L Very low on-resistance
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More informationFeatures. Description. Table 1: Device summary Order code Marking Package Packaging STR1P2UH7 1L2U SOT-23 Tape and reel
P-channel 20 V, 0.087 Ω typ., 1.4 A STripFET H7 Power MOSFET in a SOT-23 package Datasheet - production data Features Order code VDS RDS(on) max ID STR1P2UH7 20 V 0.1 Ω @ 4.5 1.4 A Very low on-resistance
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Features: Super high dense cell design for low R DS(ON) Rugged and reliable Surface Mount Package B VDSS =20V, R DS(ON) =24.5mΩ ID=6A Application DC-DC converters Power management in portable and Battery-powered
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STL3NK40 N-channel 400 V, 4.5 Ω typ., 0.43 A, SuperMESH Power MOSFET in a PowerFLAT 5x5 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STL3NK40 400 V 5.5 Ω 0.43 A 2.5
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Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
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