3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Description OBSOLESCENCE ORDER 71V016SA. Row / Column Decoders. Sense Amps and Write Drivers

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1 3.3V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1 Features 4K x 1 advanced high-speed CMOS Static RAM Commercial ( to +7 C) and Industrial ( 4 C to +5 C) Equal access and cycle times Commercial and Industrial: 15/2 One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power coumption via chip deselect Upper and Lower Byte Enable Pi Single 3.3V (±.3V) power supply Available in 44-pin Plastic SOJ and 44-pin TSOP package. Functional Block Diagram OE A -A15 Output Enable Address s Chip Enable Description The IDT71V1 is a 1,4,57-bit high-speed Static RAM organized as 4K x 1. It is fabricated using IDT s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71V1 has an output enable pin which operates as fast as 7, with address access times as fast as. All bidirectional inputs and outputs of the IDT71V1 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V1 is packaged in a JEDEC standard 44-pin Plastic SOJ and 44-pin TSOP Type II. Write Enable Row / Column Decoders 4K x 1 Memory Array 1 See Amps and Write Drivers High Byte I/O Low Byte I/O I/O15 I/O I/O7 I/O BHE BLE Byte Enable s 3211 drw 1 2 Integrated Device Technology, Inc. 1 AUGUST 2 DSC-3211/

2 Pin Configuration Pin Description A3 A2 A1 A I/O I/O1 I/O2 I/O3 VDD Vss I/O4 I/O5 I/O I/O7 A15 A14 A13 A NC 1 A Truth Table (1) SO SO SOJ/TSOP Top View A5 A A7 OE BHE BLE I/O15 I/O14 I/O13 I/O Vss VDD I/O11 I/O1 I/O9 I/O NC A A9 A1 A11 NC 3211 drw 2 OE BLE BHE I/O-I/O7 I/O-I/O15 Function H X X X X High-Z High-Z Deselected Standby L L H L H High-Z Low Byte Read L L H H L High-Z High Byte Read L L H L L Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled NOTE: 1. H = VIH, L = VIL, X = Don't care tbl

3 Absolute Maximum Ratings (1) Symbol Rating Value Unit VTERM (2) VTERM Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND.5 to +4. V.5 to VCC+.5 V TA Operating Temperature to +7 o C TBIAS Temperature Under Bias 55 to +5 o C TSTG Storage Temperature 55 to +5 o C PT Power Dissipation 1. W IOUT DC Output Current 5 ma 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VDD terminals only. 3. Input, Output,and I/O terminals; 4.V maximum. DC Electrical Characteristics (VDD = 3.3V ±.3V, Commercial and Industrial Temperature Ranges) Capacitance Symbol Parameter Test Condition ILI Input Leakage Current VDD = Max., VIN = GND to VDD ILO Output Leakage Current VDD = Max., = VIH, VOUT = GND to VDD Recommended Operating Temperature and Supply Voltage Recommended DC Operating Conditio (TA = +25 C, f = 1.MHz, SOJ package) Symbol Parameter (1) Conditio Max. Unit Min. IDT71V1 Max. Unit 5 µa 5 µa VOL Output Low Voltage IOL = ma, VDD = Min..4 V VOH Output High Voltage IOH = 4mA, VDD = Min. 2.4 V DC Electrical Characteristics (1) (VDD = 3.3V ±.3V, VLC =.2V, VHC = VDD.2V) Symbol Parameter 3211 tbl 3 Grade Temperature GND VDD Commercial C to +7 C V 3.3V ±.3V Industrial 4 C to +5 C V 3.3V ±.3V NOTE: 1. VIL (min.) = 1.5V for pulse width less than trc/2, once per cycle tbl 4 Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage V GND Supply Voltage V VIH Input High Voltage Inputs V VIH Input High Voltage I/O 2. VDD+.3 V VIL Input Low Voltage.5 (1). V 3211 tbl 5 CIN Input Capacitance VIN = 3dV pf CI/O I/O Capacitance VOUT = 3dV 7 pf NOTE: 3211 tbl 1. This parameter is guaranteed by device characterization, but not production tested. 71V1S15 71V1S2 Com'l Ind. Com'l. Ind tbl 7 Unit ICC ISB Dynamic Operating Current ma VIL, Outputs Open, VDD = Max., f = fmax (2) Standby Power Supply Current (TTL Level) ma VIH, Outputs Open, VDD = Max., f = fmax (2) ISB1 Standby Power Supply Current (CMOS Level) VHC, Outputs Open, VDD = Max., f = (2) VIN VLC or VIN VHC 1. All values are maximum guaranteed values. 2. fmax = 1/tRC (all address inputs are cycling at fmax); f = mea no address input lines are changing ma 3211 tbl

4 AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.V V 1.5V See Figure 1, 2 and 3 AC Test Loads DATA OUT 3pF* Figure 1. AC Test Load taa, ta (Typical, ) 3.3V *Including jig and scope capacitance. Figure 2. AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz) Ω 35Ω 3211 drw tbl 9 DATA OUT 5pF* 3.3V 32Ω 35Ω 3211 drw CAPACITANCE (pf) 3211 drw Figure 3. Output Capacitive Derating.42 4

5 AC Electrical Characteristics (VDD = 3.3V ±.3V, Commercial and Industrial Temperature Ranges) 71V1S15 71V1S2 Symbol Parameter Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time 15 2 taa Address Access Time 15 2 ta Chip Select Access Time 15 2 tclz (1) Chip Select Low to Output in Low-Z 5 5 tchz (1) Chip Select High to Output in High-Z toe Output Enable Low to Output Valid 1 tolz (1) Output Enable Low to Output in Low-Z tohz (1) Output Enable High to Output in High-Z toh Output Hold from Address Change 4 5 tbe Byte Enable Low to Output Valid 1 tblz (1) Byte Enable Low to Output in Low-Z tbhz (1) Byte Enable High to Output in High-Z WRITE CYCLE twc Write Cycle Time 15 2 taw Address Valid to End of Write 1 tcw Chip Select Low to End of Write 1 tbw Byte Enable Low to End of Write 1 tas Address Set-up Time twr Address Hold from End of Write twp Write Pulse Width 1 tdw Data Valid to End of Write 1 tdh Data Hold Time tow (1) Write Enable High to Output in Low-Z 1 1 twhz (1) Write Enable Low to Output in High-Z NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. Timing Waveform of Read Cycle No. 1 (1,2,3) 3211 tbl 1 trc toh taa toh PREVIOUS VALID VALID 1. is HIGH for Read Cycle. 2. Device is continuously selected, is LOW. 3. OE, BHE, and BLE are LOW drw

6 Timing Waveform of Read Cycle No. 2 (1) trc taa toh OE BHE, BLE (2) ta tclz toe tolz (2) tbe tblz 1. is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of, BHE, or BLE traition LOW; otherwise taa is the limiting parameter. 3. Traition is measured ±2mV from steady state. tohz tchz tbhz DATA OUTVALID Timing Waveform of Write Cycle No. 1 ( Controlled Timing) (1,2,4) BHE, BLE DATAIN tas PREVIOUS DATA VALID taw (5) twhz twc (2) tcw tbw twp twr tdh tdw DATAIN VALID (5) tow (5) tchz (5) tbhz DATA VALID 3211 drw 3211 drw 9 1. A write occurs during the overlap of a LOW, LOW BHE or BLE, and a LOW. 2. OE is continuously HIGH. If during a controlled write cycle OE is LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified twp. 3. During this period, I/O pi are in the output state, and input signals must not be applied. 4. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition, the outputs remain in a high-impedance state. 5. Traition is measured ±2mV from steady state..42

7 Timing Waveform of Write Cycle No. 2 ( Controlled Timing) (1,4) twc taw tas (2) tcw tbw BHE, BLE DATAIN DATAIN VALID Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing) (1,4) BHE, BLE DATAIN tas taw twp twc (2) tcw twp 3211 drw 1 1. A write occurs during the overlap of a LOW, LOW BHE or BLE, and a LOW. 2. OE is continuously HIGH. If during a controlled write cycle OE is LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified twp. 3. During this period, I/O pi are in the output state, and input signals must not be applied. 4. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition, the outputs remain in a high-impedance state. 5. Traition is measured ±2mV from steady state. tbw tdw tdw DATAIN VALID twr tdh tdh twr 3211 drw

8 Ordering Information IDT 71V1 S XX XXX X Device Type Power Speed Package Process/ Temperature Range Blank I Y PH 15 2 Commercial ( C to +7 C) Industrial ( 4 C to +5 C) 4-mil SOJ (SO44-1) 4-mil TSOP Type II (SO44-2) Speed in nanoseconds 3211 drw.42

9 Datasheet Document History 11/1/99 Updated to new format Pg. 3 Expressed commercial and industrial ranges on DC Electrical table Pg. 5 Expressed commercial and industrial ranges on AC Electrical table Pg. Revised footnotes on Write Cycle No. 1 diagram Pg. 7 Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Pg. 9 Added Datasheet Document History /3/ Part in obsolescence, order part 71V1SA. See PDN# S-3 CORPORATE HEADQUARTERS for SALES: for Tech Support: 24 Silver Creek Valley Road or ipchelp@idt.com San Jose, CA fax: The IDT logo is a registered trademark of Integrated Device Technology, Inc. 9