IDT709099L. HIGH-SPEED 128K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

Transcription

1 Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 9/2 (max.) Industrial: 9 (max.) Low-power operation IDT709099L Active:.2W (typ.) Standby: 2.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pi Counter enable and reset features Dual chip enables allow for depth expaion without additional logic Functional Block Diagram HIGH-SPEED 28K x 8 SYHRONOUS PIPELINED DUAL-PORT STATIC RAM LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 5, 208 IDT709099L Full synchronous operation on both ports setup to clock and 0 hold on all control, data, and address inputs Data input, address, and control registers Fast 9 clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 5 cycle time, 66.7MHz operation in Pipelined output mode TTL- compatible, single 5V (±0%) power supply Industrial temperature range ( 0 C to +85 C) is available for selected speeds Available in a 00-pin Thin Quad Flatpack (TQFP) package Green parts available, see ordering information R/WL OEL R/WR OER L CEL 0 0/ 0 0/ R CER FT/PIPEL 0/ 0 0 0/ FT/PIPER I/O0L - I/O7L I/O Control I/O Control I/O0R -I/O7R A6L A0L L ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A6R A0R R ADSR CNTENR CNTRSTR 86 drw Integrated Device Technology, Inc. JANUARY 208 DSC-86/9

2 Description The IDT is a high-speed 28K x 8 bit synchronous Dual- Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT has been optimized for applicatio having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by and CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only.2w of power. Pin Configuratio (,2,3) Index A6L A5L AL A3L A2L AL A0L CNTENL L ADSL GND ADSR R CNTENR A0R AR A2R A3R AR A5R A6R A7L A8L A9L A0L AL A2L A3L AL A5L A6L VCC L CEL CNTRSTL R/WL OEL FT/PIPEL IDT709099PF 65 PN00 () PIN TQFP TOP VIEW (5) A7R A8R A9R A0R AR A2R A3R AR A5R A6R GND R CER CNTRSTR R/WR OER FT/PIPER GND. 86 drw 02 GND I/O7L I/O6L I/O5L I/OL I/O3L I/O2L GND I/OL I/O0L VCC GND I/O0R I/OR I/O2R VCC I/O3R I/OR I/O5R I/O6R I/O7R. All VCC pi must be connected to power supply. 2. All GND pi must be connected to ground. 3. Package body is approximately mm x mm x.mm. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking

3 Pin Names Left Port Right Port Names L, CEL R, CER Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A6L A0R - A6R Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output L R Clock ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VCC GND Power Ground 86 tbl 0 Truth Table I Read/Write and Enable Control (,2,3) OE CE R/W I/O0-7 Mode X H X X High-Z Deselected Power Down X X L X High-Z Deselected Power Down X L H L DATAIN Write L L H H DATAOUT Read H X L H X High-Z Outputs Disabled. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 86 tbl 02 Truth Table II Address Counter Control (,2,6) Previous Addr Address Address Used ADS CNTEN CNTRST I/O (3) Mode X X 0 X X L DI/O(0) Counter Reset to Address 0 An X An L () X H DI/O(n) External Address Utilized An Ap Ap H H H DI/O(n) External Address Blocked Counter Disabled (Ap reused) X Ap Ap + H L (5) H DI/O(n+) Counter Enable Internal Address Generation. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. and OE = VIL; CE and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.. ADS is independent of all other signals including and CE. 5. The address counter advances if CNTEN = VIL on the rising edge of, regardless of all other signals including and CE. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to eure data is not written arbitrarily. 86 tbl

4 Recommended Operating Temperature and Supply Voltage Grade Ambient GND Vcc Temperature (2) Commercial 0 O C to +70 O C 0V 5.0V + 0% Industrial -0 O C to +85 O C 0V 5.0V + 0%. This is the parameter TA. This is the "itant on" case temperature. 86 tbl 0 Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GND Ground V VIH Input High Voltage () V VIL Input Low Voltage -0.5 (2) 0.8 V. VTERM must not exceed Vcc + 0%. 2. VIL > -.5V for pulse width less than tbl 05 Absolute Maximum Ratings () Symbol Rating Commercial & Industrial VTERM (2) TBIAS TSTG IOUT Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Unit -0.5 to +7.0 V -55 to +25 o C -65 to +50 o C 50 ma Capacitance () (TA = +25 C, f =.0MHz) Symbol Parameter Conditio (2) Max. Unit CIN Input Capacitance VIN = 3dV 9 pf COUT (3) Output Capacitance VOUT = 3dV 0 pf 86 tbl 07. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. 86 tbl 06. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0% for more than 25% of the cycle time or 0 maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0%. DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.0V ± 0%) L Symbol Parameter Test Conditio Min. Max. Unit ILI Input Leakage Current () VCC = 5.5V, VIN = 0V to VCC ILO Output Leakage Current = VIH or CE = VIL, VOUT = 0V to VCC 5 µa 5 µa VOL Output Low Voltage IOL = +ma 0. V VOH Output High Voltage IOH = -ma 2. V NOTE:. At Vcc < 2.0V input leakages are undefined. 86 tbl

5 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (3) (VCC = 5V ± 0%) L9 Com'l & Ind L2 Com'l Only Symbol Parameter Test Condition Version Typ. () Max. Typ. () Max. Unit ICC ISB ISB2 ISB3 ISB Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) CEL and CER= VIL Outputs Disabled f = fmax () COM'L L ma IND L CEL = CER = VIH COM'L L ma f = fmax () IND L CE"A" = VIL and CE"B" = VIH (3) Active Port Outputs Disabled, f=fmax () Both Ports CER and CEL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0 (2) CE"A" < 0.2V and CE"B" > VCC - 0.2V (5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled, f = fmax () COM'L L ma IND L COM'L L ma IND L COM'L L ma IND L tbl 09. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of /tcyc, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 mea no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".. Vcc = 5V, TA = 25 C for Typ, and are not production tested. ICC DC(f=0) = 50mA (Typ). 5. CEX = VIL mea X = VIL and CEX = VIH CEX = VIH mea X = VIH or CEX = VIL CEX < 0.2V mea X < 0.2V and CEX > VCC - 0.2V CEX > VCC - 0.2V mea X > VCC - 0.2V or CEX < 0.2V "X" represents "L" for left port or "R" for right port

6 AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3 Max..5V.5V Figures,2 and 3 86 tbl 0 5V 5V 893Ω 893Ω DATAOUT DATAOUT 37Ω 30pF 37Ω 5pF* 86 drw 0 86 drw 05 Figure. AC Output Test load. Figure 2. Output Test Load (For tcklz, tckhz, tolz, and tohz). *Including scope and jig. tcd, tcd2 (Typical, ) pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance Capacitance (pf) 86 drw 06 Figure 3. Typical Output Derating (Lumped Capacitive Load)

7 AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (3) (VCC = 5V ± 0%=) L9 Com'l & Ind L2 Com'l Only Symbol Parameter Min. Max. Min. Max. Unit tcyc Clock Cycle Time (Flow-Through) (2) tcyc2 Clock Cycle Time (Pipelined) (2) 5 20 tch Clock High Time (Flow-Through) (2) 2 2 tcl Clock Low Time (Flow-Through) (2) 2 2 tch2 Clock High Time (Pipelined) (2) 6 8 tcl2 Clock Low Time (Pipelined) (2) 6 8 tr Clock Rise Time 3 3 tf Clock Fall Time 3 3 Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time tsd Input Data Setup Time thd Input Data Hold Time D ADS Setup Time D ADS Hold Time N CNTEN Setup Time N CNTEN Hold Time tsrst CNTRST Setup Time thrst CNTRST Hold Time toe Output Enable to Data Valid 2 2 tolz Output Enable to Output Low-Z () 2 2 tohz Output Enable to Output High-Z () 7 7 tcd Clock to Data Valid (Flow-Through) (2) tcd2 Clock to Data Valid (Pipelined) (2) 9 2 Data Output Hold After Clock High 2 2 tckhz Clock High to Output High-Z () tcklz Clock High to Output Low-Z () 2 2 Port-to-Port Delay tcwdd Write Port Clock High to Read Data Delay 35 0 tccs Clock-to-Clock Setup Time tbl. Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tcyc2, tcd2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tcyc, tcd) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL

8 Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL) (3,6) tcyc tch tcl CE () R/W (5) An An + An + 2 An + 3 DATAOUT () tcklz tcd () tckhz Qn Qn + Qn + 2 () tohz () tolz OE (2) toe 86 drw 07 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH) (3,6) tch2 tcyc2 tcl2 CE () tsb thb R/W (5) An An + An + 2 An + 3 DATAOUT ( Latency) () tcklz tcd2 Qn Qn + Qn + 2 () tohz () tolz (6) OE (2) toe. Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL and CNTRST = VIH.. The output is disabled (High-Impedance state) by = VIH or CE = VIL following the next rising edge of the clock. Refer to Truth Table. 5. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 6. 'X' here denotes Left or Right port. The diagram is with respect to that port. 86 drw

9 Timing Waveform of a Bank Select Pipelined Read (,2) tcyc2 tch2 tcl2 (B) A0 A A2 A3 A A5 A6 (B) (3) tcd2 tcd2 tckhz tcd2 DATAOUT(B) Q0 Q Q3 (3) tcklz tckhz (3) (B2) A0 A A2 A3 A A5 A6 (B2) tcd2 tckhz (3) tcd2 DATAOUT(B2) Q2 Q (3) tcklz tcklz (3) 86 drw 09 Timing Waveform of Write with Port-to-Port Flow-Through Read (,5,7) "A" R/W "A" "A" DATAIN "A" MATCH tsd thd VALID NO MATCH (6) tccs "B" tcd R/W "B" "B" MATCH NO MATCH (6) tcwdd tcd DATAOUT "B". B Represents Bank #; B2 Represents Bank #2. Each Bank coists of one IDT for this waveform, and are setup for depth expaion in this example. (B) = (B2) in this situation. 2. OE, and ADS = VIL; CE(B), CE(B2), R/W and CNTRST = VIH. 3. Traition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).. and ADS = VIL; CE and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tccs < maximum specified, then data from right port is not valid until the maximum specified for tcwdd. If tccs > maximum specified, then data from right port is not valid until tccs + tcd. tcwdd does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A" VALID VALID 86 drw 0

10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL) (3) tcyc2 tch2 tcl2 CE R/W () An An + An + 2 An + 2 An + 3 An + tsd thd DATAIN Dn + 2 tcd2 () () (2) tckhz tcklz tcd2 DATAOUT Qn Qn + 3 (5) NOP WRITE 86 drw Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled) (3) tcyc2 tch2 tcl2 CE R/W An An + An + 2 An + 3 An + An + 5 DATAIN Dn + 2 Dn + 3 tcd2 DATAOUT Qn Qn + tohz () OE () (2) tsd thd 86 drw 2. Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. and ADS = VIL; CE and CNTRST = VIH. "NOP" is "No Operation".. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. tcklz () WRITE tcd

11 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL) (3) tcyc tch tcl CE R/W () An An + An + 2 An + 2 An + 3 An + tsd thd DATAIN Dn + 2 tcd (2) tcd tcd tcd DATAOUT Qn Qn + Qn + 3 () () tckhz tcklz (5) NOP WRITE 86 drw 3. Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) (3) tcyc tch tcl CE R/W () An An + An + 2 An + 3 An + An + 5 tsd thd DATAIN Dn + 2 tcd (2) Dn + 3 toe tcd tcd DATAOUT Qn () tohz () tcklz Qn + OE WRITE 86 drw. Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. and ADS = VIL; CE and CNTRST = VIH. "NOP" is "No Operation".. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.2

12 Timing Waveform of Pipelined Read with Address Counter Advance () tcyc2 tch2 tcl2 An D D ADS D D CNTEN N N tcd2 DATAOUT Qx - (2) Qx Qn Qn + Qn + 2 (2) Qn + 3 EXTERNAL WITH COUNTER COUNTER HOLD WITH COUNTER 86 drw 5 Timing Waveform of Flow-Through Read with Address Counter Advance () tcyc tch tcl An ADS CNTEN D D D D N N tcd DATAOUT Qx (2) Qn Qn + Qn + 2 Qn + 3 (2) Qn + EXTERNAL WITH COUNTER COUNTER HOLD WITH COUNTER 86 drw 6. and OE = VIL; CE, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remai cotant for subsequent clocks

13 Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) () tcyc2 tch2 tcl2 An INTERNAL (3) An (7) An + An + 2 An + 3 An + D D ADS CNTEN tsd thd DATAIN Dn Dn + Dn + Dn + 2 Dn + 3 Dn + WRITE EXTERNAL WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 86 drw 7 Timing Waveform of Counter Reset (Pipelined Outputs) (2) tcyc2 tch2 tcl2 () An An + An + 2 INTERNAL (3) (6) Ax 0 An An + R/W ADS CNTEN tsrst thrst CNTRST tsd thd DATAIN D0 DATAOUT (5) COUNTER RESET (6) WRITE 0 0 Q0 n Q n+ Qn.. and R/W = VIL; CE and CNTRST = VIH. 2. = VIL; CE = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A or WRITE cycle may be coincidental with the counter reset cycle. 7. CNTEN = VIL advances Internal Address from An to An +. The traition shown indicates the time required for the counter to advance. The An + Address is written to during this cycle drw 8

14 A Functional Description The IDT provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH traition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applicatio. = VIL or CE = VIL for one clock cycle will power down the internal circuitry to reduce static power coumption. Multiple chip enables allow easier banking of multiple IDT709099's for depth expaion configuratio. When the Pipelined output mode is enabled, two cycles are required with = VIL and CE = VIH to reactivate the outputs. Depth and Width Expaion The IDT features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expaion with no requirements for external logic. Figure illustrates how to control the various chip enables in order to expand two devices in depth. The can also be used in applicatio requiring expanded width, as indicated in Figure. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 6-bit or wider applicatio. A7 IDT IDT Control Inputs CE VCC Control Inputs CE VCC IDT CE IDT CE Control Inputs Control Inputs Figure. Depth and Width Expaion with IDT drw 9 CNTRST ADS CNTEN R/W OE 6.2

15 Ordering Information XXXXX Device Type A Power 99 Speed A Package A A Process/ Temperature Range A Blank 8 Tube or Tray Tape and Reel Blank I () Commercial (0 C to +70 C) Industrial (-0 C to +85 C) G (2) Green PF 00-pin TQFP (PN00) 9 2 Commercial & Industrial Commercial Only Speed in nanoseconds L Low Power K (28K x 8-Bit) Synchronous Dual-Port RAM. Industrial temperature range is available. For specific other, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP drw 20 Datasheet Document History 9/30/99: Initial Public Release /0/99: Replaced IDT logo 2/22/99: Page Added missing diamond /5/0: Page 3 Changed information in Truth Table II Page Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters changed wording from "open" to "disabled" Added overbar to CE in notes Changed ±200mV to 0mV in notes Removed Preliminary status /09/0: Page 2 Added date revision for pin configuration Page 5 & 7 Added Industrial temp to column heading and values for 9 speed to DC & AC Electrical Characteristics Page 5 Added Industrial temp offering to 9 ordering information Page, 5 & 7 Removed Industrial temp footnote from all tables 6.2 5

16 Datasheet Document History (continued) 0/29/09: Page 5 Removed "IDT" from orderable part number 08/20/0: Page Added green parts availability to features Page 5 Added green indicator to ordering information Page 7 In order to correct the header notes of the AC Elect Chars Table and align them with the Industrial temp range values located in the table, the commercial TA header note has been removed Pages 8- In order to correct the footnotes of timing diagrams, CNTEN has been removed to reconcile the footnotes with the CNTEN logic definition found in Truth Table II - Address Counter Control Page Removed the 7.5 speed grade from the commercial offering Page 5 Removed the 7 speed grade from the commercial offering in the DC Electrical Characteristics table Page 7 Removed the 7 speed grade from the commercial offering in the AC Electrical Characteristics table Page 5 Removed the 7 speed grade from the commercial offering in the ordering information 0/08/5: Page Numbers for Piplined Output Mode updated: includes clock to data out, cycle time and operation Page 2 Removed IDT in reference to fabrication Page 2 &6 The package code PN00- changed to PN00 to match standard package codes Page 6 Corrected typo in the Typical Output Derating(Lumped Capitive Load) diagram 0/2/8: Page 6 Added Tape and Reel to Ordering Information Product Discontinuation Notice - PDN# SP-7-02 Last time buy expires June 5, 208 CORPORATE HEADQUARTERS for SALES: for Tech Support: 602 Silver Creek Valley Road or San Jose, CA 9538 fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc