HIGH-SPEED 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM. LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

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1 Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 6.5/7.5/9 (max.) Industrial: 7.5 (max.) Low-power operation IDT79359/9L Active: 95mW (typ.) Standby:.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pi Counter enable and reset features Dual chip enables allow for depth expaion without additional logic HIGH-SPEED 8/K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT79359/9L LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 5, 8 Full synchronous operation on both ports 3.5 setup to clock and hold on all control, data, and address inputs Data input, address, and control registers Fast 6.5 clock to data out in the Pipelined output mode Self-timed write allows fast cycle time cycle time, MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility TTL- compatible, single 5V (±%) power supply Industrial temperature range ( C to +85 C) is available for 83 MHz Available in a -pin Thin Quad Flatpack (TQFP) package Green parts available, see ordering informaiton Functional Block Diagram L UBL R UBR CEL CEL / / CER CER LBL OEL LBR OER FT/PIPEL b b / a a b a a a a b b b / FT/PIPER I/O9L-I/O7L I/OL-I/O8L I/O Control I/O Control I/O9R-I/O7R I/OR-I/O8R AL () AL L ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. AR () AR R ADSR CNTENR CNTRSTR 5633 drw NOTE:. A is a NC for IDT Integrated Device Technology, Inc. FEBRUARY 8 DSC-5633/5

2 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Description The IDT79359/9 is a high-speed 8/K x 8 bit synchronous Dual- Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT79359/9 has been optimized for applicatio having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE and CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 95mW of power. Pin Configuratio (,,3,) Index A8L A7L A6L A5L AL A3L AL AL AL CNTENL L ADSL ADSR R CNTENR AR AR AR A3R AR A5R A6R A7R A9L AL AL AL () NC NC NC LBL UBL CEL CEL CNTRSTL L OEL VCC FT/PIPEL I/O7L I/O6L I/O5L I/OL I/O3L I/OL I/OL I/OL /9PF PN (5) Pin TQFP 3 63 Top View (6) A8R A9R AR AR AR () NC NC NC LBR UBR CER CER CNTRSTR R OER FT/PIPER I/O7R I/O6R I/O5R I/OR I/O3R I/OR I/OR I/O9L I/O8L VCC I/O7L I/O6L I/O5L I/OL I/O3L I/OL I/OL I/OL I/OR I/OR I/OR I/O3R I/OR I/O5R I/O6R VCC I/O7R I/O8R I/O9R I/OR 5633 drw. A is a NC for IDT All VCC pi must be connected to power supply. 3. All pi must be connected to ground.. Package body is approximately mm x mm x.mm 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.

3 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Pin Names Left Port Right Port Names CEL, CEL CER, CER Chip Enables (3) L R Read/Write Enable OEL OER Output Enable AL - AL () AR - AR () Address I/OL - I/O7L I/OR - I/O7R Data Input/Output L R Clock UBL UBR Upper Byte Select () LBL LBR Lower Byte Select () ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VCC Power (5V). A is a NC for IDT LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE are single buffered when FT/PIPE = VIL, CEo and CE are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. Ground (V) 5633 tbl Truth Table I Read/Write and Enable Control (,,3) OE CE (5) CE (5) UB () LB () Upper Byte I/O9-7 Lower Byte I/O-8 X H X X X X High-Z High-Z Deselected Power Down X X L X X X High-Z High-Z Deselected Power Down X L H H H X High-Z High-Z Both Bytes Deselected X L H L H L DATAIN High-Z Write to Upper Byte Only X L H H L L High-Z DATAIN Write to Lower Byte Only X L H L L L DATAIN DATAIN Write to Both Bytes L L H L H H High-Z Read Upper Byte Only L L H H L H High-Z Read Lower Byte Only L L H L L H Read Both Bytes H X L H X X X High-Z High-Z Outputs Disabled. "H" = VIH, "L" = VIL, "X" = Don't Care.. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signa. LB and UB are single buffered regardless of state of FT/PIPE. 5. CEo and CE are single buffered when FT/PIPE = VIL. CEo and CE are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. Mode 5633 tbl 6. 3

4 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Truth Table II Address Counter Control (,) Previous Internal External Internal Address Address Address Used ADS CNTEN CNTRST I/O (3) MODE An X An L () X H DI/O (n) External Address Used X An An + H L (5) H DI/O(n+) Counter Enabled Internal Address generation X An + An + H H H DI/O(n+) External Address Blocked Counter disabled (An + reused) X X A X X L () DI/O() Counter Reset to Address. "H" = VIH, "L" = VIL, "X" = Don't Care.. CE, LB, UB, and OE = VIL; CE and = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.. ADS and CNTRST are independent of all other signals including CE, CE, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of, regardless of all other signals including CE, CE, UB and LB tbl 3 Recommended Operating Temperature and Supply Voltage () Grade Ambient Vcc Temperature () Commercial O C to +7 O C V 5.V + % Industrial - O C to +85 O C V 5.V + % 5633 tbl. Industrial temperature: for specific speeds, packages and powers contact your sales office.. This is the parameter TA. This is the "itant on" case temperature. Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V Ground V VIH Input High Voltage. 6. () V VIL Input Low Voltage -.5 ().8 V. VTERM must not exceed Vcc + %.. VIL > -.5V for pulse width less than tbl 5 Absolute Maximum Ratings () Symbol Rating Commercial & Industrial VTERM () TBIAS TSTG IOUT Terminal Voltage with Respect to Temperature Under Bias Storage Temperature DC Output Current Unit -.5 to +7. V -55 to +5 o C -65 to +5 o C 5 ma Capacitance () (TA = +5 C, f =.MHz) Symbol Parameter Conditio () Max. Unit CIN Input Capacitance VIN = 3dV 9 pf COUT (3) Output Capacitance VOUT = 3dV pf 5633 tbl 7. These parameters are determined by device characterization, but are not production tested.. 3dV references the interpolated capacitance when the input and output switch from V to 3V or from 3V to V. 3. COUT also references CI/O tbl 6. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability.. VTERM must not exceed Vcc + % for more than 5% of the cycle time or maximum, and is limited to < ma for the period of VTERM > Vcc + %. 6.

5 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.V ± %) 79359/9L Symbol Parameter Test Conditio Min. Max. Unit ILI Input Leakage Current () VCC = 5.5V, VIN = V to VCC ILO Output Leakage Current CE = VIH or CE = VIL, VOUT = V to VCC 5 µa 5 µa VOL Output Low Voltage IOL = +ma. V VOH Output High Voltage IOH = -ma. V NOTE:. At Vcc <.V input leakages are undefined tbl 8 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (3) (VCC = 5V ± %) 79359/9L6 Com'l Only 79359/9L7 Com'l & Ind 79359/9L9 Com'l Only Symbol Parameter Test Condition Version Typ. () Max. Typ. () Max. Typ. () Max. Unit ICC ISB ISB ISB3 ISB Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) CEL and CER= VIL Outputs Disabled f = fmax () COM'L L ma IND L CEL = CER = VIH COM'L L ma f = fmax () IND L CE"A" = VIL and CE"B" = VIH (3) Active Port Outputs Disabled, f=fmax () Both Ports CER and CEL > VCC -.V VIN > VCC -.V or VIN <.V, f = () CE"A" <.V and CE"B" > VCC -.V (5) VIN > VCC -.V or VIN <.V, Active Port Outputs Disabled, f = fmax () COM'L L ma IND L _ COM'L L ma IND L _.5 3. COM'L L ma IND L _ tbl 9. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of /tcyc, using "AC TEST CONDITIONS" at input levels of to 3V.. f = mea no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".. Vcc = 5V, TA = 5 C for Typ, and are not production tested. ICC DC(f=) = 5mA (Typ). 5. CEX = VIL mea CEX = VIL and CEX = VIH CEX = VIH mea CEX = VIH or CEX = VIL CEX <.V mea CEX <.V and CEX > VCC -.V CEX > VCC -.V mea CEX > VCC -.V or CEX <.V "X" represents "L" for left port or "R" for right port. 6. 5

6 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load to 3.V Max..5V.5V Figures, and tbl 5V 5V 893Ω 893Ω 37Ω 3pF 37Ω 5pF* 5633 drw 5633 drw 5 Figure. AC Output Test load. Figure. Output Test Load (For tcklz, tckhz, tolz, and tohz). *Including scope and jig. tcd, tcd (Typical, ) pf is the I/O capacitance of this device, and 3pF is the AC Test Load Capacitance Capacitance (pf) 5633 drw 6 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6. 6

7 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (3) (VCC = 5V ± %) 79359/9L6 Com'l Only 79359/9L7 Com'l & Ind 79359/9L9 Com'l Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tcyc Clock Cycle Time (Flow-Through) () 9 5 tcyc Clock Cycle Time (Pipelined) () 5 tch Clock High Time (Flow-Through) () tcl Clock Low Time (Flow-Through) () tch Clock High Time (Pipelined) () 5 6 tcl Clock Low Time (Pipelined) () 5 6 tr Clock Rise Time tf Clock Fall Time Address Setup Time 3.5 Address Hold Time Chip Enable Setup Time 3.5 Chip Enable Hold Time Byte Enable Setup Time 3.5 Byte Enable Hold Time Setup Time 3.5 Hold Time tsd Input Data Setup Time 3.5 thd Input Data Hold Time D ADS Setup Time 3.5 D ADS Hold Time N CNTEN Setup Time 3.5 N CNTEN Hold Time tsrst CNTRST Setup Time 3.5 thrst CNTRST Hold Time toe Output Enable to Data Valid tolz Output Enable to Output Low-Z () tohz Output Enable to Output High-Z () tcd Clock to Data Valid (Flow-Through) () 5 8 tcd Clock to Data Valid (Pipelined) () Data Output Hold After Clock High tckhz Clock High to Output High-Z () tcklz Clock High to Output Low-Z () Port-to-Port Delay tcwdd Write Port Clock High to Read Data Delay 8 35 tccs Clock-to-Clock Setup Time tbl. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure ). This parameter is guaranteed by device characterization, but is not production tested.. The Pipelined output parameters (tcyc, tcd) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tcyc, tcd) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL. 6. 7

8 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL) (3,7) tcyc tch tcl CE CE UB, LB (5) An An+ An+ An+3 () tcklz tcd () tckhz Qn Qn + Qn + () tohz () tolz OE () toe 5633 drw 7 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH) (3,7) tch tcyc tcl CE CE () UB, LB (6) (5) An An + An + An + 3 ( Latency) () tcklz tcd Qn Qn + Qn + () tohz () tolz (6) OE () toe. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure ).. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH.. The output is disabled (High-Impedance state) by CE = VIH, CE = VIL, following the next rising edge of the clock. Refer to Truth Table. 5. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of for Qn + would be disabled (High-Impedance state). 7. "X" here denotes Left or Right port. The diagram is with respect to that port drw 8

9 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Timing Waveform of a Bank Select Pipelined Read (,) tcyc tch tcl (B) A A A A3 A A5 A6 CE(B) (3) tcd tcd tckhz tcd (B) Q Q Q3 (3) tcklz (3) tckhz (B) A A A A3 A A5 A6 CE(B) tcd tckhz (3) tcd (B) Q Q (3) tcklz tcklz (3) 5633 drw 9 Timing Waveform of Write with Port-to-Port Flow-Through Read (,5,7) "A" "A" "A" DATAIN "A" MATCH tsd thd VALID NO MATCH (6) tccs "B" tcd "B" "B" MATCH NO MATCH (6) tcwdd tcd "B". B Represents Bank #; B Represents Bank #. Each Bank coists of one IDT79359/9 for this waveform, and are setup for depth expaion in this example. (B) = (B) in this situation.. UB, LB, OE, and ADS = VIL; CE(B), CE(B),, CNTEN, and CNTRST = VIH. 3. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure ).. CE, UB, LB, and ADS = VIL; CE, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tccs < maximum specified, then data from right port is not valid until the maximum specified for tcwdd. If tccs > maximum specified, then data from right port is not valid until tccs + tcd. tcwdd does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A" VALID VALID 5633 drw

10 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL) (3) tcyc tch tcl CE CE UB, LB () An An + An + An + An + 3 An + tsd thd DATAIN Dn + tcd () () () tckhz tcklz tcd Qn Qn + 3 (5) NOP WRITE 5633 drw Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled) (3) tcyc tch tcl CE CE UB, LB An An + An + An + 3 An + An + 5 DATAIN Dn + Dn + 3 tcd Qn Qn + tohz () OE () () tsd thd 5633 drw. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure ).. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE, UB, LB, and ADS = VIL; CE, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. tcklz () WRITE tcd 6.

11 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL) (3) tcyc tch tcl CE CE UB, LB () An An + An + An + An + 3 An + tsd thd DATAIN Dn + tcd () tcd tcd tcd Qn Qn + Qn + 3 () () tckhz tcklz (5) NOP WRITE 5633 drw 3 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) (3) tcyc tch tcl CE CE UB, LB () An An + An + An + 3 An + An + 5 tsd thd DATAIN Dn + tcd () Dn + 3 toe tcd tcd Qn () tohz () tcklz Qn + OE WRITE 5633 drw. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure ).. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE, UB, LB, and ADS = VIL; CE, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.

12 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Timing Waveform of Pipelined Read with Address Counter Advance () tcyc tch tcl An D D ADS D D CNTEN N N tcd Qx - () Qx Qn Qn + Qn + () Qn + 3 EXTERNAL WITH COUNTER COUNTER HOLD WITH COUNTER 5633 drw 5 Timing Waveform of Flow-Through Read with Address Counter Advance () tcyc tch tcl An ADS CNTEN D D D D N N tcd Qx () Qn Qn + Qn + Qn + 3 () Qn + EXTERNAL WITH COUNTER COUNTER HOLD WITH COUNTER 5633 drw 6. CE, OE, UB, and LB = VIL; CE,, and CNTRST = VIH.. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remai cotant for subsequent clocks. 6.

13 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) () tcyc tch tcl An INTERNAL (3) An (7) An + An + An + 3 An + D D ADS CNTEN tsd thd DATAIN Dn Dn + Dn + Dn + Dn + 3 Dn + WRITE EXTERNAL WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 5633 drw 7 Timing Waveform of Counter Reset (Pipelined Outputs) () tcyc tch tcl () An An + An + INTERNAL (3) (6) Ax An An + ADS CNTEN tsrst thrst CNTRST tsd thd DATAIN D (5) COUNTER RESET (6) WRITE Q n Q n+ Qn.. CE, UB, LB, and = VIL; CE and CNTRST = VIH.. CE, UB, LB = VIL; CE = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A or WRITE cycle may be coincidental with the counter reset cycle. 7. CNTEN = VIL advances Internal Address from An to An +. The traition shown indicates the time required for the counter to advance. The An + Address is written to during this cycle drw 8

14 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM A Functional Description The IDT79359/9 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH traition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applicatio. CE = VIH or CE = VIL for one clock cycle will power down the internal circuitry to reduce static power coumption. Multiple chip enables allow easier banking of multiple IDT79359/9's for depth expaion configuratio. When the Pipelined output mode is enabled, two cycles are required with CE = VIL and CE = VIH to re-activate the outputs. Depth and Width Expaion The IDT79359/9 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expaion with no requirements for external logic. Figure illustrates how to control the various chip enables in order to expand two devices in depth. The IDT79359/9 can also be used in applicatio requiring expanded width, as indicated in Figure. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36-bit or wider applicatio. A3/A () IDT79359/9 CE IDT79359/9 CE Control Inputs CE VCC Control Inputs CE VCC IDT79359/9 CE IDT79359/9 CE CE CE Control Inputs Control Inputs 5633 drw 9 Figure. Depth and Width Expaion with IDT79359/9 CNTRST ADS CNTEN LB, UB OE NOTE:. A3 is for IDT79359, A is for IDT

15 IDT79359/9L High-Speed 8/K x 8 Synchronous Pipelined Dual-Port Static RAM Ordering Information XXXXX Device Type A Power 99 Speed A Package A A Process/ Temperature Range A Blank 8 Tube or Tray Tape & Reel Blank I () Commercial ( C to +7 C) Industrial (- C to +85 C) G () Green PF -pin TQFP (PN) Commercial Only Commercial & Industrial Commercial Only Speed in nanoseconds L Low Power K (8K x 8-Bit) Synchronous Dual-Port RAM 7K (K x 8-Bit) Synchronous Dual-Port RAM. Contact your local sales office for industrial temp range for other speeds, packages and powers.. Green parts available. For specific speeds, packages and powers contact your sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP drw Datasheet Document History 7/8/: Initial Public Release 8/8/3: Removed Preliminary status Page 6 Added IDT Clock Solution Table //8: Page6 Removed "IDT" from orderable part number 5//5: Page Added green availability to Features Page Removed -pin fine pitch Ball Grid Array fpbga offering from Features Page Removed IDT in reference to fabrication Page 3 The package code PN- changed to PN to match standard package codes Page 3 Removed the date for the PN-pin TQFP configuration Page Removed the -pin fine pitch Ball Grid Array fpbga configuration and corresponding footnotes Page 5 Corrected typo in footnote text Page 7 Corrected typo in the Typical Output Derating drawing Page 8 Removed the commercial temp range from the AC Elec Chars Read & Write Cycle Timing table title Page 5 Added Tape & Reel and Green indicators with their footnote annotatio to the Ordering Information Page 5 Removed the -pin TQFP fpbga from the Ordering Information Page 5 Removed IDT Clock table /8/8: Product Discontinuation Notice - PDN# SP-7- Last time buy expires June 5, 8 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6 Silver Creek Valley Road or San Jose, CA 9538 fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6. 5