HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM

Transcription

1 Features Architecture based on Dual-Port SRAM cells Allows full simultaneous access from both ports High-speed clock-to-data output times Commercial: /0/2 (max.) Industrial: 0 (max.) Low-power operation IDT0949S Active: 500mW (typ.) Standby: 5mW (typ.) 4K X 9 bits 3 cycle time, MHz operation in pipeline mode Self-timed write allows for fast cycle times Functional Block Diagram HIGH-SPEED 3K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 5, 20 IDT0949S Synchronous operation 4 setup to clock, hold on all control, data, and address inputs Data input, address, and control registers Fast clock to data out TTL-compatible, single 5V (±0%) power supply Clock Enable feature Guaranteed data output hold times Industrial temperature range ( 40 C to +5 C) is available for selected speeds Green parts available, see ordering information I/O0-L REGISTER WRITE LOGIC MEMORY YARRAY ARRAY SENSE AMPS DECODER DECODER WRITE LOGIC SENSE AMPS REGISTER 0 0/ I/O0-R FT/PIPEDR OEL CLKL REG en REG en OER CLKR CLKENL CLKENR R/WL REG Selftimed Write Logic Selftimed Write Logic REG R/WR CEL A0L-AL A0R-AR CER 3494 drw 0 20 Integrated Device Technology, Inc. FEBRUARY 20 DSC-3494

2 IDT0949S Description The IDT0949 is a high-speed 4K x 9 bit synchronous Dual-Port SRAM. The memory array is based on Dual-Port memory cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up and hold times. The timing latitude provided by this approach will allow systems to be designed with very short cycle times. This device has been optimized for applicatio having unidirectional data flow or bi-directional data flow in bursts, by utilizing input data registers. The IDT0949 utilizes a 9-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applicatio where it is necessary to use a parity bit for tramission/ reception error checking. Fabricated using CMOS high-performance technology, these Dual- Ports typically operate on only 00mW of power at maximum high-speed clock-to-data output times as fast as. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT0949 is packaged in an 0-pin TQFP. Pin Configuratio (,2,3) Reference A5L A4L A3L A2L AL A0L CLKENL CLKL CLKR CLKENR A0R AR A2R A3R A4R A5R AR AL AL AL A9L A0L AL OEL VCC VCC R/WL N/ C CEL I/OL I/OL I/OL IDT0949PF PN0 (4) 0-Pin TQFP Top View (5) I/O5L VCC I/O4L I/O3L I/O2L I/OL I/O0L I/O0R I/OR I/O2R I/O3R VCC I/O4R I/O5R AR AR A9R A0R AR OER FT/PIPEDR R/WR CER I/OR I/OR I/OR 3494 drw 02. All VCC pi must be connected to power supply. 2. All ground pi must be connected to ground supply. 3. Package body is approximately 4mm x 4mm x.4mm. 4, This package code is used to reference the package diagram. 5. This text does not indicate the orientaion of the actual part-marking..42 2

3 IDT0949S Absolute Maximum Ratings () Symbol Rating Commercial & Industrial VTERM (2) Terminal Voltage with Respect to Unit -0.5 to +.0 V VTERM (2) Terminal Voltage -0.5 to VCC V TBIAS TSTG Temperature Under Bias Storage Temperature -55 to +25 o C -5 to +50 o C IOUT DC Output Current 50 ma Maximum OperatingTemperature and Supply Voltage () Grade Ambient Temperature Vcc Commercial 0 O C to +0 O C 0V 5.0V + 0% Industrial -40 O C to +5 O C 0V 5.0V + 0% 3494 tbl 02. This is the parameter TA. This is the "itant on" case temperature tbl 0. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0% for more than 25% of the cycle time or 0 maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0%. Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V Ground V VIH Input High Voltage (2) V VIL Input Low Voltage -0.5 () 0. V Capacitance (TA = +25 C, f =.0MHz) Symbol Parameter Conditio Max. Unit CIN Input Capacitance VIN = 3dV pf COUT Output Capacitance VOUT = 3dV 9 pf 3494 tbl 04. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.. VIL > -.5V for pulse width less than VTERM must not exceed Vcc + 0% tbl 03 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 0%) 0949S Symbol Parameter Test Conditio Min. Max. Unit ILI Input Leakage Current () VCC = 5.5V, VIN = 0V to VCC ILO Output Leakage Current VOUT = 0V to VCC 0 µa 0 µa VOL Output Low Voltage IOL = +4mA 0.4 V VOH Output High Voltage IOH = -4mA 2.4 V NOTE:. At VCC < 2.0V, input leakages are undefined 3494 tbl

4 IDT0949S DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (4) (VCC = 5V ± 0%) 0949S Com'l Only 0949S0 Com'l & Ind 0949S2 Com'l Only Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit ICC Dynamic Operating Current (Both Ports Active) CEL and CER = VIL, Outputs Disabled f = fmax () COM'L ma IND ISB Standby Current (Both Ports - TTL Level Inputs) CEL and CER = VIH COM'L ma f = fmax () IND 90 5 ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH (3) Active Port Outputs Disabled, f=fmax () COM'L ma IND ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs) CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0 (2) COM'L ma IND 5 20 ISB4 Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V (3) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled, f = fmax () COM'L ma IND tbl 0. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of /tclk, using "AC TEST CONDITIONS" at input levels of to 3V. 2. f = 0 mea no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25 C for Typ, and are not production tested. ICC DC = 50mA (Typ). AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATAOUT 34Ω 5V 93Ω 30pF 3494 drw 03 Figure. AC Output Test load. DATAOUT to 3.0V 3 Max..5V.5V Figures,2 and 3 34Ω 5V 3494 tbl 0 93Ω 5pF*, 3494 drw 04 Figure 2. Output Test Load (For tcklz, tckhz, tolz, and tohz). *Including scope and jig. tcd (Typical, ) pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance Capacitance (pf) 3494 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load).,.424

5 IDT0949S AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) 0949S Com'l Only 0949S0 Com'l & Ind 0949S2 Com'l Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tcyc Clock Cycle Time (Flow-Through) (3) tcyc2 Clock Cycle Time (Pipelined) (3) 3 5 tch Clock High Time (Flow-Through) (3) tcl Clock Low Time (Flow-Through) (3) tch2 Clock High Time (Pipelined) (3) tcl2 Clock Low Time (Pipelined) (3) tcd Clock to Data Valid (Flow-Through) (3) tcd2 Clock to Data Valid (Pipelined) (3) 0 2 Registered Signal Set-up Time Registered Signal Hold Time tdc Data Output Hold After Clock High tcklz Clock High to Output Low-Z (,2) tckhz Clock High to Output High-Z (,2) 9 toe Output Enable to Output Valid 0 tolz Output Enable to Output Low-Z (,2) tohz Output Disable to Output High-Z (,2) 9 CK Clock Enable, Disable Set-Up Time CK Clock Enable, Disable Hold Time tcwdd Write Port Clock High to Read Data Delay Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The Pipelined output parameters (tcyc2, tcd2) always apply to the Left Port. The Right Port uses the Pipelined tcyc2 and tcd2 when FT/PIPEDR = VIH and the Flow- Through parameters (tcyc, tcd) when FT/PIPEDR = VIL tbl

6 IDT0949S Timing Waveform of Read Cycle for Flow-Through Output on Right Port (FT/PipedR = VIL) tcyc CLK tch tcl CK CK CK CLKEN CE R/W ADDRESS An An + An + 2 An + 3 tcd tdc () tckhz DATAOUT OE () tcklz Qn Qn + Qn + () tohz () tolz toe 3494 drw 0 Timing Waveform of Left Port Write to Flow-Through Right Port Read (FT/PipedR = VIL) (2,3) CLK "L" R/W "L" ADDR "L" MATCH NO MATCH DATA IN "L" VALID VALID CLK "R" tccs R/W "R" ADDR "R" MATCH NO MATCH tcwdd tcd DATA OUT "R" VALID tdc VALID 3494 drw 0. Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CEL = CER = VIL, CLKENL = CLKENR = VIL 3. OE = VIL for the reading port, port 'R'..42

7 IDT0949S Timing Waveform of Read Cycle for Pipelined Operation (Left Port; Right Port when FT/PipedR = VIH) (3) tch2 tcyc2 tcl2 CLK CE R/W ADDRESS An An + An + 2 An + 3 ( Latency) tcd2 tdc tcd2 DATAOUT () tcklz Qn Qn + Qn + 2 () tohz () tolz OE (2). Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. CLKENL and CLKENR = VIL. toe 3494 drw 0.42

8 IDT0949S Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL) CLK tcyc2 tch2 tcl2 CE R/W ADDRESS An An + An + 2 An + 2 An + 3 An + 4 DATAIN Dn + 2 tcd2 () () (2) tckhz tcklz tcd2 DATAOUT Qn Qn + 3 (3) READ NOP WRITE READ 3494 drw 09 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled) tcyc2 tch2 tcl2 CLK CE R/W ADDRESS An An + An + 2 An + 3 An + 4 An + 5 DATAIN Dn + 2 Dn + 3 tcd2 (2) tcklz () tcd2 DATAOUT Qn Qn + 4 OE tohz () READ WRITE READ 3494 drw 0. Traition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity..42

9 IDT0949S Functional Description The IDT0949 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is dependent only on the low to high traitio of the clock signal to initiate a write allowing the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applicatio. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power coumption. When piplelined mode is enabled, two cycles are required with CE LOW to reactivate the outputs. Truth Table I: Read/Write Control () Inputs Outputs Synchronous (3) Asynchronous CLK CE R/W OE I/O0- Mode H X X High-Z Deselected Power Down L L X DATAIN Selected and Write Enable L H L DATAOUT Read Selected and Data Output Enabled Read ( Latency) X X H High-Z Data I/O Disabled 3494 tbl 09 Truth Table II: Clock Enable Function Table () Inputs Register Inputs Register Outputs (4) Operating Mode CLK (3) CLKEN (2) ADDR DATAIN ADDR DATAOUT Load "" L H H H H Load "0" L L L L L Hold (do nothing) H X X NC NC X H X X NC NC 3494 tbl 0. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock traition, 'L' = LOW voltage level steady state 'l' = LOW voltage level one set-up time prior to the LOW-to-HIGH clock traition, 'X' = Don't care, 'NC' = No change 2. CLKEN = VIL must be clocked in during Power-Up. 3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOWto-HIGH traition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH traistion of the CLK. 4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN..42 9

10 IDT0949S Ordering Information XXXX Device Type A Power 999 Speed A Package A A Process/ Temperature Range A Blank Tube or Tray Tape and Reel Blank I () Commercial (0 C to +0 C) Industrial (-40 C to +5 C) G (2) Green PF 0-pin TQFP (PN0) 0 2 Commercial Only Commercial & Industrial Commercial Only Speed in nanoseconds S Standard Power. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP--02 Datasheet Document History 3//99: Initiated datasheet document history Converted to new format Cosmetic and typographical correctio Added additional notes to pin configuratio /3/99: Changed drawing format 9//99: Removed Preliminary /0/99: Replaced IDT logo 5/24/00: Page 3 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes 0/24/02: Page 2 Added date revision for pin configuration Page 3, 4 & 5 Removed Industrial temp footnote from all tables Page 4 Added Industrial temp to 0 speed in the column heading and values of DC Electrical Characteristics Page 5 Corrected a typo in the column heading of AC Electrical Characteristics Page 5 Added Industrial temp to 0 speed in the column heading of AC Electrical Characteristics Page 0 Added Industrial temp to 0 offering in ordering information Pages & 0 Replaced TM logo with logo 0/29/09: Page 0 Removed "IDT" from orderable part number 04/0/5: Page 2 Removed IDT in reference to fabrication Page 2 &0 The package code PN0- changed to PN0 to match standard package codes 02/02/: Page 4 Corrected typo in the Typical Output Derating(Lumped Capitive Load) diagram Page 0 Added Tape and Reel and Green indicators with their footnote annotatio to the Ordering Information Product Discontinuation Notice - PDN# SP--02 Last time buy expires June 5, 20 CORPORATE HEADQUARTERS for SALES: for Tech Support: 024 Silver Creek Valley Road or San Jose, CA 953 fax: DualPorelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc K (4K x 9-Bit) Synchronous Pipelined Dual-Port RAM 3494 drw