IDT70V9359/49L. HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

Transcription

1 HIGH-SPEED 3.3V 8/K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT7V9359/9L Features: True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 6.5/7.5/9 (max.) Industrial: 7.5 (max.) Low-power operation IDT7V9359/9L Active: 5mW (typ.) Standby:.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pi Counter enable and reset features Dual chip enables allow for depth expaion without additional logic Functional Block Diagram Full synchronous operation on both ports 3.5 setup to clock and hold on all control, data, and address inputs Data input, address, and control registers Fast 6.5 clock to data out in the Pipelined output mode Self-timed write allows fast cycle time cycle time, MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±.3V) power supply Industrial temperature range ( C to +85 C) is available for 83 MHz Available in a -pin Thin Quad Flatpack (TQFP) and - pin Fine Pitch Ball Grid Array (fpbga) packages Green parts available, see ordering information L UBL R UBR CEL CEL / / CER CER LBL OEL LBR OER FT/PIPEL b b / a a b a a a b b a b / FT/PIPER I/O9L-I/O7L I/OL-I/O8L I/O Control I/O Control I/O9R-I/O7R I/OR-I/O8R A2L () AL L ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A2R () AR R ADSR CNTENR CNTRSTR NOTE:. A2 is a NC for IDT7V drw JULY 2 2 Integrated Device Technology, Inc. DSC-5638/5

2 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Description: The IDT7V9359/9 is a high-speed 8/K x 8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT7V9359/9 has been optimized for applicatio having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE and CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT s CMOS high-performance technology, these devices typically operate on only 5mW of power. Pin Configuratio (,2,3,) 7/3/2 Index A8L A7L A6L A5L AL A3L A2L AL AL CNTENL L ADSL VSS ADSR R CNTENR AR AR A2R A3R AR A5R A6R A7R A9L AL AL A2L () NC NC NC LBL UBL CEL CEL CNTRSTL L OEL FT/PIPEL I/O7L I/O6L VSS I/O5L I/OL I/O3L I/O2L I/OL I/OL V9359/9PF PN- (5) -Pin TQFP Top View (6) A8R A9R AR AR A2R () NC NC NC LBR UBR CER CER CNTRSTR R VSS OER FT/PIPER I/O7R VSS I/O6R I/O5R I/OR I/O3R I/O2R I/OR. I/O9L I/O8L I/O7L I/O6L I/O5L I/OL I/O3L I/O2L VSS I/OL I/OL VSS I/OR I/OR I/O2R I/O3R I/OR I/O5R I/O6R I/O7R I/O8R I/O9R I/OR 5638 drw 2. A2 is a NC for IDT7V All pi must be connected to power supply. 3. All VSS pi must be connected to ground supply.. Package body is approximately mm x mm x.mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking

3 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Pin Configuratio(cont'd) (,2,3,) 7V9359/9BF BF (5) 7/3/2 -Pin fpbga Top View (6) A A8R A2 AR A3 UBR A CNTRSTR A5 A6 A7 A8 A9 I/O3R I/OR A I/O7R B A6R B2 A7R B3 AR B A2R () B5 R B6 OER B7 B8 PL/FTR I/O2R B9 I/O9R B I/O6R C A3R C2 AR C3 A5R C A9R C5 CER C6 I/O6R C7 I/O5R C8 I/OR C9 I/O7R C I/O3R D AR D2 R D3 AR D A2R D5 LBR D6 CER D7 I/OR D8 I/O8R D9 I/O5R D I/OR E E2 ADSR E3 E CNTENR AL E5 ADSL E6 E7 I/OR E8 I/O2R E9 I/OR E F F2 L F3 AL F A3L F5 F6 F7 F8 I/O2L F9 I/OL F I/OL G CNTENL G2 AL H H2 A2L A6L G3 A7L H3 AL G UBL G5 G6 I/O3L H H5 H6 CEL CNTRSTL I/O5L G7 NC H7 I/O9L G8 I/OL H8 I/O7L G9 H9 I/O6L G I/O3L H I/O5L, J A5L J2 A9L J3 J A2L () L J5 OEL J6 J7 PL/FTL I/O2L J8 I/OL J9 J I/O8L K A8L K2 AL K3 LBL K CEL K5 K6 K7 I/O6L K8 I/OL K9 I/OL K I/O7L 5638 drw 3. A2 is a NC for IDT7V All pi must be connected to power supply. 3. All VSS pi must be connected to ground supply.. Package body is approximately mm x mm x.mm with.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking

4 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Pin Names Left Port Right Port Names CEL, CEL CER, CER Chip Enables (3) L R Read/Write Enable OEL OER Output Enable AL - A2L () AR - A2R () Address I/OL - I/O7L I/OR - I/O7R Data Input/Output L R Clock UBL UBR Upper Byte Select (2) LBL LBR Lower Byte Select (2) ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through / Pipeline VSS Power (3.3V) Ground (V) NOTE:. A2 is a NC for IDT7V LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE are single buffered when FT/PIPE = VIL, CEo and CE are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect tbl Truth Table I Read/Write and Enable Control (,2,3) OE CE (5) CE (5) UB () LB () Upper Byte Lower Byte MODE I/O9-7 I/O-8 X H X X X X High-Z High-Z Deselected Power Down X X L X X X High-Z High-Z Deselected Power Down X L H H H X High-Z High-Z Both Bytes Deselected X L H L H L DATAIN High-Z Write to Upper Byte Only X L H H L L High-Z DATAIN Write to Lower Byte Only X L H L L L DATAIN DATAIN Write to Both Bytes L L H L H H DATAOUT High-Z Read Upper Byte Only L L H H L H High-Z DATAOUT Read Lower Byte Only L L H L L H DATAOUT DATAOUT Read Both Bytes H X L H X X X High-Z High-Z Outputs Disabled 5638 tbl 2. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. LB and UB are single buffered regardless of state of FT/PIPE. 5. CEo and CE are single buffered when FT/PIPE = VIL. CEo and CE are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. 6.2

5 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Truth Table II Address Counter Control (,2) Previous Internal External Internal Address Address Address Used ADS CNTEN CNTRST I/O (3) MODE An X An L () X H DI/O (n) External Address Used X An An + H L (5) H DI/O(n+) Counter Enabled Internal Address generation X An + An + H H H DI/O(n+) External Address Blocked Counter disabled (An + reused) X X A X X L () DI/O() Counter Reset to Address. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE, LB, UB, and OE = VIL; CE and = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.. ADS and CNTRST are independent of all other signals including CE, CE, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of, regardless of all other signals including CE, CE, UB and LB tbl 3 Recommended Operating Temperature and Supply Voltage Grade Ambient Temperature () GND Commercial O C to +7 O C V 3.3V +.3V Industrial - O C to +85 O C V 3.3V +.3V. This is the parameter TA. This is the "itant on" case temperature tbl Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit Supply Voltage V VSS Ground V VIH Input High Voltage V (2) V VIL Input Low Voltage -.3 ().8 V. VIL > -.5V for pulse width less than. 2. VTERM must not exceed +.3V tbl 5 Absolute Maximum Ratings () Symbol Rating Commercial Unit & Industrial Terminal Voltage -.5 to +.6 V with Respect to GND VTERM (2) TBIAS TSTG Temperature Under Bias Storage Temperature -55 to +25 o C -65 to +5 o C IOUT DC Output Current 5 ma 5638 tbl 6. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed +.3V for more than 25% of the cycle time or maximum, and is limited to < 2mA for the period of VTERM > +.3V. Capacitance () (TA = +25 C, f =.MHZ) Symbol Parameter Conditio (2) Max. Unit CIN Input Capacitance VIN = 3dV 9 pf COUT (3) Output Capacitance VOUT = 3dV pf 5638 tbl 7. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from V to 3V or from 3V to V. 3. COUT also references CI/O

6 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ( = 3.3V ±.3V) 7V9359/9L Symbol Parameter Test Conditio Min. Max. Unit ILI Input Leakage Current () = 3.6V, VIN = V to ILO Output Leakage Current CE = VIH or CE = VIL, VOUT = V to 5 µa 5 µa VOL Output Low Voltage IOL = +ma. V VOH Output High Voltage IOH = -ma 2. V NOTE:. At < 2.V input leakages are undefined tbl 8 DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (3) ( = 3.3V ±.3V) 7V9359/9L6 Com'l Only 7V9359/9L7 Com'l & Ind 7V9359/9L9 Com'l Only Symbol Parameter Test Condition Version Typ. () Max. Typ. () Max. Typ. () Max. Unit IDD Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fmax () COM'L L ma IND L ISB Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH f = fmax () COM'L L ma IND L 8 ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH (5) Active Port Outputs Disabled, f=fmax () COM'L L ma IND L 5 8 ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > -.2V, VIN > -.2V or VIN <.2V, f = (2) COM'L L ma IND L.5 3. ISB Full Standby Current (One Port - CMOS Level Inputs) CE"A" <.2V and CE"B" > -.2V (5) VIN > -.2V or VIN <.2V, Active Port, Outputs Disabled, f = fmax () COM'L L ma IND L tbl 9. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of /tcyc, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = mea no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".. = 3.3V, TA = 25 C for Typ, and are not production tested. ICC DC(f=) = 9mA (Typ). 5. CEX = VIL mea CEX = VIL and CEX = VIH CEX = VIH mea CEX = VIH or CEX = VIL CEX <.2V mea CEX <.2V and CEX > -.2V CEX > -.2V mea CEX > -.2V or CEX <.2V "X" represents "L" for left port or "R" for right port

7 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.V 2 Max..5V.5V Figures, 2, and tbl 3.3V 3.3V 59Ω 59Ω DATAOUT DATAOUT 35Ω 3pF 35Ω 5pF* Figure. AC Output Test load drw 5638 drw 5 Figure 2. Output Test Load (For tcklz, tckhz, tolz, and tohz). *Including scope and jig. tcd, tcd2 (Typical, ) pf is the I/O capacitance of this device, and 3pF is the AC Test Load Capacitance Capacitance (pf) 5638 drw 6. Figure 3. Typical Output Derating (Lumped Capacitive Load)

8 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (3) ( = 3.3V ±.3V) 7V9359/9L6 Com'l Only 7V9359/9L7 Com'l & Ind 7V9359/9L9 Com'l Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tcyc Clock Cycle Time (Flow-Through) (2) tcyc2 Clock Cycle Time (Pipelined) (2) 2 5 tch Clock High Time (Flow-Through) (2) tcl Clock Low Time (Flow-Through) (2) tch2 Clock High Time (Pipelined) (2) 5 6 tcl2 Clock Low Time (Pipelined) (2) 5 6 tr Clock Rise Time tf Clock Fall Time Address Setup Time 3.5 Address Hold Time Chip Enable Setup Time 3.5 Chip Enable Hold Time tsb Byte Enable Setup Time 3.5 thb Byte Enable Hold Time Setup Time 3.5 Hold Time tsd Input Data Setup Time 3.5 thd Input Data Hold Time D ADS Setup Time 3.5 D ADS Hold Time N CNTEN Setup Time 3.5 N CNTEN Hold Time tsrst CNTRST Setup Time 3.5 thrst CNTRST Hold Time toe Output Enable to Data Valid tolz Output Enable to Output Low-Z () tohz Output Enable to Output High-Z () tcd Clock to Data Valid (Flow-Through) (2) tcd2 Clock to Data Valid (Pipelined) (2) Data Output Hold After Clock High tckhz Clock High to Output High-Z () tcklz Clock High to Output Low-Z () Port-to-Port Delay tcwdd Write Port Clock High to Read Data Delay tccs Clock-to-Clock Setup Time 9 5. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tcyc2, tcd2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tcyc, tcd) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL tbl 6.2 8

9 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL) (3,7) tcyc tch tcl CE CE tsb thb UB, LB tsb thb (5) DATAOUT (2) OE An An + An + 2 An + 3 () tcd tckhz Qn Qn + Qn + 2 () () tcklz tohz () tolz toe 5638 drw 7 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH) (3,7) tch2 tcyc2 tcl2 CE CE () UB, LB tsb thb tsb (6) thb (5) An An + An + 2 An + 3 DATAOUT ( Latency) () tcklz tcd2 Qn Qn + Qn + 2 () tohz () tolz (6) OE (2) 5638 drw 8. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL and CNTRST = VIH.. The output is disabled (High-Impedance state) by CE = VIH, CE = VIL following the next rising edge of the clock. Refer to Truth Table. 5. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "X' here denotes Left or Right port. The diagram is with respect to that port. toe 6.2 9

10 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of a Bank Select Pipelined Read (,2) tcyc2 tch2 tcl2 (B) A A A2 A3 A A5 A6 CE(B) (3) tcd2 tcd2 tckhz tcd2 DATAOUT(B) Q Q Q3 (3) (3) tcklz tckhz (B2) A A A2 A3 A A5 A6 CE(B2) tcd2 tckhz (3) tcd2 DATAOUT(B2) Q2 Q (3) tcklz tcklz (3) 5638 drw 9 Timing Waveform with Port-to-Port Flow-Through Read (,5,7) "A" "A" "A" DATAIN "A" MATCH tsd thd VALID NO MATCH (6) tccs "B" tcd "B" "B" MATCH NO MATCH (6) tcwdd tcd DATAOUT "B" 6.2 VALID VALID 5638 drw. B Represents Bank #; B2 Represents Bank #2. Each Bank coists of one IDT7V9359/9 for this waveform, and are setup for depth expaion in this example. (B) = (B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE(B), CE(B2), and CNTRST = VIH. 3. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure 2).. CE, UB, LB, and ADS = VIL; CE and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tccs < maximum specified, then data from right port is not valid until the maximum specified for tcwdd. If tccs > maximum specified, then data from right port is not valid until tccs + tcd. tcwdd does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".

11 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL) (3) tcyc2 tch2 tcl2 CE CE tsb thb UB, LB () An An + An + 2 An + 2 An + 3 An + tsd thd DATAIN Dn + 2 tcd2 () () (2) tckhz tcklz tcd2 DATAOUT Qn Qn + 3 (5) NOP WRITE 5638 drw Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled) (3) tcyc2 tch2 tcl2 CE CE UB, LB tsb thb An An + An + 2 An + 3 An + An + 5 DATAIN Dn + 2 Dn + 3 tcd2 DATAOUT Qn Qn + tohz () OE () (2) tsd 5638 drw 2. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE, UB, LB, and ADS = VIL; CE and CNTRST = VIH. "NOP" is "No Operation".. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. thd tcklz () WRITE tcd2 6.2

12 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL) (3) tcyc tch tcl CE CE UB, LB tsb thb () An An + An + 2 An + 2 An + 3 An + tsd thd DATAIN Dn + 2 tcd tcd tcd tcd (2) DATAOUT Qn Qn + Qn + 3 () () tckhz tcklz (5) NOP WRITE 5638 drw 3 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) (3) tcyc tch tcl CE CE tsb thb UB, LB () An An + An + 2 An + 3 An + An + 5 tsd thd DATAIN Dn + 2 tcd (2) Dn + 3 toe tcd tcd DATAOUT Qn () tohz () tcklz Qn + OE WRITE 5638 drw. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE, UB, LB, and ADS = VIL; CE and CNTRST = VIH. "NOP" is "No Operation".. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity

13 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Pipelined Read with Address Counter Advance () tcyc2 tch2 tcl2 An D D ADS D D CNTEN N N tcd2 DATAOUT Qx - (2) Qx Qn Qn + Qn + 2 (2) Qn + 3 EXTERNAL WITH COUNTER COUNTER HOLD WITH COUNTER 5638 drw 5 Timing Waveform of Flow-Through Read with Address Counter Advance () tcyc tch tcl An D D ADS D D N N CNTEN tcd DATAOUT Qx (2) Qn Qn + Qn + 2 Qn + 3 (2) Qn + EXTERNAL WITH COUNTER COUNTER HOLD WITH COUNTER 5638 drw 6. CE, OE, UB, and LB = VIL; CE,, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remai cotant for subsequent clocks

14 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) () tcyc2 tch2 tcl2 An INTERNAL (3) An (7) An + An + 2 An + 3 An + D D ADS CNTEN (7) tsd thd DATAIN Dn Dn + Dn + Dn + 2 Dn + 3 Dn + WRITE EXTERNAL WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 5638 drw 7 Timing Waveform of Counter Reset (Pipelined Outputs) (2) tcyc2 tch2 tcl2 () An An + An + 2 INTERNAL (3) (6) Ax An An + ADS CNTEN tsrst thrst D D N N CNTRST DATAIN tsd D thd DATAOUT (5) COUNTER RESET (6) WRITE Q n Q n drw 8. CE, UB, LB, and = VIL; CE and CNTRST = VIH. 2. CE, UB, LB = VIL; CE = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.. Addresses do not have to be accessed sequentially since ADS = VIL cotantly loads the address on the rising edge of the ; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A or WRITE cycle may be coincidental with the counter reset cycle. ADDR will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from An to An +. The traition shown indicates the time required for the counter to advance. The An + Address is written to during this cycle. Qn 6.2

15 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Functional Description The IDT7V9359/9 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH traition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applicatio. CE = VIL and CE = VIH for one clock cycle will power down the internal circuitry to reduce static power coumption. Multiple chip enables allow easier banking of multiple IDT7V9359/9's for depth expaion configuratio. When the Pipelined output mode is enabled, two cycles are required with CE = VIL and CE = VIH to re-activate the outputs. Depth and Width Expaion The IDT7V9359/9 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expaion with no requirements for external logic. Figure illustrates how to control the varioius chip enables in order to expand two devices in depth. The IDT7V9359/9 can also be used in applicatio requiring expanded width, as indicated in Figure. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36-bit or wider applicatio. A3/A2 () IDT7V9359/9 CE IDT7V9359/9 CE Control Inputs CE Control Inputs CE IDT7V9359/9 CE IDT7V9359/9 CE CE CE Control Inputs Control Inputs 5638 drw 9 Figure. Depth and Width Expaion with IDT7V9359/9 CNTRST ADS CNTEN LB, UB OE NOTE:. A3 is for IDT7V9359, A2 is for IDT7V

16 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Ordering Information XXXXX A 99 A A A Device Type Power Speed Package Process/ Temperature Range Blank I () Commercial ( C to+7 C) Industrial (- C to+85 C) G (2) Green PF BF -pin TQFP (PN-) -pin fpbga (BF) Commercial Only Commercial & Industrial Commercial Only Speed in nanoseconds L Low Power, 7V9359 7V939 K (8K x 8-Bit) Synchronous Dual-Port RAM 72K (K x 8-Bit) Synchronous Dual-Port RAM 5638 drw 2 NOTE:. Contact your local sales office for Industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your sales office. IDT Clock Solution for IDT7V9359/9 Dual-Port IDT Dual-Port Part Number Dual-Port I/O Speciticatio Voltage I/O Input Capacitance Clock Specificatio Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance 7V9359/9 3.3 LVTTL 9pF % 5ps IDT PLL Clock Device IDT235 IDT238 IDT239 IDT Non-PLL Clock Device FCT385 FCT385D/E FCT387 FCT387D/E 5638 tbl

17 IDT7V9359/9L High-Speed 3.3V 8/K x 8 Dual-Port Synchronous Pipelined Static RAM Datasheet Document History //: Initial Public Release 7/3/2: Pages 2 & 3 Added data revision for pin configuratio Coolidated multiple devices into one datasheet 8/5/3: Removed Preliminary status Page 6 Added IDT Clock Solution Table /29/9: Page 6 Removed "IDT" from orderable part number 7/26/: Page Added green parts availability to features Page 6 Added green indicator to ordering information Page 8 In order to correct the header notes of the AC Elect Chars Table and align them with the Industrial temp range values located in the table, the commercial TA header note has been removed Pages 9-2 In order to correct the footnotes of timing diagrams, CNTEN has been removed to reconcile the footnotes with the CNTEN logic definition found in Truth Table II - Address Counter Control CORPORATE HEADQUARTERS for SALES: for Tech Support: 62 Silver Creek Valley Road or San Jose, CA 9538 fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc